KR910005974B1 - Non-volatilization semiconductor memory - Google Patents

Abstract

The memory equips the data correction memans which is tested easily. The memory comprises means generating the hamming parity code with the unti of the word or byte corresponding to each address, means storing the parity code corresponding to the input data into the memory cell, means decoding the data and parity bits after reading them, and means separating the memory cell, the error correction circuit, and other circuits each other.

Description

Nonvolatile Semiconductor Memory with Error Correcting Means

1 is an overall block diagram showing an embodiment of the present invention.

2 is a block diagram showing a circuit activated when data is written in the present invention.

3 is an embodiment of the code generation circuit diagram of the present invention.

4 is a block diagram showing a circuit that is activated when data is read in the present invention.

5 is an embodiment of a decoding circuit and a correction roll of the present invention.

6 is a test flowchart of a nonvolatile memory incorporating error correction means in this invention.

7 is an embodiment of a data selection circuit of this invention.

8 is a block diagram showing a circuit activated during a test of the code generation circuit of the present invention.

9 is a time chart of the code generation circuit test of the present invention.

10 is an embodiment of an input buffer, an output buffer, and a code generation detection control circuit of the present invention.

11 is an embodiment of the error generating circuit of this invention.

* Explanation of symbols for main parts of the drawings

1: Array 2, 3: Address buffer

4: decoder 5: data line selector

6: input / output unit 7: output buffer

8: Code generation detection control circuit 9: Input buffer

10: correction circuit 11: data selection circuit

12: decoding circuit 13: code generating circuit

14: sense amplifier 15: error generating circuit

16: error bit position selection circuit

Ex1, Ex2 ... E1, E2 ...: Exclusive Oagate

Bk0-Bk3: blocks 11, 12 ... IM: inverter

NA1, NA2, ... NAM: NANDGATE NB1, NB2 ...: NANDGATE

The present invention relates to a nonvolatile semiconductor memory having error correction means. As the conventional nonvolatile semiconductor memory becomes more integrated than other memories, the internal cell is a bit problem, and due to the problem of high reliability and yield, the non-volatile semiconductor memory is corrected by error correction code. It was necessary to improve the reliability problem and the yield caused by the bitness failure.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problem of reliability and improve the yield due to a bit error by providing a data correction means by an error correction code in a nonvolatile semiconductor memory.

It is another object of the present invention to provide a means for facilitating a test of a nonvolatile semiconductor memory with error correction means.

The error correction means of the nonvolatile semiconductor memory allows data input at the time of data write and parity generated by the input data to be written in the memory cell, and data and parity at the time of data read. Means for decoding by means and means for correcting errors. The means to be tested includes a memory cell tester for pure data bits, a memory cell test code generation circuit test for parity bits, and means for independently performing testers of the decoding circuit and the correction circuit without corrective action. .

A feature of the present invention constitutes a means for generating an error correction parity code in units of words or bytes corresponding to each address in a nonvolatile semiconductor memory, and writes input data into a cell for data bits when data is written. And means for writing a parity code corresponding to the input data into the cell, and means for simultaneously reading and decoding data bits and parity bits at read time so as to correct errors occurring in units of words or bytes. It is in one. Another feature is that the memory cell array, the error correction circuit, and the other circuits provide a means for separating them from each other so that they can be individually verified.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is an overall block diagram showing an embodiment of the present invention, and FIG. 1a shows an EEPROM as an array 1 of MN-byte memory cells. This EEPROM consists of an X-column address buffer (2) and a Y-axis address buffer (3) and is connected to the data line selector (5) via a decoder (4) to write and read data to memory cells in the array (1). do.

FIG. 1B shows an embodiment of error correction means connected to the EEPROM of FIG. 1A, which is an example used in N lines of Weedline (W0-Wn-1) and M-byte (B0-Bm-1) memory cells. Indicates. Here, one byte is composed of eight data memory cells and four parity bit memory cells, and is composed of a total of 12 memory cells. The error correcting code uses an error check of 1 bit and a correction code of 1 bit and can be applied to the present invention as another correction code. (B) shows an input buffer (B) through the input / output unit (6). 9) and the output buffer 7 is connected, and the code generation detection control circuit 8 is connected between the input and output buffers (9) (7). The input buffer 9 is connected to the error generating circuit 15 to one side through a data line and is connected to the code generating circuit 13 to supply a parity signal generated according to the input data and the input data. The sense amplifier 14 connected to the code generation circuit 13 supplies data at the time of reading and is connected to the correction circuit 10 through the data selection circuit 11 and of the decoding circuit 12 connected to the code generation circuit 13. The output is coupled to the correction circuit 10 and configured to correct an errored bit.

The circuit has a configuration connected to the second drawing when data writes and a configuration connected to the fourth drawing when data reading.

The operation of writing data will be described with reference to FIGS. 2 and 3.

2 is a block diagram of a circuit that is activated when data is written, and FIG. 3 shows an embodiment of a code issuing circuit.

First, when eight input data DIi are input through the input buffer 7 connected to the input / output circuit 6, four parity codes PWi are generated in the code generation circuit 13 by the eight input data. The eight input data DIi and the parity code PWi through the code generation circuit 13 are stored in the memory array 1 via the data line selector 5.

3 shows an embodiment of a code generation circuit, in which a block BK0 composed of an exclusive burner gate EX1-EX5 is connected to eight data lines D / L and four parity lines P / L. The blocks BK1-BK3 also have the same structure. MOS transistors MOS are connected to each parity line P / L to be controlled by the clock signal C1.

In other words, since the clock signal C1 is supplied as the logic H state and the MOS transistor MOS is turned on, the four parity lines P / L are maintained at the logic L level, and the data of the data lines D / L are maintained. The parity codes Pw0-Pw3 are generated by operating with the extruder oragates of each block BK0-BK3 and written to the array 1 together with the eight input data DIi as described above.

The data read operation is described with reference to FIGS. 4 and 5.

FIG. 4 is a block diagram of a circuit activated during data read, and FIG. 5 shows an embodiment of a decoder and a corrector. When data is read, data and a parity code designated to the memory array 1 are output through the data line selector 5 and the output detected by the sense amplifier 14 is transmitted to the data selection circuit 11 and the code generation circuit 13. Delivered.

)이 로직 L상태이면 낸드게이트(NA1-NAM) 및 인버터(I1-IM)로 구성된 복호회로의 출력을 항상 L상태가 되어 복호회로(13)는 디스에이블되므로 정정자기용이 일어나지 않게된다.The code generation circuit 13 outputs four parity codes as input 12-bit signals, and supplies a parity signal decoded by the decoding circuit 12 to the correction circuit 10 so that an error occurs among the eight data. Is corrected (inverted) to be delivered to the output buffer 7 and an error data signal is immediately transmitted to the output buffer 7 to draw out the corrected data through the input / output circuit 6. Here, the code generation circuit 13 is the same circuit as that in FIG. And the control signal of the decoding circuit 12 in FIG.

If the L is in the logic L state, the output of the decoding circuit composed of the NAND gates NA1-NAM and the inverters I1-IM is always in the L state, and the decoding circuit 13 is disabled so that corrective magnetic use does not occur.

)은 보통 데이터리드시 H상태가 된다. 정정회로(10)는 익스크루시버 오아게이트(E1-EM)로 구성되어 있는 것으로 일측입력은 센스앰프(14)에 연결되어 있고 타측입력은 복호회로(12)의 인버터(O1-IM)의 출력측과 연결되어 있다.However, the control signal (

) Is usually H when data read. The correction circuit 10 is composed of an extruder oragate (E1-EM), with one input connected to the sense amplifier 14 and the other input connected to the output side of the inverter O1-IM of the decoding circuit 12. Connected with

Here, the output of the decoding circuit 12 serves as a control signal. When the output of the decoding circuit is in the L state, the sensed output is passed as it is. When the output of the decoding circuit is in the logic H state, the sensed output is inverted. Passed. Eight data bits and four parity bits are sensed through the sense amplifier 14 and the sensed output generates a sign in the code generation circuit. The generated code passes through the decoding circuit 12 to determine whether there is an error and the location of the data bit in which the error occurred. When one error of the eight data Dsi occurs, the output of the decoding circuit corresponding to the position becomes H state, whereby the data in which the error occurs is corrected (inverted) and passed, and finally the output buffer 7 ), The corrected byte of data is read.

According to the present invention, when a memory device is manufactured and tested in this manner, if there is a defect (a hardware error) of a 1-bit memory cell in one byte, the read data is corrected by an error correction circuit. This defect cannot be found and apparently there is no error. Therefore, in order to completely perform various tests on the nonvolatile semiconductor memory to which the error correction function is added, it is necessary to independently test the memory cell code generation circuit, the decoding circuit, and the correction circuit, respectively. In particular, in a nonvolatile semiconductor memory, the write time is long (a few ms), and too much time is required to directly write and read data to check the error correction circuit.

This invention is provided with the means which can fully implement the above-mentioned various tests. 6 shows a test flow chart of a nonvolatile semiconductor memory incorporating error correction means in this invention. There are three main test methods.

First, how to disable error correction and check pure memory cells (memory cells for data bits and memory cells for parity bits)

Second, a method of separating the code generation circuit 13 from the array 1 and inspecting the code generation circuit 13 itself.

Thirdly, it is a method of inspecting the protection circuit and the correction circuit and finding the correction effect by forcibly generating the 1-bit error at a desired position and storing the read data in the array.

(1) memory cell test

)을 로직 L상태로 두어 먼저 데이터 정정동작을 중지시키고, 제7도의 데이터선택회로(11)는 , 콘트롤시그널(

)(

)를 양입력으로 하는 낸드게이트(NB1)와, 콘트롤시그널(

)(

)에 의해 선택되는 패리티부호(PRi)(Psi)와, 상기 낸드게이트(NB1)의 출력을 양입력으로 하는 낸드게이트(NB3)와, 상기 낸드게이트(NB1)의 출력을 인버팅시킨 신호와 8개의 데이터(Dsi)를 양입력으로 하는 낸드케이트(NB2)와, 상기 낸드게이트(NB2)(NB3)의 출력을 양입력으로하여 선택신호를 출력하는 낸드게이트(NB4)로 이루어졌다. 이 데이터 선택회로에서 콘트롤시그널(H2)이 L상태가 되면 8개의 데이터(Dsi)가 선택되므로 1바이트중 데이터비트용 8개의 메모리 셀을 정정작용없이 검사한다. 만약 콘트롤시그널(

)이 로직 L상태이면 4개의 패리티부로(Psi)가 선택되고 출력버퍼(7)중 4개를 통해 패리티비트용 셀을 검사할 수 있다.To test a pure memory cell, first the control signal of the decoding circuit 12 shown in FIG.

) Is placed in the logic L state to stop the data correction operation first, and the data selection circuit 11 of FIG.

) (

), The NAND gate (NB1) having both inputs, and the control signal (

) (

Parity code PRi (Psi) selected by the < RTI ID = 0.0 >),< / RTI > a NAND gate NB3 having the output of the NAND gate NB1 as a positive input, and a signal inverting the output of the NAND gate NB1. NAND gate NB2 having two data Dsi as positive inputs, and NAND gate NB4 outputting a selection signal using the outputs of the NAND gate NB2 NB3 as positive inputs. In the data selection circuit, when the control signal H2 is in the L state, eight data Dsi are selected, so eight memory cells for data bits in one byte are checked without corrective action. If control signal (

In the logic L state, four parity units Psi are selected, and the cells for parity bits can be checked through four of the output buffers 7.

(2) Code generation circuit test

)은 로직 L상태가 되고 어레이(1)는 주변회로들과 분리되며 부호발생 검출제어회로(8)가 활성화 된다. 그리고 콘트롤시그널(

)에 의해 데이터 선택회로(11)에서 4개의 패리티부호(PRi)를 선택하고 4개의 출력버퍼(7)에 입력시키고 콘트롤시그널(

)은 L상태가 되어 복호회롤를 디스에이블시켜 에러정정작용을 중지시킨다. 이를 제10도의 타이밍도로서 살펴보면 콘트롤시그널(

)이 L상태에서는 출력버퍼(7)가 인에이블되어 데이터가 읽혀지고, H상태에서는 디스에이블되고 I/O패드와 출력버퍼(7)가 차단된다.The test of the code generation circuit 13 will be described with reference to FIG. 8, FIG. 9, and FIG. FIG. 8 is a block diagram of a circuit that is activated during a code generation circuit test. FIG. 9 shows an embodiment of an input buffer 9, an output buffer 7, and a code generation detection control circuit 8. FIG. A timing diagram of the operation. Control signal during test of code generation circuit

) Becomes the logic L state, the array 1 is separated from the peripheral circuits, and the sign generation detection control circuit 8 is activated. And control signal (

4 selects the parity codes PRi from the data selection circuit 11 and inputs them to the four output buffers 7 and the control signal.

) Becomes L state, which disables the decoding circuit roll and stops error correction. Looking at this as the timing diagram of FIG. 10, the control signal (

In the L state, the output buffer 7 is enabled and data is read. In the H state, the output buffer 7 is disabled and the I / O pad and the output buffer 7 are blocked.

)에 L상태 구간동안 발생된 부호를 출력버퍼(7)를 통해 패드에서 읽혀지게 되고 콘트롤시그널(C2)의 라이징에지에서 래치를 풀고 다른 입력데이타를 받아들이게 된다.Then, the control signal C2 generated by the code generation detection control circuit 8 latches the data entered into the input buffer 9 for L and releases the latch in the H state. After about 100 ns from the rising edge of the control signal OE, the data entered into the input buffer 9 is latched. By this data, the code is generated in the code generator circuit and the control signal (

The code generated during the L state period is read from the pad through the output buffer 7, and the latch is released from the rising edge of the control signal C2 to accept another input data.

The code generation circuit 13 can be tested by checking the code generated by each input data by such a series of control.

Here, C3 and C4 are internal clock signals, the control signal C3 is in the H state, and the control signal C4 is in the L state during the code generation circuit test.

(3) Decoding circuit, correction path and error correction operation test

In the test, a sign is generated by the input data, and when writing the input data and the sign to the memory cell, the data is forcibly written as opposed to the input data, such that an arbitrary bit error occurs among the eight data bits. The error correction operation is checked and the code circuit and the correction circuit are checked by reading the data while the error correction circuit is enabled. The shift operation will be described with reference to FIG. 11, which is an embodiment of the error generating circuit 15. FIG.

)은 H상태가 되어 에러비트위치 선정회로(16)의 출력은 항상 L상태가 되고, 이에 따라 입력버퍼(9)를 통해 들어온 입력데이타(DIi)는 인버터되지 않고 그대로 전달되어 정상적인 입력데이타가 메모리 셀에 쓰여지게 된다.In FIG. 11, data DIi, which is input through the input buffer 9, is input to one side input of the exclusive oragate, and an output of the error bit positioning circuit 16 is supplied to the other input. Normal control signal (

) Is in the H state, and the output of the error bit position selection circuit 16 is always in the L state. As a result, the input data DIi input through the input buffer 9 is transferred without being inverter, and the normal input data is stored in memory. Will be written to the cell.

However, during the test, the control signal H4 is in the L state and an arbitrarily select 1 bit of the eight input data by the error bit positioning input (addresses A0-A2). That is, one of the eight outputs of the error bit positioning circuit is in the H state and the remaining seven outputs are in the L state.

This input data is inverted and written to the memory cell as if an error occurred. However, as shown in FIG. 1, a sign must be generated by input data before an error occurs, and data in which an error occurs when writing a memory cell is recorded. The read access time when the decoding circuit and the correction circuit are tested and the data error is detected and corrected by forcibly generating an error at any data position in one byte and checking the corrective action with the error correction circuit enabled. In general, the access time is slightly slower when performing a corrective action.

As described above, the present invention provides a nonvolatile semiconductor memory with data correction means by an error correction code to solve the bit fault, thereby improving convergence and reliability, and independently performing functional tests of various circuits. It is effective to verify effectively.

Claims (8)

Means for generating an error correction parity code in units of words or bytes corresponding to each address in a nonvolatile semiconductor memory, and means for writing input data into a cell for data bits when writing data, and input data for Means for writing a corresponding parity code into a cell, and means for simultaneously reading and decoding data bits and parity bits at the time of reading and having error correction means for correcting errors occurring in units of words or bytes. Nonvolatile Semiconductor Memory. 2. The apparatus of claim 1, wherein the error correction means comprises: a code generation circuit 13 for generating a parity code corresponding to the data, and a decoded output connected to the code generation circuit 13 and supplied to the pruning circuit 10; A nonvolatile semiconductor memory having an error correction means configured by a decoding circuit (12) and an error generating circuit (15) which causes an error of one bit of data supplied through an input buffer (9). 3. The code generator circuit 13 is composed of a parity ranin (P / L) connected to a data line (D / L) and a transistor, and according to an error correcting code, the transceiver oragate (EX1-EX5). Non-volatile semiconductor memory having error correction means configured to be connected to the block (Bk0-Bk2) consisting of. A means for constructing a nonvolatile memory cell array 1 and an error correction circuit and separating the code generation circuit 13, the decoding circuit 12, and the error generation circuit 15 of the error correction circuit, respectively. And error correction means having means for verifying each of the partial circuits of the error correction circuit individually. 5. The apparatus according to claim 4, wherein the means for verifying each partial circuit of the error correction circuit comprises: an input buffer 9 that accepts input data and a code that generates a code by data input through the input buffer 9; An anisotropic semiconductor memory having an error correcting means comprising a generating circuit 13 and a closed loop of an output buffer 7 for outputting each generated code to the outside. 5. The device according to claim 4, wherein the means for verifying each circuit of the error correction circuit selects data read out from the memory cell and data generated from the code generation circuit 13 by the control signals H1 and H2. A non-volatile semiconductor memory comprising error correction means characterized in that it combines with a data selection circuit (11) to be passed through. 5. The nonvolatile semiconductor memory according to claim 4, comprising an error generating circuit (15) capable of controlling the occurrence of an error in the error correction circuit so as to control the position of the bit where an error occurs by an input address. 7. The control circuit according to claim 6, wherein the data selection circuit (11) comprises a control signal.

) (

), The NAND gate (NB1) having both inputs, and the control signal (

) (

NAND gate NB3 having the parity code PRi (Psi) and the output of the NAND gate NB1 selected as the two inputs, and an inverted signal of the NAND gate NB1 and eight signals. And a NAND gate NB2 having the data Dsi as a positive input, a NAND gate NB4 outputting a selection signal with the outputs of the NAND gates NB2 and NB3 being positive inputs, and Nonvolatile memory having error correction means.

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