KR910005237Y1 - Fade control circuit - Google Patents

Abstract

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Description

Fade control circuit of video equipment

1 is an implementation circuit diagram of the present invention.

2 is another embodiment of the present invention.

3 is a voltage waveform diagram in each part of FIG. 1;

* Explanation of symbols for main parts of the drawings

1: blanking signal input terminal 2: fade control unit

R1-R7: Resistor C, C ': Capacitor

SW, SW ': Fade-out switch VR: Variable resistor for fade voltage setting

TR: Transistor

The present invention provides a smooth operation of the FADE-IN and FADE-OUT functions in a video device that records a video signal using an image sensor such as a video camera or a camcorder. And a blanking signal mixed with the fade control signal to eliminate the pelsnoise and the interference.

In a conventional video device, a blanking pulse is input to a video processing IC to blank a series of completed video signals, thereby generating noise and mutual interference due to the pulse input, and ignoring voltage fluctuations during fading out. Because it lowers to OV, it takes a long time before the screen appears when fading in.

The purpose of the present invention is to reduce the fading control voltage at the time of fade-out only to the voltage level at which the screen disappears, in order to solve such an end, to shorten the time the screen appears during fade-in, fade control from the outside of the video processing IC A fade control circuit that mixes the blanking signal directly with the voltage and maintains this fade control voltage at OV during the blanking period to perform blanking to prevent noise and interference due to blanking pulse input to the video processing IC. As to provide a, when the present invention will be described in detail by the accompanying drawings as follows.

As shown in FIG. 1, the blanking signal input terminal 1 is connected to the base terminal of the transistor TR through the resistor R1, and the collector terminal of which the emitter terminal of the transistor TR is grounded is faded. In the known art by connecting the control signal to the output terminal 3 and the variable resistor VR for fade voltage setting, the voltage divider R2-R4 in the fade control unit 2 for dividing the Vcc voltage is connected in series. Ground, the connection point of the resistors R3 and R4 is connected to the fade out switch SW having one end grounded, and the connection point of the resistors R2 and R3 is set via the integrating capacitor C. It is configured by connecting to the variable resistance VR.

FIG. 2 is another embodiment of the fade control unit 2 of FIG. 1, which is connected to the connection point of the voltage divider resistor R5 and R6 for dividing the Vcc voltage through an integrated capacitor C 'having one end grounded. At the same time, the variable resistor VR for setting the fade voltage is connected and the resistor R7 having one end connected to the ground is connected through the fade out switch SW '.

Referring to the effect of the present invention configured in this way in detail as follows.

First, the voltage at point X after sufficient time has passed when the fade out switch SW is " off " is set to a constant voltage (Δ) set to a value of Vcc X R1 / (R2 + R3) as in the previous part of FIG. V1 + DELTA VO is maintained, and this voltage is divided to the required voltage by the fade voltage setting variable VR to be applied to the collector of the transistor TR.

On the other hand, when the fade out switch SW is "on", the voltage at the point X is a voltage ΔVO having a constant time t1 in FIG. 3a by the integrating capacitor C and having a value of Vcc × R1 / R2. The reason for not making the fade out voltage completely OV is that the video signal output falls to the pedestal level even if the fade control voltage is lowered to a certain level. If you do, you will have to wait for some time until you actually see the video output when you fade in by turning the fade out switch (SW) off.

On the other hand, the blanking signal input to the blanking signal input terminal 1 has a pulse shape as shown in FIG. The fading control voltage output to the signal output terminal 3 becomes OV to perform a blanking function. When this pulse falls to the "low" level, the transistor Q1 is "off" and the variable resistor for setting the fade voltage ( The fading control voltage applied through VR) is output to the fade control signal output terminal 3.

Therefore, the blanking characteristic is created by controlling the fading control voltage by the blanking signal without inputting the blanking signal to the video processing IC, thereby preventing noise and signal interference due to the blanking signal input to the video processing IC. .

In FIG. 3A, P1 and P2 represent the "on" time and the "off" time of the fade out switch SW, respectively, and ΔV1 is the voltage that falls after the "on" of the fade out switch SW, Δ VO represents the voltage maintained in the fade out state, and t2 represents the voltage rise time when the fade out switch SW is " off ".

3C shows the fade control voltage waveform measured at point y as described above, and the voltage of ΔV2 is set to the state of the variable resistor VR or fade out switch SW for setting the fade voltage of FIG. It shows the voltage fluctuation that varies accordingly.

2 shows another embodiment of the fade control unit 2. The fade voltage setting variable resistor is set by the resistors R6 and R7 in parallel connection when the fade-out switch SW 'is turned on. This reduces the phenomenon of impedance differences between the (VR) and fade control stages.

As described above, the present invention processes the blanking signal by mixing the fading control voltage with the blanking signal to make it OV during the blanking period, thereby preventing noise generation and mutual interference due to the blanking signal input to the video processing IC, and fade-out. It is advantageous to lower the control voltage level of the clock to only the voltage at which the screen disappears, so that the screen appears immediately upon fade-in.

Claims (2)

The blanking signal input terminal 1 is connected to the base terminal of the transistor TR through the resistor R1, and its collector terminal of which the emitter terminal of the transistor TR is grounded is connected to the fade control signal output terminal 3; In the well-known thing connected to the fade voltage setting variable VR, the voltage divider R2-R4 in the fade control unit 2 for dividing the Vcc voltage is connected in series to ground and the resistors R3, ( A fade out switch SW having one end grounded is connected to the connection point of R4), and a fade voltage setting variable resistor VR is connected to the connection points of the resistors R2 and R3 through an integration capacitor C. A fade control circuit of a video device, characterized in that configuration. The resistor R5 and the connection point of the resistors R5 and R6 for dividing the Vcc voltage through an integrated capacitor C 'are connected to the variable resistor VR for setting the fade voltage. A fade control circuit for a video device, characterized in that the connection point (R6) is configured by connecting a resistor (R7) through a fade out switch (SW ').