KR910005113U - Slew rate adjustable output buffer - Google Patents

Slew rate adjustable output buffer

Info

Publication number
KR910005113U
KR910005113U KR2019890012809U KR890012809U KR910005113U KR 910005113 U KR910005113 U KR 910005113U KR 2019890012809 U KR2019890012809 U KR 2019890012809U KR 890012809 U KR890012809 U KR 890012809U KR 910005113 U KR910005113 U KR 910005113U
Authority
KR
South Korea
Prior art keywords
output buffer
slew rate
adjustable output
rate adjustable
slew
Prior art date
Application number
KR2019890012809U
Other languages
Korean (ko)
Other versions
KR940005871Y1 (en
Inventor
최영철
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR2019890012809U priority Critical patent/KR940005871Y1/en
Publication of KR910005113U publication Critical patent/KR910005113U/en
Application granted granted Critical
Publication of KR940005871Y1 publication Critical patent/KR940005871Y1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
KR2019890012809U 1989-08-31 1989-08-31 Slewrate contorl output buffer KR940005871Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019890012809U KR940005871Y1 (en) 1989-08-31 1989-08-31 Slewrate contorl output buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019890012809U KR940005871Y1 (en) 1989-08-31 1989-08-31 Slewrate contorl output buffer

Publications (2)

Publication Number Publication Date
KR910005113U true KR910005113U (en) 1991-03-20
KR940005871Y1 KR940005871Y1 (en) 1994-08-26

Family

ID=19289629

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019890012809U KR940005871Y1 (en) 1989-08-31 1989-08-31 Slewrate contorl output buffer

Country Status (1)

Country Link
KR (1) KR940005871Y1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100374547B1 (en) * 1995-12-30 2003-04-23 주식회사 하이닉스반도체 Data output buffer circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100374547B1 (en) * 1995-12-30 2003-04-23 주식회사 하이닉스반도체 Data output buffer circuit

Also Published As

Publication number Publication date
KR940005871Y1 (en) 1994-08-26

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Legal Events

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Year of fee payment: 11

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