KR910003663Y1 - Deflection distortion compensating circuit - Google Patents
Deflection distortion compensating circuit Download PDFInfo
- Publication number
- KR910003663Y1 KR910003663Y1 KR2019850015497U KR850015497U KR910003663Y1 KR 910003663 Y1 KR910003663 Y1 KR 910003663Y1 KR 2019850015497 U KR2019850015497 U KR 2019850015497U KR 850015497 U KR850015497 U KR 850015497U KR 910003663 Y1 KR910003663 Y1 KR 910003663Y1
- Authority
- KR
- South Korea
- Prior art keywords
- horizontal
- output
- deflection
- coil
- resistors
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
- H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
- H04N3/23—Distortion correction, e.g. for pincushion distortion correction, S-correction
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Details Of Television Scanning (AREA)
Abstract
내용 없음.No content.
Description
본 고안의 회로도.Circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 진폭조정부 2 : 반전부1: amplitude adjusting unit 2: inverting unit
3 : 합성부 4 : 차동증폭기3: synthesis section 4: differential amplifier
5 : 증폭제어부 6 : 위상보정부5: amplification control unit 6: phase correction
7 : 증폭부 8 : 수평공진부7: amplification unit 8: horizontal resonance unit
9 : 수평편향회로 VR1, VR2: 가변저항9: horizontal deflection circuit VR 1 , VR 2 : variable resistor
R1, R2: 저항 Q-Q7: 트랜지스터R 1 , R 2 : resistor QQ 7 : transistor
C1-C2: 콘덴서 H-DY : 수평편향코일C 1 -C 2 : Condenser H-DY: Horizontal Deflection Coil
FBT : 플라이백트랜스FBT: Flyback Trans
본 고안은 텔레비젼 브라운관에 나타나는 영상신호의 찌그러짐을 트랜지스터를 사용하여 보상할 수 있도록 한 편향 찌그러짐의 보정회로에 관한 것이다.The present invention relates to a deflection distortion correction circuit that can compensate for distortion of an image signal appearing in a television CRT using a transistor.
브라운관에 나타나는 영상신호가 직선적으로 이루어지지 않을 때 발생되는 것을 편향 찌그러짐이라고 하는데 텔레비전 회로에서 이와 같은 찌그러짐을 보상하여 왔다.Deflection distortion, which occurs when the video signal appearing in the CRT is not linear, has been compensated for such distortion in a television circuit.
그러나 종래에는 브라운관의 구조와 편향각과의 거리가 다르므로 주변에 찌그러짐이 생겨 트랜스를 사용하여 보정하고 있으나 트랜스의 특성과 주변 부품등의 특성으로 인하여 좌우의 찌그러짐 보정이 일정하게 조정되지 않는 단점이 있었다.However, in the related art, the structure of the CRT and the distance between the deflection angle are different, so that distortion is generated around the transformer. However, the distortion of the left and right distortions is not constantly adjusted due to the characteristics of the transformer and the surrounding components. .
본 고안은 이와 같은 점을 감안하여 트랜지스터를 사용하여 보정을 행함으로써 좌우 찌그러짐을 충분히 보정할 수 있는 편향 찌그러짐의 보정회로를 제공하고자 하는 것으로 수직 출력이 진폭 조정부를 거쳐 반전부에서 반전시키고 합성부의 차동 증폭기에서 합성시킨 후 증폭 제어부의 트랜지스터로써 수평 편향 회로의 수평 진폭 조정 코일에 흐르는 전류를 가감하여 수평 진폭 조정 코일의 인덕턴스 값을 변화시켜 보정하는 회로인 것이다.In view of the above, the present invention aims to provide a deflection distortion correction circuit capable of sufficiently correcting left and right distortions by performing correction using transistors. It is a circuit for compensating by changing the inductance value of the horizontal amplitude adjustment coil by synthesizing it in the amplifier and then adding or subtracting the current flowing in the horizontal amplitude adjustment coil of the horizontal deflection circuit as a transistor of the amplification controller.
이를 첨부도면에 의하여 상세히 설명하면 다음과 같다.When described in detail by the accompanying drawings as follows.
수직출력을 가변저항(VR1)과 콘덴서(C3)로 구성된 진폭조정부(1)에서 수직진폭을 조정하여 트랜지스터(Q2)와 저항(R2-R5)으로 구성된 반전부(2)에서 반전시킨 후 합성부(3)의 차동증폭기(4)에 인가되게 구성하고 차동증폭기(4)의 트랜지스터(Q4)(Q5)의 에미터측에는 수직 출력이 가변저항(VR2)과 콘덴서(C1)(C2) 및 저항(R1)으로 구성된 위상보정부(6)에서 위상보정을 행한후 트랜지스터(Q3)와 저항(R6-R9) 및 콘덴서(C4)로 구성된 증폭부(7)에서 증폭시킨 후 출력을 인가시키게 구성한다.In the inverting section 2 composed of the transistors Q 2 and the resistors R 2 -R 5 , the vertical output is adjusted in the amplitude adjusting section 1 composed of the variable resistor VR 1 and the capacitor C 3 . After inverting, it is configured to be applied to the differential amplifier 4 of the synthesizing section 3, and the vertical output is provided on the emitter side of the transistors Q 4 and Q 5 of the differential amplifier 4 with the variable resistor VR 2 and the capacitor ( After phase correction in the phase compensator 6 composed of C 1 ) (C 2 ) and resistor R 1 , amplification composed of transistor Q 3 , resistors R 6 -R 9 , and capacitor C 4 After the amplification in section (7) is configured to apply the output.
그리고 저항(R10-R14)과 콘덴서(C5) 및 차동증폭기(4)로 구성된 합성부(3)에서 반전된 출력과 위상보정된 후 증폭된 출력이 합성되게 구성하고 차동증폭기(4)의 트랜지스터(Q5)의 콜렉터측에 저항(R15-R17)과 트랜지스터(Q6)(Q7)로 구성된 증폭제어부(5)를 구성시켜 합성부(3)의 출력을 증폭 제어하도록 구성한다.In the synthesizer 3 composed of the resistors R 10 -R 14 , the capacitor C 5 , and the differential amplifier 4, the inverted output and the phase-amplified output are synthesized and the differential amplifier 4 is synthesized. configuration to the configuration of the resistance (R 15 -R 17) and a transistor amplifier controlling section 5 is composed of (Q 6), (Q 7) to the collector side of the transistor (Q 5) to the amplification control of the output of the combination unit (3) do.
또한 증폭제어부(5)의 트랜지스터(Q7)의 출력이 저항(R10)과 콘덴서(C6)를 거쳐 반전부(2)에 궤환되게 구성함과 동시에 콘덴서(C10)(C11)와 수평진폭조정코일(L1)(L2)로 구성된 수평 편향회로(9)에서 수평공진부(8)의 수평편향 코일(H-DY)에 흐르는 전류를 제어하게 구성하고 수평 출력이 수평공진부(8)의 트랜지스터(Q1)와 콘덴서(C7-C9)를 거쳐 플라이백트랜스(FBT)에 고압을 유기시켜 주고 수평편향코일(H-DY)을 통하여 편향 조정되도록 구성한 것이다.In addition, the output of the transistor Q 7 of the amplification control unit 5 is configured to be fed back to the inverting unit 2 through the resistor R 10 and the capacitor C 6 , and at the same time, the capacitor C 10 (C 11 ) and In the horizontal deflection circuit 9 consisting of the horizontal amplitude adjusting coil L 1 and L 2 , the electric current flowing through the horizontal deflection coil H-DY of the horizontal resonator 8 is controlled, and the horizontal output is the horizontal resonator. The high voltage is induced to the flyback transformer (FBT) through the transistor (Q 1 ) and the capacitor (C 7 -C 9 ) of (8) and configured to be deflected through the horizontal deflection coil (H-DY).
도면중에 설명 부호인 다이오드(D1)는 파형 보정용이다.In the figure, the diode D 1 , which is an explanation code, is used for waveform correction.
이와 같이 구성된 본 고안은 수평출력이 수평공진부(8)의 트랜지스터(Q1)와 콘덴서(C7-C9)를 통하여 플라이백 트랜스(FBT)에 고압을 유기시킴과 동시에 수평편향코일(H-DY)로써 수평편향을 행하게 하며 또한 수평편향회로(9)의 콘덴서(C10)(C11)와 수평진폭 조정코일(L1)(L2)에 출력을 인가시킨다.According to the present invention configured as described above, the horizontal output coil induces a high pressure to the flyback transformer FBT through the transistors Q 1 and the capacitors C 7 to C 9 of the horizontal resonator 8, and at the same time the horizontal deflection coil H -DY) and the output is applied to the capacitor (C 10 ) (C 11 ) and the horizontal amplitude adjustment coil (L 1 ) (L 2 ) of the horizontal deflection circuit (9).
그리고 수직 출력을 진폭조정부(1)의 가변저항(VR1)으로써 진폭을 조정하여 반전부(2)에 인가시켜 저항(R2-R5)과 트랜지스터(Q2)을 통하여 증폭제어부(5)에서 저항(R18)과 콘덴서(C6)를 통하여 궤환된 출력을 반전시켜 합성부(3)의 차동증폭기(4)에 인가시키고 수직출력이 위상보정부(6)의 가변저항(VR2)을 통하여 위상이 보정된 후 저항(R6-R9)와 트랜지스터(Q3)로써 구성된 증폭부(7)에서 증폭시켜 트랜지스터(Q4)(Q5)로 구성된 차동증폭기(4)의 에미터 측에 인가시킨다.Then, the vertical output is controlled by the variable resistor VR 1 of the amplitude adjusting unit 1 and is applied to the inverting unit 2 so that the amplification control unit 5 is provided through the resistors R 2 -R 5 and the transistor Q 2 . Invert the output fed back through the resistor (R 18 ) and condenser (C 6 ) and apply it to the differential amplifier (4) of the synthesis section (3), the vertical output of the variable resistor (VR 2 ) of the phase compensation (6) Emitter of the differential amplifier 4 composed of transistors Q 4 and Q 5 by amplifying in the amplifier 7 composed of resistors R 6 -R 9 and transistor Q 3 after phase correction through To the side.
따라서 차동증폭기(4)에서는 반전부(2)의 반전된 출력과 증폭부(7)의 증폭된 출력이 합성되어 트랜지스터(Q5)의 콜렉터측에 연결된 증폭제어부(5)에 인가시키며 이때 저항(R10-R14)은 차동증폭기(4)의 바이어스저항으로 동작한다.Therefore, in the differential amplifier 4, the inverted output of the inverting unit 2 and the amplified output of the amplifying unit 7 are synthesized and applied to the amplifying control unit 5 connected to the collector side of the transistor Q 5 . R 10 -R 14 ) operates as a bias resistor of the differential amplifier 4.
그리고 증폭제어부(5)는 차동증폭기(4)의 출력으로써 전원(B+)이 인가되는 트랜지스터(Q6)(Q7)를 순차적으로 동작시켜 증폭시키며 트랜지스터(Q7)의 출력이 수평편향회로(9)의 수평진폭조정코일(L1)(L2)에 흐르는 전류를 가감시켜 수평진폭 조정코일(L1)(L2)의 포화특성을 이용하여 수평편향코일(H-DY)으로써 편향의 찌그러짐을 보정해주는 것이다.The amplification control unit 5 sequentially operates and amplifies the transistors Q 6 and Q 7 to which the power supply B + is applied as the output of the differential amplifier 4, and the output of the transistor Q 7 is a horizontal deflection circuit. 9, the horizontal amplitude adjusting coil (L 1) by subtraction of the current flowing between (L 2), the horizontal amplitude adjusting coil (L 1) deflected by the horizontal deflection coil (H-DY) by using the saturation characteristic of the (L 2) of the This is to correct the distortion of the.
이상에서와 같이 본 고안은 수직 출력이 진폭조정부(1)를 거쳐 반전부(2)의 궤환된 출력으로써 반전시킨 후 위상 조정부(6)와 증폭부(7)를 거쳐 증폭된 출력과 합성부(3)의 차동증폭기(4)로써 합성시켜 합성된 출력으로써 증폭제어부(5)의 트랜지스터(Q6)(Q7)에 흐르는 전류를 가감하여 수평편향회로(9)에 인가시켜 수평진폭 조정코일(L1)(L2)에 흐르는 전류를 가감시킴으로 수평공진부(8)의 출력이 인가되는 수평편향코일(H-DY)로써 편향을 행하게 하여 좌우의 찌그러짐을 보정시켜 줄 수 있는 것으로 트랜지스터를 사용하므로써 저가격에 설계할 수 있는 것이다.As described above, according to the present invention, the vertical output is inverted as the feedback output of the inverting unit 2 through the amplitude adjusting unit 1, and then the output and synthesis unit amplified through the phase adjusting unit 6 and the amplifying unit 7 ( The output synthesized by synthesizing with the differential amplifier 4 of 3) is applied to the horizontal deflection circuit 9 by adding and subtracting the current flowing through the transistors Q 6 and Q 7 of the amplification control unit 5 to the horizontal amplitude adjusting coil ( L 1 ) (L 2 ) by adjusting the current flowing through the horizontal resonance coil (H-DY) applied to the output of the horizontal resonance portion (8) to deflect the right and left distortion by using a transistor This makes it possible to design at low cost.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850015497U KR910003663Y1 (en) | 1985-11-23 | 1985-11-23 | Deflection distortion compensating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850015497U KR910003663Y1 (en) | 1985-11-23 | 1985-11-23 | Deflection distortion compensating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870009103U KR870009103U (en) | 1987-06-15 |
| KR910003663Y1 true KR910003663Y1 (en) | 1991-05-31 |
Family
ID=19246671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019850015497U KR910003663Y1 (en) | 1985-11-23 | 1985-11-23 | Deflection distortion compensating circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR910003663Y1 (en) |
-
1985
- 1985-11-23 KR KR2019850015497U patent/KR910003663Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR870009103U (en) | 1987-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3947723A (en) | Low power high frequency horizontal deflection amplifier | |
| KR910003663Y1 (en) | Deflection distortion compensating circuit | |
| KR930020954A (en) | Corner pin cushion deformation correction circuit and TV receiver | |
| FI65006B (en) | VERTICAL AVBOEJNINGSKRETS | |
| KR910009210Y1 (en) | Deflection distortin compensating circuit | |
| GB1237819A (en) | A circuit for producing magnetic vertical deflection in colour television apparatus | |
| KR900010850Y1 (en) | Focus compensating circuit for crt. | |
| KR970031777A (en) | Screen width correction circuit | |
| US4651063A (en) | Horizontal deflection circuit | |
| US4166237A (en) | Horizontal deflection circuit for television camera | |
| US3293486A (en) | Linearity correction circuit | |
| US4855651A (en) | Timebase circuit | |
| KR960006105Y1 (en) | Compensation circuit of crt | |
| KR950002322B1 (en) | Picture compensating circuit for monitor | |
| JPS57118474A (en) | Picture compensating device | |
| GB1174183A (en) | Improvements in and relating to circuit arrangements for the correction of pin cushion distortion in display tubes | |
| KR900008498Y1 (en) | Cathode-ray tube | |
| KR940003037Y1 (en) | Distortion compensating circuit for color display device | |
| KR910008281Y1 (en) | Laster horizontal width control circuit | |
| CA1155557A (en) | Quasi feedback horizontal scan linearization for cathode ray tube | |
| KR200184826Y1 (en) | Dynamic focus circuit of monitor | |
| JPH05199425A (en) | High voltage stabilizing circuit for image reception tube | |
| KR910003665Y1 (en) | Trapezoid distortion control circuit for crt | |
| KR940011395B1 (en) | Dynamic focus circuit | |
| KR900008980Y1 (en) | Over deflecting compensation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| REGI | Registration of establishment | ||
| FPAY | Annual fee payment |
Payment date: 19970424 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |