KR910003616Y1 - Rf synchronizing signal rectifying circuit - Google Patents

Rf synchronizing signal rectifying circuit Download PDF

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Publication number
KR910003616Y1
KR910003616Y1 KR2019870019630U KR870019630U KR910003616Y1 KR 910003616 Y1 KR910003616 Y1 KR 910003616Y1 KR 2019870019630 U KR2019870019630 U KR 2019870019630U KR 870019630 U KR870019630 U KR 870019630U KR 910003616 Y1 KR910003616 Y1 KR 910003616Y1
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South Korea
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signal
output
synchronous
control pulse
detector
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KR2019870019630U
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Korean (ko)
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KR890011468U (en
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노일영
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삼성전자 주식회사
안시환
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/54—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head into or out of its operative position or across tracks
    • G11B5/55—Track change, selection or acquisition by displacement of the head
    • G11B5/5521—Track change, selection or acquisition by displacement of the head across disk tracks
    • G11B5/5526—Control therefor; circuits, track configurations or relative disposition of servo-information transducers and servo-information tracks for control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/58—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
    • G11B5/584—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on tapes

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

내용 없음.No content.

Description

RF 동기 신호 정형회로RF sync signal shaping circuit

제 1 도는 본 고안의 회로도.1 is a circuit diagram of the present invention.

제 2 도는 본 고안의 각부 파형도.2 is a waveform diagram of each part of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : RF동기 검출기 2 : 제어펄스 발생기1: RF synchronous detector 2: control pulse generator

5 : RF 동기 신호 검출기 A1-A4: 앰프5: RF sync signal detector A 1 -A 4 : amplifier

DM : 드럼 모터 I1: 인버터DM: Drum Motor I 1 : Inverter

AN1: 앤트게이트 C1, C2: 콘덴서AN 1 : Antgate C 1 , C 2 : Condenser

H1: 헤드H 1 : head

본 고안은 디지털 오디오 테이프 레코더(Digital Audio Tape Recorder : D. A. T)의 서어보(Servo)회로에 있어서, 안정된 서어보 동작을 수행할 수 있도록 RF동기 신호를 정형화시켜 주는 RF동기 신호 정형 회로에 관한 것이다.The present invention relates to an RF synchronous signal shaping circuit for shaping an RF synchronous signal in a servo circuit of a digital audio tape recorder (DA T). .

일반적으로 D. A. T의 서어보 회로에서는 재생시에 정확하게 트랙(Track)을 재생하기 위하여 A. T. F(Automatic Track Finding)기법을 사용하고 있는데 이러한 ATF에 사용되는 샘플링 펄스(Sampling pulse)를 정확하게 만들어 내기 위해서는 RF 동기 신호를 정확하게 검출해줄 필요가 있는 것이다.In general, the DA T's servo circuit uses the AT F (Automatic Track Finding) technique to accurately reproduce tracks during playback. In order to accurately generate sampling pulses used for these ATFs, RF synchronization is required. It is necessary to detect the signal accurately.

그러나 헤드에서 재생된 신호는 재생 앰프를 통하여 중폭된 후 버퍼를 통하여 RF동기 검출기에서 RF동기신호를 검출하도록 구성된 종래의 회로에서는 DAT헤드에서 재생되는 μV단위가 되므로 재생 앰프를 거친 신호를 RF동기 검출기로 검출할시에는 약간의 노이즈만 발생하여도 원래의 동기 신호가 없는 곳에서 RF동기 신호가 있는 것처럼 검출되게 된다.However, in the conventional circuit configured to detect the RF synchronization signal from the RF synchronization detector through the buffer after the signal reproduced at the head is amplified by the reproduction amplifier, the signal that has been reproduced at the DAT head is in μV units. In the case of detecting the signal, even if a little noise occurs, it is detected as if there is an RF synchronization signal in a place where the original synchronization signal is not present.

이와 같이 RF동기 신호가 없는 곳에서도 노이즈에 의한 RF동기 신호가 검출되면 서어보 회로의 ATF콘트롤 신호가 오동작하게 되므로써 정상적인 트랙킹(Tracking)이 이루어지지 못하게 되는 단점이 있는 것이었다.As described above, when the RF synchronization signal due to noise is detected even in the absence of the RF synchronization signal, the ATF control signal of the servo circuit is malfunctioned, thereby preventing normal tracking.

본 고안은 이와 같은 점을 감안하여 RF신호가 반드시 있어야 할 부분에서만 RF동기 신호가 출력되게 하고 그 이외의 부분에서는 RF동기 신호의 출력을 차단해주어 ATF콘트롤 신호가 RF동기 신호가 없는 부분에서도 트랙킹을 제어하게 되는 오동작을 방지해 주도록 한 것으로써 이를 첨부 도면에 의하여 상세히 설명하면 다음과 같다.In consideration of this, the present invention allows the RF synchronous signal to be output only in the part where the RF signal must be present, and cuts the output of the RF synchronous signal in the other parts so that the ATF control signal can track even in the absence of the RF synchronous signal. It will be described in detail by the accompanying drawings to prevent the malfunction to be controlled as follows.

헤드(H1)에서 재생된 신호는 재생 앰프(A1)를 통하고 콘덴서(C1)와 버퍼용 앰프(A2)를 통한후 콘덴서(C2)가 연결된 RF동기 검출기(1)를 통하여 출력되게 구성된 공지의 RF동기 신호 검출부(5)의 출력을 앤드게이트(AN1)의 일측에 인가시키고 앤드 게이트(AN1)의 타측에는 제어 펄스 발생기(2)의 RFW(Radio Frequecy Window) 신호가 인버터(I1)를 통하여 인가되게 구성하되 제어 펄스 발생기(2)에는 드럼 모터(DM)로부터 앰프(A3)(A4)를 통하여 위상 제어용 펄스(DPG)와 스피드 제어용 펄스(DFG)가 인가되게 구성하므로써 앤드게이트(AN1)의 출력측으로 정형화된 RF 동기 신호가 출력되게 구성한 것이다.The signal reproduced from the head (H 1 ) is passed through the reproduction amplifier (A 1 ), through the capacitor (C 1 ) and the buffer amplifier (A 2 ), and then through the RF synchronous detector (1) to which the capacitor (C 2 ) is connected. output to be a known RF synchronization signal detector 5 to output the aND gate (aN 1) side is applied and the aND gate (aN 1), the other side RFW (Radio Frequecy Window) signal of the control pulse generator (2) of the of the configured It is configured to be applied through an inverter (I 1 ) but the control pulse generator (2) is applied from the drum motor (DM) through the amplifier (A 3 ) (A 4 ) phase control pulse (DPG) and speed control pulse (DFG) In this configuration, the RF synchronous signal is output to the output side of the AND gate AN 1 .

이와 같이 구성된 본 고안에서 제 1 도는 본 고안의 회로도로써 DAT의 재생중에 헤드(H1)에서 테이프에 기록되어 있는 신호를 읽어 재생 앰프(A1)와 직류 커플링용 콘덴서(C1) 및 버퍼용 앰프(A2)를 통하게 한후 RF검파드레스홀드(Threshold) 제어용 콘덴서(C2)가 연결된 RF 동기 검출기(1)에 인가시켜 주어 RF동기 검출기(1)에서 RF신호의 유무를 판단하여 제 2e 도에서와 같은 RF동기 신호 출력을 출력시키도록 구성된 공지의 RF동기 신호 검출부(5)의 출력은 앤드게이트(AN1)의 일측에 인가되게 한다.1 is a circuit diagram of the present invention, which reads the signal recorded on the tape from the head H 1 during playback of the DAT, and reproduces the amplifier A 1 , the DC coupling capacitor C 1 , and the buffer. After passing through the amplifier A 2 , the RF detection threshold control capacitor C 2 is applied to the RF synchronization detector 1 connected to the RF synchronization detector 1 to determine the presence or absence of an RF signal. An output of the known RF synchronization signal detector 5 configured to output an RF synchronization signal output as in FIG. 5 is applied to one side of the AND gate AN 1 .

이때 RF동기 검출기(1)의 출력은 헤드(H1)에서 재생되는 신호의 레벨이 μV단위로 매우 작기 때문에 약간의 노이즈만 발생되어도 RF신호가 없어야 하는 구간에서도 RF신호가 있는 것처럼 RF동기 검출기(1)가 출력을 하여 레벨로 출력시키게 되는 문제점이 있으므로 이러한 노이즈성 RF동기 신호 출력을 제거하기 위하여 RF동기 신호 검출부(5)의 출력은 앤드게이트(AN1)의 일측에 인가시켜 주는 것이다.At this time, since the level of the signal reproduced from the head H 1 is very small in units of μV, the output of the RF synchronous detector 1 is similar to that of the RF synchronous detector ( The output of the RF synchronous signal detector 5 is applied to one side of the AND gate AN 1 in order to remove such a noisy RF synchronous signal output since there is a problem in that 1 ) outputs the output.

그런후에 드럼모터(DM)에서 제 2a 도에서와 같은 위상 제어용 펄스(DPG)와 스피드 제어용 펄스(DFG)를 발생시켜 각각의 앰프(A3)(A4)를 통한후 제어 펄스 발생기(2)에 인가시켜 주면 제어펄스 발생기(2)에서는 제 2b 도에서와 같은 스위칭 펄스(SWP)를 발생시켜 서어보 회로와 신호처리회로에 인가시켜 주게 됨과 동시에 제 2c 도에서와 같은 RFW신호를 출력시키게 된다.Then, the drum motor DM generates the phase control pulses DPG and the speed control pulses DFG as shown in FIG. 2A through the respective amplifiers A 3 and A 4 , and then the control pulse generator 2. When applied to the control pulse generator 2, the control pulse generator 2 generates the switching pulse SWP as shown in FIG. 2B and applies it to the servo circuit and the signal processing circuit, and simultaneously outputs the RFW signal as shown in FIG. 2C. .

즉 세어 펄스 발생기(2)에서는 위상 제어용 펄스(DPG)를 받아들여 RF신호가 반드시 있어야 하는 구간 동안에는 RFW신호를 로우 레벨로 출력시켜 주게 된다.That is, the counting pulse generator 2 receives the phase control pulse DPG and outputs the RFW signal at a low level during the period in which the RF signal must be present.

이러한 제어 펄스 발생기(2)의 제 2c 도에서와 같은 RFW신호는 인버터(I1)를 통하여 제 2d 도에서와 같이 반전된 펄스로 출력되어 앤드게이트(AN1)의 타측에 인가되게 되므로써 앤드게이트(AN1)에서는 일측으로 인가되는 제 2e 도에서와 같은 펄스와 타측으로 인가되는 제 2d 도에서와 같은 펄스를 논리곱(AND)하여 제 2f 도에서와 같은 RF동기 신호를 출력시키게 된다.The RFW signal as shown in FIG. 2C of the control pulse generator 2 is outputted as an inverted pulse as shown in FIG. 2D through the inverter I 1 and applied to the other side of the AND gate AN 1 . In (AN 1 ), the same pulse as in FIG. 2e applied to one side and the same pulse as in FIG. 2d applied to the other side are ANDed to output the RF synchronization signal as shown in FIG. 2f.

즉 제 2f 도에서와 같은 RF동기 신호를 출력시킴으로써 RF신호가 없어야 되는 부분에서의 노이즈에 의한 RF동기 신호가 발생되는 것을 억제시켜 RF신호가 있는 구간에서만 RF동기 신호가 하이 레벨로 정확히 출력되도록 한 것이다.That is, by outputting the RF synchronization signal as shown in FIG. 2F, the generation of the RF synchronization signal due to the noise in the portion where the RF signal should not be suppressed is made so that the RF synchronization signal is correctly output at a high level only in the section where the RF signal is present. will be.

한편 본 고안에서 드럼 모터(DM)로부터 위상 제어용 펄스(DPG)와 스피드 제어용 펄스(DFG)를 받아 RFW신호의 위상을 반대로 구성할 수 있으며 이때에는 인버터(I1)를 제거하고 앤드게이트(AN1)만 사용할수도 있다.Meanwhile, in the present invention, the phase of the RFW signal can be reversed by receiving the phase control pulse DPG and the speed control pulse DFG from the drum motor DM. In this case, the inverter I 1 is removed and the AND gate AN 1 is removed. ) Can only be used.

이와 같이 종래에는 실제로 RF신호가 없는 구간에서도 노이즈에 의한 RF동기 신호가 검출되어 트랙킹을 행하는데 있어서 오동작을 하게 되는데 반하여 본 고안에서는 RF신호가 없는 부분에서의 RF동기 신호를 노이즈로부터 방지시켜 주므로써 트랙킹을 정확하게 행할 수 있게 되는 효과가 있는 것이다.As described above, an RF synchronous signal due to noise is detected even in a section where there is no RF signal, and thus a malfunction occurs in tracking. However, the present invention prevents an RF synchronous signal in a portion without an RF signal from noise. There is an effect that tracking can be performed accurately.

Claims (1)

드럼모터(DM)에서 앰프(A3)를 통하여 발생시킨 위상 제어용 펄스(DPG)를 제어펄스 발생기(2)에 인가시켜 주어 RFW신호를 출력시키게 구성하고 RFW신호는 인버터(I1)를 통한후 공지의 RF동기 신호 검출부(5)의 출력과 함께 앤드 게이트(AN1)를 통하여 정형화된 RF동기 신호로 출력되게 구성한 RF동기 신호 정형회로.After applying the phase control pulse (DPG) generated by the amplifier (A 3 ) in the drum motor (DM) to the control pulse generator (2) is configured to output the RFW signal and the RFW signal through the inverter (I 1 ) An RF synchronous signal shaping circuit configured to be output as a standardized RF synchronous signal through an AND gate (AN 1 ) together with the output of a known RF synchronous signal detector (5).
KR2019870019630U 1987-11-12 1987-11-12 Rf synchronizing signal rectifying circuit KR910003616Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019870019630U KR910003616Y1 (en) 1987-11-12 1987-11-12 Rf synchronizing signal rectifying circuit

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Application Number Priority Date Filing Date Title
KR2019870019630U KR910003616Y1 (en) 1987-11-12 1987-11-12 Rf synchronizing signal rectifying circuit

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Publication Number Publication Date
KR890011468U KR890011468U (en) 1989-07-13
KR910003616Y1 true KR910003616Y1 (en) 1991-05-31

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KR2019870019630U KR910003616Y1 (en) 1987-11-12 1987-11-12 Rf synchronizing signal rectifying circuit

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