KR910001985B1 - Side-wall doped half-vcc plate trench capacitor cell and manufacturing method thereof - Google Patents

Abstract

The trench capacitor with SDHT structure for DRAM is manufactured by: forming a P-wall region on P-type Si substrate; forming a trench by RIE etching through mask pattern; forming a diffusion layer at side-wall of trench for outer electrode by PSG or POCL3 method; forming a thick oxide layer by CVD method on the side- wall of the first trench; forming an inner electrode with poly-Si on the ONO layer formed at the residual side-wall of the second trench; forming a word line by the second poly-Si layer; forming a gate electrode including source and drain; connecting the drain and trench electrode with third poly-Si layer for bit line.

Description

Trench capacitor cell composed of SDHT structure and its manufacturing method

1 is a cross-sectional view of a trench capacitor cell made of an SDHT structure made in accordance with the present invention.

2 to 7 are cross-sectional views showing in detail a process of self-aligned contact (SELFALIGNED CONTACT) process,

2 is a cross-sectional view of the gate electrode formed during the manufacturing process according to the present invention.

FIG. 3 is a cross-sectional view of an oxide film formed on the left and right sides of the gate electrode of FIG. 2 and an upper portion of a silicon wafer, and an N-impurity formed on the P-WELL.

4 is a cross-sectional view of forming a spacer SPACER on the left and right side wall surfaces of the gate electrode of FIG.

5 is a cross-sectional view of an oxide film deposited on top of an N-WELL such that N + impurities are not diffused in order to fabricate a FET forming a P-type channel in a CMOS structure.

FIG. 6 is a cross-sectional view of the IPOLY pattern formed on the gate left and right spacer SPACER of FIG.

FIG. 7 is a cross-sectional view of forming a pattern by forming an LTO film on the gate of FIG. 6 and depositing a poly 3 layer on the IPOLY.

8 is a chart showing the state of change of the threshold voltage according to the thickness of the CVD oxide layer of the trench capacitor according to the present invention.

* Explanation of symbols for main parts of the drawings

1: P-type silicon substrate 2: Protective layer

3: metal layer 4: doped oxide layer

5: Poly 3 layer 6: LTO (LOW TEMPERATURE OXIDE) oxide film layer

7: IPOLY (INTERCONNECTION POLY) layer

8: poly 2 layer 9: insulating oxide layer

10: gate oxide films 11 and 11 ': source and drain N + regions

12: ONE (OXIDE-NITRIDE-OXIDE) layer

13: POLY 1st floor 14: N + diffusion layer

15: P-WELL Area

16: CVD (CHEMICAL VAPOUR DEPOSITION) oxide layer

17 nitride layer 18 LTO oxide layer

19: oxide layer 20: LDD (LIGHTLY DOPED DRAIN) region

21: spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technology of SDHT (SIDE-WALL DOPED HALF-VCC PLATE TRENCH CAPACITOR) cells of semiconductor integrated storage devices. In particular, the present invention has a structure similar to that of an SDT cell. The present invention relates to a trench capacitor cell having a small SDHT structure and a method of manufacturing the same.

In the conventional SDT cell structure, a high voltage of the same VCC as a P-type substrate is applied to the P + region diffused into the sidewalls of the trench capacitor so that the thickness of the tetragonal layer of the trench capacitor is generated by the voltage applied across the capacitor. It had to be thick enough to withstand. As the thickness of the oxide film becomes thicker, the capacity of the capacitor decreases in inverse proportion and the area of the moving gate has been widened by using a mask as follows.

In other words, the BNC mask is used to connect the drain region of the movable gate to the trench capacitor storage electrode by using a DC contact mask when the source region of the movable gate is connected to the bit line. And the area of the cell increases because the minimum distance must be maintained to prevent leakage current between the gate and the mask.

Accordingly, an object of the present invention is to solve the above-mentioned disadvantages and to provide an SDHT cell trench capacitor cell having a larger capacitor capacity than a conventional SDT cell and a small cell area, and a method of manufacturing the same.

According to the present invention, the impurity diffused on the sidewalls of the trench capacitor is N + region, and the capacitor oxide film thickness can be reduced to about 80 kV by applying the VCC / 2 voltage to the P + substrate, and compared with the SDT cell of the same area. A large trench capacitor capacity can be obtained, and the area is reduced by using a method of self-aligned contact without using a mask when connecting the source region, the bit line, the drain region and the trench storage electrode of the moving gate.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing the structure of an SDHT cell manufactured according to the present invention, in which a N-WELL or P-WELL is applied to a peripheral circuit to perform a CMOS process for reducing power consumption of a memory device on a P-type silicon substrate 1. After forming the region 15, a mask pattern is formed on the P-WELL region 15 to form a trench capacitor, and a primary trench is formed to a depth of about 2 占 퐉 with an RIE etch, and then the process is performed. Subsequently, when the storage electrode poly1 layer 13 is charged with electric charge, a parasitic vertical NMOSFET is formed between the moving gate drain N + region 11 and the N + diffusion layer 14 in the trench sidewall to form N + in the drain N + region 11 '. Charge is leaked to the diffusion layer 14, which prevents this and simultaneously controls the tunneling current in the N + diffusion layer 14 when a strong electric field is applied to the N + diffusion region 14 and the trench capacitor interface on the side wall. To cut off the leakage current The deposited over the CVD oxide layer 16 to about 1000Å. As an example for explaining this, FIG. 8 is a diagram illustrating the voltage VGS between the gate and the source when the threshold voltage VT and the IDS current = 10 (A) according to the oxide film thickness and the voltage applied to the gate.

After the above process, nitride is deposited on the CVD oxide 16 layer, for example, about 500 mm thick, and the anisotropic etch removes the nitride layer and the CVD oxide layer 16 at the bottom of the first trench, and then the secondary trench is about 5 μm. Formed to length and deposited PSG impurities on the secondary trench wall, and then heat-treated to form an N-diffusion layer 14, a VCC / 2 plate for trench external electrodes, to remove residual PSG.

After the above process, the nitride layer of the primary trench wall is removed, and the ONO layer 12 of the capacitor oxide layer is formed on the primary trench CVD oxide layer 16 and the secondary trench wall surface of 100 占 or less to increase the capacitor capacity. . In addition, in the foldline bit line cell arrangement, in order to apply 1/2 VCC to the capacitor external electrode N + diffusion layer 14, since the unit cells are periodically alternately arranged, the N + diffusion regions between the unit cells and the unit cells are arranged to be interconnected. In order to connect the VCC / 2 electrode to the N + diffusion layer 14 for the external electrode at the outermost portion of the memory region, the CVD oxide layer 16 is removed at the outermost trench side and all sides of the primary and secondary trenches are removed. The wall portion is diffused with N type impurities to form an N + diffusion layer.

After the process, the N-type poly1 layer 13 is filled in the trench structure, the mask pattern layer on the trench is removed, the surface is planarized by a flat process, and the polyl for trench internal electrode 1 is fabricated by a LOCOS method. An insulating oxide layer 9 is formed to a thickness of about 3000 kPa in order to insulate each transistor inside the IC on the upper right side of the layer 13.

After the above process, the poly 2 layer 8 'is deposited on the insulating oxide layer 9 and the moving gate poly 2 layer 8 is deposited on the left P-WELL region 15 to form a gate electrode. The IPOLY layer 5 is deposited to remove the gate top and heat treated to diffuse N impurity from the IPOLY layer 5 into the P-WELL region 15 to form source and drain N + regions 11 and 11 '.

After the process, the LTO oxide layer 7 is deposited and removed, leaving a portion, and then the bitline poly3 layer 5 is deposited so as to contact the IPOLY layer 5 over the source N + region 11, A dope oxide film layer 4 of BPSG is deposited on the bit line poly 3 layer 5 to insulate the metal layer 3 and the bit line poly 3 layer 5.

After the above process, the word line fixing metal layer 3 is formed on the dope oxide layer 4 so that when the poly 2 layer 8, which becomes a word line, is continuously connected, the resistance is increased so that a voltage drop is generated. In order to prevent such a voltage drop, the voltage drop is solved by supplying power by contacting the poly 2 layer 8 with the metal layer 3 every 128th cell of the cell.

Thereafter, a protective layer 2 is deposited on the metal layer to protect the cell from heat, shock and current.

The structure made of the above process is the structure of the SDHT cell as shown in FIG.

After the process, the process of forming the moving gate poly 2 layer 8 and connecting the moving gate source and drain N + regions 11 and 11 ′ to the bit line and the storage electrode poly 1 layer 13 is performed using a self-aligned contact. CONTACT) will be described with reference to FIGS.

FIG. 2 deposits a gate oxide film 10 over the P-WELL region 15 on the left side of the trench capacitor and deposits a gate electrode poly 2 (8) over the oxide film 10, and then LTO (LOW TEMPERATURE) on the top. OXIDE) It is sectional drawing of the nitride film layer 17 deposited in order to deposit the oxide film layer 18, to protect the LTO oxide layer 18 at the time of etching, and to prevent an oxide film from growing upward during an oxidation process.

3 is for preventing leakage current of the IPOLY (INTERCONNETION POLY) 5 at the left and right sides of the gate electrode poly 2 (8) and reducing the junction depth of the N-impurity of the LDD (LOWER DOPED DRAIN) region 20. An oxide layer 19 is formed on the upper and lower surfaces of the P-WELL region 15 and the gate electrode poly 2 layer 8, and then an N-type impurity is formed on the oxide layer 19 above to form an N-region. The ion implantation forms an LDD region 20, which causes a strong electric field when an inversion layer occurs between the source and drain N + regions 11 and 11 'regions, thereby changing the acceleration of electrons to a low-concentration N- region and thus the intensity of the electric field. This reduces the acceleration of electrons.

4 shows an oxide film deposited on the left and right sides of the gate electrode poly2 layer 8, and then anisotropic oxide film etch is performed to diffuse N-type impurities into the LDD region 21 from the IPOLY 5 to be formed in a later step. The spacers 21 are formed to protect them from being changed and the remaining oxide film is removed.

In addition, in order to prevent the diffusion of the N-regions of the P-MOSFETs, that is, the source and drain N + regions 11 and 11 ', from the N-type impurities of POLY when the P-MOSFET is simultaneously formed with the N-MOSFET to form CMOS. 5 is a thin oxide film grown.

FIG. 6 shows the removal of the nitride layer 17 over the gate electrode poly2 layer 8 of FIG. 4, followed by removal of the oxide of the NMOS region using a SAC mask, and the LTO oxide layer on the gate electrode poly2 layer 8 ( 18) In the process of depositing IPOLY (7) on the upper part and P-WELL area 15 and removing some part of IPOLY (7) on the gate, it is possible to deposit IPOLY (7) directly without using a mask when depositing it. When using a mask, there is no need to provide a minimum distance to compensate for errors in the process equipment. For example, the minimum distance X is X between the left side of the gate electrode and IPOLY (7), X between the right side of the gate electrode and IPOLY (7) and IPOLY (7) on the left side of the gate electrode on the insulating oxide layer 9 ) X is 3X, and if the size of the cell on the word line is Y, the reduced area of the cell can be expressed as 3XY.

FIG. 7 shows that when the IPOLY 7 deposited in FIG. 6 is diffused into the P-WELL region 15 through a heat treatment process, source and drain N + regions 11 and 11 'are formed and IPOLY is formed on the two gates of the cell. The LTO oxide layer 6 was grown to insulate the layer 7 and the bitline poly3 (5) and then the bitline poly3 (5) was deposited.

As described above, the gate electrode is formed, the IPOLY layer 7 is deposited, the source and drain N + regions 11 and 11 'are formed, and the LTO oxide layer 17 is deposited. After the process of depositing a self-aligned contact, the bit line poly 3 layer 5 and the doped oxide layer 4 of BPSG are deposited on the bit line poly 3 (5) and the upper metal layer (3). It is insulated, and the word line fixing metal layer 3 is formed on the dope oxide layer 4 so that the word line poly 2 layer 8 is continuously connected to the cell to generate a voltage drop. Connected to layer 8 and connected directly from metal layer 3 to every 128th cell so that power is supplied. After the process, the protective layer 2 is deposited to protect the cell from heat, impact, current, and the like.

The operation of the present invention is a unit cell in which a transistor and a capacitor are connected in series. The gate electrode is connected to the word line, the source terminal is connected to the bit line, and the drain terminal and the capacitor are connected in series, and the capacitor and the other terminal are connected to the P + substrate. With a grounded structure, charges can be accumulated or erased. For example, when the capacitor of the NMOSFET structure is not accumulated, if a positive voltage is applied to the bit line and a positive voltage to the word line, the word line applies a positive voltage to the gate terminal so that the drain and the source are conducted, and the bit line is the source terminal. The positive voltage is applied to the capacitor, and charge is accumulated in the capacitor through the drain.

Also, in the case of accumulated capacitors, when a positive voltage is applied to a word line, it is connected to a gate terminal and is connected to a source and a drain. Is discharged and erased. Thus, the function of erasing can be sensed to read the information.

The SDHT cell of the present invention can not only increase the capacitor capacity as described above, but can also reduce the area of the cell by using a self-aligned contact method.

Claims (2)

A P-well region is formed on a P-type substrate, a mask pattern is formed, and a trench is formed by RIE etching. A trench external electrode diffusion layer is formed on the trench wall by PSG or POCL3 impurity diffusion. In a trench capacitor cell including a metal layer and a protective layer, a trench in which a CVD oxide layer is thickly formed on the trench wall formed by the primary trench and an ONO layer is formed on the remaining trench formed by the secondary trench in the trench wall formed by the secondary trench. Forming an internal electrode by filling a poly1 layer therein, forming a word line by depositing a poly2 layer on the insulating oxide layer formed on the internal electrode, and a gate including a source and a drain region on the P well region. An electrode is formed, and the IP3 layer is used to form the polyline layer contact region for the bit line, the drain and the trench of the moving gate. Trench capacitor cell with SDHT structure After forming a P-well region on a P-type substrate, a mask pattern layer is formed to form trenches in the P-well region and a P-type substrate by RIE etching, and then a trench for forming a diffusion layer on the trench wall by a selective doping method. In the method of manufacturing a capacitor cell, forming a primary trench in the P-well region, depositing a CVD oxide layer, and depositing a nitride in the CVD oxide layer and the nitride layer at the bottom of the primary trench with anisotropic etch; Forming a secondary trench from which the CVD oxide layer is removed and depositing PSG impurities on the secondary trench wall surface; And removing the nitride layer of the first trench wall after the removing process and forming a capacitor oxide layer on the first trench CVD oxide layer and the second trench wall. Forming an insulating oxide layer by filling an N-type poly1 layer in the formed trench, removing a mask pattern layer on the trench, and then planarizing the surface; and forming a word line poly layer on the insulating oxide layer. And forming a mobile gate poly2 layer to fabricate a trench capacitor cell having an SDHT structure characterized by a self-aligned contact process connecting the source and drain N + regions of the mobile gate to the poly3 layer for the bit line and the charge storage electrode of the trench. Way.

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