JPH02128466A - Dram cell having sdht structure and manufacture thereof - Google Patents

Abstract

PURPOSE: To increase the capacitance of the capacitor of a DRAM cell having an SDHT structure by increasing the degree of integration of the cell by reducing the area of the cell by using the self-aligned contact method. CONSTITUTION: After a P-type well area 15 is formed on a P-type silicon substrate 1, a primary trench 21 and a secondary trench 22 formed by further deepening the trench 21 to the substrate 1 are formed in the area 15. Then a CVD oxide film layer 16 is formed on the internal surface of the trench 21 and an ONO layer is formed on the surface of the oxide film layer 16 and the internal surface of the trench 22 as a capacitor oxide film layer 12. After the formation of the ONO layer, an internal charge storage electrode 13A is formed by filling up the trenches 21 and 22 with a conductive material. Then the capacitance of the capacitor of a DRAM cell having an SDHT structure is increased by forming an element separating insulating oxide layer 9 to a prescribed thickness in a fixed part of the upper section 24 of a trench capacitor 30 formed by the LOCOS method.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to SDHT (SIDE-
WALL DOPED HALF-VCCPLAT
This field relates to a DRAM cell having an E CAPACITOR structure and its manufacturing method, and in particular, to a DRAM cell having a conventional SDT
Increasing the capacitance of the capacitor compared to the structure capacitor, D
D with SDHT structure that reduces the area of the RAM cell
The present invention relates to a RAM cell and its manufacturing method.

[Prior art and problems to be solved by the invention] In the structure of a DRAM cell having a conventional SDT structure,
When a high CC voltage is applied to the P+ diffusion region formed on the side wall of the trench capacitor, which is the same as a P type substrate, the oxide film on the side wall is made to withstand the strength of the electric field generated in the trench capacitor. had to be thick. However, as the thickness of the oxide film increases, the capacitance of the capacitor decreases. Also, MOS
There is a problem in that the area of the FET increases when the following mask is used.

That is, a bit line contact mask is used when connecting the source N region of the MOSFET to the bit line, and an SNC (SNC) is used when connecting the drain N region of the MOSFET to the internal charge storage electrode of the trench capacitor.
When a mask is used, errors may occur in the mask arrangement due to the precision of process equipment. Therefore, since a minimum distance between the gate electrode and the mask must be maintained to prevent leakage current, the overall area of the cell increases.

[Means to solve the problem]

Therefore, it is an object of the present invention to overcome the above-mentioned disadvantages and to
Provided is a DRAM cell having an SDHT structure, which has a capacitor capacity larger than that of a DT structure capacitor, and which reduces the area of the DRAM cell, and a method for manufacturing the same.

A DRAM cell having an SDHT structure according to the present invention includes a P-type silicon substrate with a P-well region formed thereon, a primary trench formed in the P-well region, and a primary trench formed in the P-well region.
A secondary trench formed by further digging the secondary trench to the P-type silicon substrate, a CVD oxide film layer formed on the inner wall surface of the wall of the primary trench, the CVD oxide film layer and the secondary trench. a capacitor oxide film layer formed on the inner wall surface of the trench wall; an internal charge storage electrode made of a conductive material filled in the primary and secondary trenches; and a portion of the upper part of the primary trench and the 1
an insulating oxide film layer formed on the P-well region located near the secondary trench, and a portion of the P-well region on the outer wall of the secondary trench wall;
and a VC formed on a part of the P-type silicon substrate.
A C/2 N diffusion region for an external electrode, a gate electrode line formed on a part of the insulating oxide film layer and having a first insulating layer formed thereon, and a drain and source N region including the LDD region. An NMOS is formed in the P well region near the primary and secondary trenches, having a gate electrode with spacers on both sides and a first insulating film layer formed on the top.
FET, and a second conductive layer that connects the source N+ region of the MOSFET to a second conductive layer for a bit line to be formed later, and the drain N+ region of the MOSFET to the internal charge storage electrode while being insulated by a second insulating layer. A third insulating layer formed on the second bit line conductive layer, and a metal layer and a protective layer formed on the third insulating layer.

A method of manufacturing a DRAM cell having an SDHT structure according to the present invention includes the steps of: forming a P-well region on a P-type silicon substrate; A step of forming a primary trench formed from to a part of the P well region, a step of forming a CVD oxide film layer on and below the inner wall surface of the wall of the primary trench, and a step of forming a CVD oxide film layer formed in the primary trench. A step of forming a nitride film on the film layer, and a step of forming a nitride film located at the bottom of the primary trench and CVD.
removing a part of the oxide film layer thereby exposing a part of the P-well region, and forming a part of the P-type silicon substrate from the exposed P-well region with a wall having an inner wall surface and an outer wall surface; forming an N+ diffusion region over a part of the P-well region and a part of the P-type silicon substrate on the outer wall surface of the wall of the secondary trench; removing the remaining nitride film formed on the CVD oxide film on the inner wall surface of the trench wall, and forming a capacitor oxide film layer on the CVD oxide film and on the inner wall surface of the secondary trench wall. filling the primary trench and the secondary trench with an internal charge storage electrode material and planarizing the upper surface of the primary trench; A step of forming an insulating oxide film layer on the P-well region, a gate electrode line with spacers on both sides 1 of the upper part of the insulating oxide film, a first insulating layer formed on the upper part, and a drain and source including the LDD region. The N- region has an electrode with a spacer on both sides and a first insulating layer formed on the top.
a step of forming a MOSFET; the source N2 region of the MO3FET is connected to a second conductive layer for a bit line to be formed later, and the drain N2 region of the MO3FET is connected to the internal charge storage electrode while being insulated by a second insulating layer; forming a third insulating layer on the second conductive layer for bit lines; forming a metal layer on the upper end of the third insulating layer, and connecting the third insulating layer and the metal; The method is characterized in that it includes a step of forming a protective layer on the layer.

[Effect]

According to the present invention, since the impurity diffused into the side wall of the trench capacitor is an N+ diffusion region, a voltage of VCC/2 can be applied separately from the P-type silicon substrate. Thereby, the thickness of the capacitor oxide film can be reduced to about 80A. In addition, a relatively large capacitor capacity can be obtained compared to a capacitor having an SDT structure having the same area. Also,
When connecting the source N2 region and the bit line of the MOSFET, and the drain N2 region and the internal charge storage electrode of the trench capacitor, there is an advantage that high integration can be achieved using a self-aligned contact process method without using a mask.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an SDHT manufactured according to an embodiment of the present invention.
1 shows a cross-sectional view of a DRAM cell having a structure. In order to apply the CMOS process to reduce power consumption of highly integrated semiconductor devices, P-WE L is applied to the P-type silicon substrate 1.
An L region 15 (or N-WELL region) is formed. Then, in order to form a trench capacitor 30, a primary trench 21 is formed in a part of the P-well region 15 to a depth of approximately 2 μm, for example. Thereafter, a CVD oxide film layer 16 of approximately 1000 Å is formed on the inner wall surface 21A of the wall 2IC of the primary trench 21. What should be noted here is that charges are accumulated in the internal charge storage electrode 13A of the trench capacitor 30 due to the parasitic vertical NMOSFET formed between the drain N region 11' of the MO5FET 23 and the N+ diffusion region 14 on the side wall of the trench capacitor 30. In order to prevent charge from leaking from the drain N region to the N+ diffusion region 14 when The CV
The D oxide film layer 16 is formed thick. Also, as an example to explain this, the threshold voltage depending on the thickness of the oxide film■
Changes in and ■ Goo T when the current is -10A
FIG. 7 is a diagram showing changes in the voltage VGS between the DST electrode 8A and the source N region 11.

After forming the CVD oxide film 16, the CVD oxide film 16 is
Although not shown, a nitride film is formed on the layer to a thickness of, for example, about 500 Å, and the nitride film layer and the CVD oxide film layer 16 under the primary trench 21 are removed by anisotropic etching.

Then, a secondary trench 22 is formed over a part of the P-well region 15 at the bottom end of the trench 21 and a part of the P-type silicon substrate 1, which are exposed by removing the nitride film layer and the CVD oxide film layer 16.
is formed to a depth of approximately 5 μm. And VC for external electrode
The N+ diffusion region 14 of the C/2 plate is the P well region 15
and on a part of the P-type silicon substrate 1 on the outer wall surface 22B of the wall 22C of the secondary trench 22 by a known method. That is, an impurity doping source such as PSG containing an N impurity is formed on the nitride film (not shown) of the primary trench 21 and on the wall 22C of the secondary trench 22, and the impurity doping source is driven in. By diffusing N into the outer wall surface 22B of the wall 22C of the secondary trench 22 through processing,
+ A diffusion region is formed. Then, the remaining PSG impurities are removed.

After the above process, the nitride film layer formed in the primary trench 21 is removed, and the CVD oxide film layer 16 on the inner wall surface 21A of the wall 2IC (7) of the primary trench 21 and the secondary trench 2 are removed.
A capacitor oxide film layer 1 is formed on the inner wall surface 22A of the wall 22C of 2.
2, for example, the OH2 layer is formed to have a thickness of 100A or less. For reference, although not shown in the drawing, the fault (
(Folded) In a bit line cell arrangement, unit cells are arranged so as to periodically intersect with each other, so it is highly integrated semiconductor in which the N diffusion regions between the unit cells are arranged so as to be interconnected. In the memory element, in order to connect the VCC/2 electrode to the N diffusion region for the external electrode of the trench capacitor formed in the outermost shell, a CVD oxide film is formed on the side surfaces of the first and second trenches formed in the outermost shell. The layer and the capacitor oxide film are removed to form N 2 diffusion regions on the side walls of all the primary and secondary trenches.

After the above process, an N-type poly layer 13 is filled in the primary and secondary trenches 21 and 22 structures to form an internal charge storage electrode 13A, and a flattening process is performed to flatten the upper end 24 surfaces of the primary and secondary trenches. to become LOGO8(LOCALI)
An insulating oxide film layer 9 for element isolation is formed to a thickness of about 3000 Å on a certain portion of the upper part 24 of the trench capacitor 30 by a ZED OXIDATION OF 5 ILICON method.

After the above steps, in order to form an N-MOSFET above the P-well region 15 on the P-type silicon substrate 1, a gate oxide film layer 10 is formed, and then a conductive material for the gate electrode and gate electrode line is formed on the entire top. as poly layer 8 and 8
', and an LTO oxide film layer 18 as a first insulating layer are sequentially formed. Next, a gate electrode 8A is formed on the gate oxide film 10 and a gate electrode line 8B is formed on the insulating oxide film 9 by a gate electrode mask pattern process. On the other hand, LDD regions 20 are formed by ion implantation in the P well regions 15 around both sides of the gate electrode 8A.

Then, the gate electrode and gate electrode lines 8A and 8
An oxide film layer is formed on both sides of B, and oxide film spacers 25 are formed by anisotropic etching.

After the above steps, the other overall first conductive layer is PO.
LY layer 7 is formed to form a gate electrode and gate electrode line 8A.
Source and drain N+ regions 11 and 11' are removed by removing a certain portion of the POLY layer 7 above 8B and performing heat treatment to diffuse the N+ impurity contained in the POLY layer 7 into the P well region 15.
form.

After the above process, an LTO oxide film layer 6 is formed as a second insulating layer of the insulating layer, and after removing it leaving a certain part as shown in the drawing, a bit line POLYCI layer is formed on the second conductive layer.
POLY on source N+ region 11 to form DE layer 5
Connected to layer 7. After that, B is deposited as a third insulating layer on top of the bit line POLYCI DE layer 5.
An oxide film layer 4 doped with SG etc. is formed to form a metal layer 3 and 3' which will be formed later and a POLYCI for bit line.
The DE layer 5 is insulated.

Gate electrode and gate electrode line 8A serving as word line
When 8B and 8B are continuously connected, the resistance increases and a voltage drop occurs. Therefore, after the above process, the word line metal layers 3 and 3' are formed on the doped oxide film layer 4, and the metal layers 3 and 3' are applied to the gate electrode and the gate electrode line 8A for each 128th cell. and 8B to solve the problem of signal delay. after that,
A protective layer 2 is deposited on top of the metal layers 3 and 3' and the cell is heated.
Protect from shocks, currents, etc. The structure formed by the above steps is the DRAM having the SDHT structure according to this embodiment.
This is the structure of the cell.

On the other hand, in FIG. 1, the gate electrode 8A is formed and the MO3FE
T23 source and drain N regions 11 and 11
The structure of connecting the bit line to the bit line POLYCIDE layer 5 and the charge storage electrode 13A is a self-aligned contact process, which will be described in more detail with reference to FIGS. 2 to 6.

First, FIG. 2 will be explained. trench capacitor 3
An N-type MOSFET 23 is placed above the P well region 15 on the 0 side.
To form this, first, a gate oxide film 10, a poly layer 8 made of a conductive material for a gate electrode, and an LTO oxide film layer 18 as a first insulating layer are sequentially formed on the poly layer 8. Then, a nitride film layer 17 is formed on the LTO oxide film layer 18 in order to protect the LTO oxide film layer 18 during etching and prevent the oxide film from growing upward during the oxidation process, and then a mask pattern process is performed to form a nitride film layer 17 on top of the LTO oxide film layer 18. A portion is removed to form a gate electrode 8A. FIG. 2 is a sectional view showing this state.

Next, FIG. 3 will be explained. The N-
In order to reduce the junction depth of impurities, as shown in FIG.
A TO oxide layer 19 is grown. Next, N- impurity ions are implanted above the LTO oxide film layer 19 to form an LDD region 20. FIG. 3 is a sectional view showing this state. Here, the LDD region 20 is used as a gate electrode in order to prevent a strong electric field from being generated and accelerating electrons when an inversion layer is generated in the source and drain N regions 11 and 11' that will be formed later. A portion of the source and drain N+ regions adjacent to 8A is formed into a lightly doped N- region, which serves to reduce the strength of the electric field and prevent acceleration of electrons.

FIG. 4 is a cross-sectional view of a state in which an oxide film is further formed on both sides of the gate electrode 8A and then subjected to anisotropic etching to form an oxide film spacer 25. At this time, the oxide film spacer 25 prevents the N 2 impurity from being diffused into the LDD region 20 inside the lower end of the gate electrode 8A when the POLY layer 7 to be formed later is heat treated.

Furthermore, as shown in FIG. 5, after removing the nitride film layer 17 above the gate electrode 8A in FIG. A POLY layer 7 is formed on the top, and a portion of the POLY layer 7 above the gate electrode 8A is removed. Here, as above
Since the formation of the POLY layer 7 can be done without performing a separate mask process, the minimum effective distance due to errors in mask arrangement that occur during the mask pattern process as mentioned in the introduction is eliminated. Ru. That is, if the minimum distance is X, then the distance between the POLY layer 7 and the left side of the gate electrode 8A is X1, the distance between the right side of the gate electrode 8A and the POLY layer
Assuming that the distance between the two is X, and the distance between the left side of the gate electrode line 8B on the insulating oxide film layer 9 and the POLY layer 7 is X, and the width of the unit cell on the word line side is, for example, Y. The total area size by which the cell area can be reduced can be expressed as 3XY.

Next, FIG. 6 will be explained. PO formed in Figure 5
When the LY layer 7 is subjected to a heat treatment process to diffuse the impurities contained therein into the P well region 15, source and drain N+ regions 11 and 11' are formed. and,
POLY layer 7 which is the first conductive layer above the gate electrode 8A
and the second conductive layer, POLYCIDE for the bit line.
An LTO oxide layer 6 is grown as a second insulating layer to insulate layer 5 and is removed except for certain portions as shown in the drawing. And overall bit line POLY
A CI DE film layer is formed and connected to the source N region 11. FIG. 6 is a sectional view of this state.

As described above, in the present invention, the process of forming the POLY layer 7 after forming the gate electrode 8A, the process of forming the source and drain N regions 11 and 11', and the process of forming the first L
After forming the TO oxide film layer 18, the bit line POL
The YCI DE film layer is formed by a self-aligned contact process.

The operation of the present invention is performed in a unit DRAM cell in which a MOSFET and a trench capacitor are connected in series. That is, the gate electrode is connected to the word line, the source N region is connected to the bit line, and the drain N region is connected to the internal charge storage electrode of the trench capacitor, and the other electrode of the capacitor is connected to the P-type silicon substrate. Because of this structure, it is possible to perform operations such as accumulating or erasing charges. For example, when attempting to accumulate charge in the trench capacitor in the DRAM cell structure of the present invention, when a positive voltage is applied to the bit line and a positive voltage to the word line, the word line is connected to the drain N+ region by applying a positive voltage to the gate terminal. The source N+ region is conductive and the bit line applies a positive voltage to the source N+ region so that charge is stored in the capacitor via the drain N+ region.

In addition, when attempting to erase the accumulated charge using a trench capacitor, when zero voltage is applied to the bit line and a positive voltage is applied to the word line, a positive voltage is applied to the gate terminal and the source and drain N+ regions are made conductive. Source N+
Since this region has a lower potential than the drain N+ region, charges are discharged and erased from the trench capacitor through the drain N+ region toward the source N+ region. Therefore, information can be stored or read using such functions.

〔Effect of the invention〕

The DRAM cell having the SDHT structure of the present invention has the effect of not only increasing the capacitance as described above, but also reducing the area of the DRAM cell by using the self-aligned contact method, thereby contributing to higher integration.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a DRAM cell having an SDHT structure manufactured according to an embodiment of the present invention, and FIGS. 2 to 7 show self-aligned contacts (SELFA) during the DRAM cell process.
FIG. 2 is a cross-sectional view showing the gate electrode formed using the self-aligned contact process method, and FIG. 3 is a cross-sectional view showing the left and right sides of the gate electrode in FIG. FIG. 4 is a cross-sectional view in which an oxide film is formed on the upper part of the silicon substrate and an LDD region is formed in the P-WELL L region. FIG. Figure 5 is the fourth
Figure 6 is a cross-sectional view of a POLY layer formed on the spacer on the left and right sides of the gate electrode, and Figure 6 shows the source and drain N+ regions formed in the drive-in process after the process in Figure 5, and the LTO oxide film formed on the top of the gate electrode. FIG. 7 is a cross-sectional view of a state in which a POLYCI DE layer for a bit line is formed on the top of the POLY layer, and FIG. This is a diagram. 1... P-type silicon substrate, 2... protective layer, 3...
Metal layer, 4... Doped oxide film layer, 5... PL
YCIDE layer, 6... LTO (LOW TEMPERATURE 0XIDE) oxide film layer, 7
...POLY (I NTER CONNECT
I0NPOLY) layer, 8 and 8'...poly layer,
9... Insulating oxide film layer, 10... Gate oxide film layer, 1
1 and 11'...source and drain N regions, 1
2...ONO (OX I DE-N I TRID
E-OX I DE) layer, 13...POLY layer, 14
...N+ diffusion region, 15...P type WELL region, 1
6...CVD (CHEMICAL VAPOURE)
DDEPO8I T I ON) Oxide film layer, 17...
Nitride film layer, 18... LTO oxide film layer, 19... Oxide film layer, 20... LDD (LIGHTLY DOPE
DDRAIN) region, 21... primary trench, 22...
...Secondary trench. Representative Patent Attorney Yoshiki Hasejo
Salt 1) Tatsuya 15/ 15/

Claims (1)

[Claims] 1. A P-type silicon substrate on which a P-well region is formed; a primary trench formed in the P-well region;
A secondary trench formed by further digging the secondary trench to the P-type silicon substrate, a CVD oxide film layer formed on the inner wall surface of the wall of the primary trench, the CVD oxide film layer and the secondary trench. a capacitor oxide film layer formed on the inner wall surface of the trench wall, an internal charge storage electrode made of a conductive material filled in the primary and secondary trenches, a part of the upper part of the primary trench and the an insulating oxide film layer formed on the P-well region located near the primary trench; and a portion of the P-well region on the outer wall of the secondary trench and a portion of the P-type silicon substrate. taV_
A N^+ diffusion region for an external electrode of C_C/2, a gate electrode line formed on a part of the above insulating oxide film layer and having a first insulating layer formed thereon, and a drain and source N which includes an LDD region. The N- well region is formed in the P-well region near the primary and secondary trenches, with a gate electrode having a ^+ region, spacers on both sides, and a first insulating film layer formed above.
MOSFET, the source N^+ region of the MOSFET is connected to a second conductive layer for a bit line to be formed later, and the drain N^+ region of the MOSFET is connected to the internal charge storage electrode while being insulated by the second insulating layer. an SDHT structure including a first conductive layer connected to each other, a third insulating layer formed on the second conductive layer for bit lines, and a metal layer and a protective layer formed on the third insulating layer. DRAM cell. 2. The first conductive layer is formed in the source N^+ region and the drain N, excluding the gate electrode above the insulating oxide film layer and a part of the upper part of the first insulating layer formed on the gate electrode line. The drain N
the first conductive layer formed on the first conductive layer excluding a part of the upper part of the first conductive layer formed on the source N^+ region; 2. The source N^+ region is connected to a second conductive layer for a bit line formed on the second insulating layer, and the source N^+ region is connected to the second conductive layer for a bit line.
A DRAM cell having the SDHT structure described in . 3. A method for manufacturing a DRAM cell having an SDHT structure, which includes the steps of: forming a P-well region in a P-type silicon substrate; A step of forming a primary trench that extends up to a part of the P-well region, a step of forming a CVD oxide film layer on the inner wall surface of the wall of the primary trench, and a step of forming a CVD oxide film layer on the inner wall surface of the primary trench. A step of forming a nitride film, and a step of forming a nitride film located at the bottom of the primary trench and CVD.
removing a portion of the oxide film layer thereby exposing a portion of the P-well region; forming an N^+ diffusion region on the outer wall surface of the wall of the secondary trench over a part of the P-well region and a part of the P-type silicon substrate; removing the remaining nitride film formed on the CVD oxide film on the inner wall surface of the wall of the primary trench, and forming a capacitor oxide film on the CVD oxide film and the inner wall surface of the secondary trench wall; filling the primary trench and the secondary trench with an internal charge storage electrode material and planarizing the upper surface of the primary trench; A step of forming an insulating oxide film layer on the P-well region near the trench, a gate electrode line with spacers on both sides of the top of the insulating oxide film, and a first insulating layer formed on the top, and a step that includes the LDD region. An N layer having drain and source N^+ regions, spacers on both sides, and electrodes with a first insulating layer formed on top.
- a step of forming a MOSFET; the source N^+ region of the MOSFET is placed in a second conductive layer for a bit line to be formed later; forming a third insulating layer on the second bit line conductive layer; forming a metal layer on the upper end of the third insulating layer; 3. A method for manufacturing a DRAM cell having an SDHT structure, the method comprising the step of forming a protective layer on an insulating layer and a metal layer. 4. The step of forming the N^+ diffusion region includes doping impurities on the nitride film on the CVD oxide film layer formed on the inner wall surface of the wall of the above-mentioned primary trench and on the inner wall surface of the wall of the secondary trench. dopant sauce
N is formed on the outer wall surface of the wall of the secondary trench by heat-treating the impurity dopant source through a drive-in process.
4. The SDHT according to claim 3, comprising the steps of forming a diffusion region and completely removing the impurity dopant source from the primary and secondary trenches.
A method for manufacturing a DRAM cell having a structure. 5. The step of forming the MOSFET and the step of connecting the MOSFET include sequentially forming a gate oxide film, a conductive material for a gate electrode, a first insulating layer, and a nitride film layer on a P-type silicon substrate in which a P-well region is formed. etching the gate electrode conductive material, first insulating layer, and nitride film layer formed sequentially by a gate electrode mask pattern step; etching an oxide film on the left and right side surfaces of the gate electrode conductive material; After growing the layer, there is a step of forming LDD regions in the P-well regions on both sides of the gate electrode poly layer by ion implantation, and after further growing an oxide film on both sides of the gate electrode, oxidation is performed by anisotropic etching. forming a film spacer and removing the nitride film; and forming a first conductive layer containing impurities on the entire region and removing a part of the first conductive layer formed above the gate electrode. removing the internal charge storage electrode thereby connecting the internal charge storage electrode to a drain N^+ region to be formed later; and diffusing impurities contained in the first conductive layer into the P-well region by a heat treatment step to connect the source and drain electrodes to the P-well region. N^+
forming a second insulating layer on top of the entire region to form a source N
a step of removing a part of the second insulating layer formed above the source N^+ region; and a step of forming a second conductive layer for a bit line over the entire region, and forming a first conductive layer formed above the source N^+ region. 4. The D having an SDHT structure according to claim 3, further comprising a self-aligned contact step comprising a step of connecting with a conductive layer.
A method for manufacturing a RAM cell.