KR910001938Y1 - Signal selecting circuit - Google Patents
Signal selecting circuit Download PDFInfo
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- KR910001938Y1 KR910001938Y1 KR2019880007631U KR880007631U KR910001938Y1 KR 910001938 Y1 KR910001938 Y1 KR 910001938Y1 KR 2019880007631 U KR2019880007631 U KR 2019880007631U KR 880007631 U KR880007631 U KR 880007631U KR 910001938 Y1 KR910001938 Y1 KR 910001938Y1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/04113—Modifications for accelerating switching without feedback from the output circuit to the control circuit in bipolar transistor switches
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Abstract
내용 없음.No content.
Description
제1도는 종래의 회로도.1 is a conventional circuit diagram.
제2도는 본 고안의 회로도.2 is a circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
200, 225 : 신호 전달 회로 205 : 직류레벨 고정회로200, 225: signal transmission circuit 205: DC level fixed circuit
210 : 임피던스 정합회로 215 : 신호 제거회로210: impedance matching circuit 215: signal removal circuit
220 : 선택 스위치부 TR1∼TR6 : 트랜지스터220: selection switch section TR1 to TR6: transistor
R1-R23: 저항 C1-C5: 콘덴서R 1 -R 23 : resistor C 1 -C 5 : condenser
SW1, SW2 : 스위치SW1, SW2: switch
본 고안은 다수의 입력신호가 있는 회로에서 출력단에 1개의 출력을 시키고자하는 회로에 있어서 신호 선택회로에 관한것이다.The present invention relates to a signal selection circuit in a circuit for outputting one output to an output terminal in a circuit having a plurality of input signals.
종래에는 제1도에 도시한 바와같이 2입력신호를 온/오프하는 2개의 스위치와 트랜지스터를 사용하여 그중 1신호를 선택하여 출력하였다.Conventionally, as shown in FIG. 1, one of the signals is selected and output using two switches and transistors for turning on / off two input signals.
따라서 직류레벨의 변화나 스위치의 동작시 2개를 선택해야되는 번거러움이 있었으며, 2개의 신호를 동시에 출력단에서 제거하고자 할때 2개의 스위치를 동시에 조작하는 불편한 문제점이 있었다.Therefore, there was a hassle to select two at the time of change of DC level or operation of switch, and there was an inconvenience of operating two switches simultaneously when trying to remove two signals at the same time.
본 고안은 상기와 같은 문제점을 해결하기 위하여 안출한 것인바, 2신호를 전달하도록 구성된 전달회로인 2신호를 선택하는 스위치회로와 2신호의 출력을 직류로 고정하는 직류레벨 고정회로 및 임피던스 정합을 위한 정합회로로 구성하여 상기 스위치회로에 3단자가 있는 스위치를 사용하여 2신호의 입력을 선택하도록 하고 하나의 접지단자를 두어 2개의 신호를 동시에 제거하도록 한것으로 이하 첨부된 도면에 의하여 본 고안을 상세히 설명하면 다음과 같다.The present invention has been made to solve the above problems, a switch circuit for selecting two signals which is a transmission circuit configured to deliver two signals and a DC level fixed circuit for fixing the output of the two signals to DC and impedance matching In order to select the input of two signals using a switch having three terminals in the switch circuit by configuring a matching circuit for the two circuits to remove the two signals at the same time by putting one ground terminal in detail the present invention in accordance with the accompanying drawings The explanation is as follows.
제2도는 본 고안의 회로도로써 2신호 (A)(B) 입력중 신호(A)의 전달회로(200)는 트랜지스터(TR2)에 저항(R5)(R6)(R9)을 연결하여 구성하고 신호(B)의 전달회로(225)는 트랜지스터(TR4)에 저항(R7)(R8)(R15)을 연결하여 구성하며 상기 전달회로(200)(225)의 출력신호를 직류레벨로 고정시키는 고정회로(205)는 저항(R10)(R17)과 콘덴서(C3)(C5)를 각각 병렬로 연결하여 구성한다.FIG. 2 is a circuit diagram of the present invention, and the transfer circuit 200 of the signal A during the input of the two signals A and B is configured by connecting the resistors R5, R6, and R9 to the transistor TR2. The transfer circuit 225 of (B) is configured by connecting the resistors R7, R8, and R15 to the transistor TR4, and fixes the output signal of the transfer circuits 200 and 225 at a DC level. 205 is configured by connecting the resistors R10 and R17 and the capacitors C3 and C5 in parallel.
상기 직류레벨 고정회로(205)에서 출력된 신호의 임피던스 매칭을 시키는 정합회로(210)는 트랜지스터(TR3)에 저항(R11∼R14)을 연결하여 구성하고 입력신호(A)(B)를 동시에 제거하기 위한 제거회로(215)는 트랜지스터(TR5)(TR6)에 저항(R16)(R20∼R23)을 연결하여 구성하며 신호선택 스위치부(220)는 공통접지부와 선택단자(C∼E)로 구성하여 상기 선택단자(C)는 저항(R18)을 통하여 신호(A) 선택 전달회로(200)에 연결되고 상기 선택단자(D)는 저항(R19)을 통하여 신호(B) 선택 전달회로(225)에 연결되어 상기 선택단자(E)는 2신호 제거회로(215)에 각각 연결된다.The matching circuit 210 for impedance matching of the signal output from the DC level fixing circuit 205 is configured by connecting the resistors R11 to R14 to the transistor TR3 and simultaneously removing the input signals A and B. The removal circuit 215 is configured by connecting resistors R16 (R20 to R23) to transistors TR5 and TR6, and the signal selection switch unit 220 is connected to the common ground and the selection terminals C to E. In this case, the selection terminal C is connected to the signal A selection transfer circuit 200 through the resistor R18, and the selection terminal D is the signal transfer selection circuit 225 through the resistor R19. The select terminal (E) is connected to the two signal cancellation circuit 215, respectively.
이하 이들의 작용효과를 설명한다.The effect of these will be described below.
제2도에서 2신호(A)(B)가 입력될때 상기 2신호를 선택하여 출력단에 전달하기 위하여 선택스위치부(220)의 접지단자를 스위치단자(C)에 연결하면 상기 신호(A) 전달회로(220)의 트랜지스터(TR2) 베이스에 로우신호가 인가되어 상기 트랜지스터(TR2)는 도통한다. 상기 트랜지스터(TR2)가 도통하면 신호(A)는 에미터와 콜렉터를 통하여 직류레벨 고정회로(205)의 저항(R10)과 콘덴서(C3)를 거쳐 콘덴서(C4)를 통해 임피던스 정합회로(210)에 인가되며, 상기 선택스위치부(220)의 접지단자를 스위치단자(D)에 연결하면 상기 신호(B) 전달회로(225)의 트랜지스터(TR4) 베이스에 로우신호가 인가되어 상기 트랜지스터(TR4)는 도통된다.In FIG. 2, when the two signals A and B are input, the ground terminal of the selector switch 220 is connected to the switch terminal C to select the two signals and transmit them to the output terminal. A low signal is applied to the base of the transistor TR2 of the circuit 220 to conduct the transistor TR2. When the transistor TR2 conducts, the signal A passes through an emitter and a collector, through a resistor C10 through a resistor R10 and a capacitor C3 of the DC level fixed circuit 205, and through a capacitor C4. When the ground terminal of the selector switch 220 is connected to the switch terminal D, a low signal is applied to the base of the transistor TR4 of the signal transfer circuit 225 so that the transistor TR4 is applied. Is conducting.
상기 트랜지스터(TR4)가 도통되면 상기 신호(B)는 에미터와 콜렉터를 통하여 상기 직류레벨 고정회로(205)의 저항(R17)과 콘덴서(C5)를 거쳐 상기 콘덴서(C4)를 통해 상기 임피던스 정합회로(210)에 인가된다. 이와같이 임피던스 정합회로(210)에 인가된 신호는 트랜지스터(TR3)를 도통시켜 출력단으로 출력된다. 또한 상기 선택스위치부(220)의 접지단자를 스위치단자(E)에 연결하면 2신호 제거회로(215)의 트랜지스터(TR5) 베이스에 로우신호가 인가되어 상기 트랜지스터(TR5)는 도통시켜 상기 도통된 트랜지스터(TR5)의 콜렉터에 접속된 트랜지스터(TR6)의 베이스에 하이신호가 인가되어 상기 트랜지스터(TR6)도 도통한다.When the transistor TR4 is turned on, the signal B is matched to the impedance through the capacitor C4 through the resistor R17 and the capacitor C5 of the DC level fixed circuit 205 through an emitter and a collector. Is applied to the circuit 210. In this way, the signal applied to the impedance matching circuit 210 conducts the transistor TR3 and is output to the output terminal. In addition, when the ground terminal of the selection switch unit 220 is connected to the switch terminal E, a low signal is applied to the base of the transistor TR5 of the two-signal removal circuit 215 so that the transistor TR5 conducts the conductive state. A high signal is applied to the base of the transistor TR6 connected to the collector of the transistor TR5 to conduct the transistor TR6.
상기 트랜지스터(TR6)가 도통되면 상기 직류레벨 고정회로(205)를 통과한 신호(A)나 신호(B)는 도통된 트랜지스터(TR6)의 콜렉터와 에미터를 거쳐 접지되므로 상기 임피던스 정합회로(210)를 통하여 출력되지 못한다.When the transistor TR6 is turned on, the signal A or B, which has passed through the DC level fixing circuit 205, is grounded through the collector and emitter of the transistor TR6 that is turned on, so that the impedance matching circuit 210 is grounded. ) Is not output through
이상에서 설명한 바와같이 본 고안은 스위치 1개를 사용하여 2신호를 컨트롤 함으로써 출력에 2신호중 1신호를 선택하여 출력시키는 효과와 2신호를 동시에 제거하여 출력을 로우로 만들수 있는 장점이 있는 것이다.As described above, the present invention has the advantage of controlling the two signals by using one switch to select and output one of the two signals to the output, and simultaneously remove the two signals to make the output low.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880007631U KR910001938Y1 (en) | 1988-05-24 | 1988-05-24 | Signal selecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880007631U KR910001938Y1 (en) | 1988-05-24 | 1988-05-24 | Signal selecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR890023918U KR890023918U (en) | 1989-12-04 |
| KR910001938Y1 true KR910001938Y1 (en) | 1991-03-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019880007631U KR910001938Y1 (en) | 1988-05-24 | 1988-05-24 | Signal selecting circuit |
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| Country | Link |
|---|---|
| KR (1) | KR910001938Y1 (en) |
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1988
- 1988-05-24 KR KR2019880007631U patent/KR910001938Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR890023918U (en) | 1989-12-04 |
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