KR900019174A - Semiconductor device manufacturing process - Google Patents

Semiconductor device manufacturing process Download PDF

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KR900019174A
KR900019174A KR1019900005861A KR900005861A KR900019174A KR 900019174 A KR900019174 A KR 900019174A KR 1019900005861 A KR1019900005861 A KR 1019900005861A KR 900005861 A KR900005861 A KR 900005861A KR 900019174 A KR900019174 A KR 900019174A
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temperature
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dehydration
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KR970005142B1 (en
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앤 프레밍 데브라
윌프레드 죤슨 2세 데이빗
신가 쇼바
그랜드 지.반 위테르트 리
제이.지드직 죠지
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오레그 이. 앨버
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31625—Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/133—Reflow oxides and glasses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/902—Capping layer

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

내용 없음No content

Description

반도체 소자 제조공정Semiconductor device manufacturing process

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3A내지 3D도는 상이한 처리 상태로 소결된 SiO2 가 도핑된 P2O5의 샘플의회학적 표현을 비교하는 도시도.3A to 3D are diagrams comparing the scientific representations of samples of SiO 2 doped P 2 O 5 sintered in different processing conditions.

Claims (19)

반도체 표면의 적어도 일부분상에 입자 빔 침착에 의해 포스포실리게이트 유리 목표 물질을 침착하며 따라서, 상기 표면의 적어도 일부분이 1에서 15몰퍼센트 P2O5를 포함하는 접촉 포스포실리케이트 유리 영역으로 커버되는 반도체 소자를 제조하는 공정에 있어서, 상기 유리 물질이, a) 50에서 400㎡/g의 범위내에 표면 영역을 가지며 25에서 55의 중량퍼센트 실리카를 포함하는 졸을 형성하기에 충분한 량이 부가되는 증발된 실리카와, 시제등급 인산의 수성액 및 졸을 함께 혼합하고 상기 졸을 겔화하는 것을 허용하는 겔을 형성하는 단계와, b) 14일 까지의 기간동안 순환 공기 및 온도상태에서 상기 겔을 건조하는 단계와, c) 시간당 250에서 350℃의 비율로 500에서 700℃의 범위내의 온도까지 가열하므로 상기 건조된 겔을 탈수하고 10분에서 3시간의 기간동안 상기 온도에서 유지하는 단계와, d) 상기 탈수 온도에서 600에서 1200℃의 범위내의 희망 피크 온도까지 시간당 100에서180℃의 비율로 상기 겔을 가열하므로 상기 탈수된 겔을 유리로 소결하는 단계 및 e) 주로 상기 피크 온도에 도달하여, 상기 소결된 유리를 냉각하는 단계를 포함하는 절차에 의해 제조되는데, 상기 탈수 및 소결 단계가 불활성 가스를 포함한 흐르는 공기중에서 관리되는 것을 특징으로 하는 반도체 소자 제조공정.Depositing a phosphorosigate glass target material by particle beam deposition on at least a portion of the semiconductor surface and thus covering at least a portion of the surface with a contact phosphorosilicate glass region comprising 1 to 15 mole percent P 2 O 5 . In the process of manufacturing a semiconductor device, the evaporation of the glass material comprises: a) an amount sufficient to form a sol having a surface area in the range of 50 to 400 m 2 / g and comprising 25 to 55 weight percent silica; Mixed silica with an aqueous solution of a reagent grade phosphoric acid and a sol to form a gel that allows the sol to gel, and b) drying the gel in circulating air and temperature for a period of up to 14 days. And c) heating the dried gel to a temperature in the range of 500 to 700 ° C. at a rate of 250 to 350 ° C. per hour and dehydrating the dried gel for a period of 10 minutes to 3 hours. Sintering the dehydrated gel into glass by d) heating the gel at a rate of 100 to 180 ° C. per hour from the dehydration temperature to a desired peak temperature in the range of 600 to 1200 ° C. at the dehydration temperature; and e) produced by a procedure comprising cooling the sintered glass, primarily by reaching the peak temperature, wherein the dewatering and sintering steps are managed in flowing air containing an inert gas. . 제1항에 있어서, 상기 유리 물질 영역이 특허 2내지 10몰퍼센트P2O5와 나머지의 SiO2를 포함하는 것을 특징으로 하는 반도체 소자 제조 공정.The process of claim 1 wherein the glass material region comprises patents 2 to 10 mole percent P 2 O 5 and the remaining SiO 2 . 제1또는 제2항에 있어서, 상기 실리카가 150에서 250㎡/g주로, 대략200㎡/g의 범위내의 표면 영역을 포함하는 것을 특징으로 하는 반도체 소자 제조 공정.The process of claim 1 or 2, wherein the silica comprises a surface area in the range of from 150 to 250 m 2 / g, approximately 200 m 2 / g. 제1, 제2 또는 제3항에 있어서, 상기 실리카가, 30에서 50중량퍼센트 실리카를 포함하는 졸을 형성하기위해, 부가되는 것을 특징으로 하는 반도체 소자 제조 공정.The process of claim 1, 2 or 3, wherein the silica is added to form a sol comprising 30 to 50 weight percent silica. 제1내지 제4항중 어느 한 항에 있어서, 상기 겔의 상기 건조가 3일동안 실행되는 것을 특징으로 하는 반도체 소자 제조 공정.The process of claim 1, wherein the drying of the gel is performed for three days. 제1내지 제5항중의 어느 한항에 있어서, 상기 건조된 겔이 상기 탈수 온도까지 약 300℃/hr의 비율로 가열되는 것을 특징으로 하는 반도체 소자 제조 공정.The process of claim 1, wherein the dried gel is heated to the dehydration temperature at a rate of about 300 ° C./hr. 7. 제1내지 제6항중 어느 한항에 있어서, 상기 탈수가 2시간동안 약 650℃의 온도에서 상기 건조된 겔을 가열하므로 이루어지는 것을 특징으로 하는 반도체 소자 제조 공정.The process of any one of claims 1 to 6, wherein the dehydration is accomplished by heating the dried gel at a temperature of about 650 ° C for 2 hours. 제1내지 제7항중 어느 한항에 있어서, 상기 탈수 온도에서 피크 소결 온도까지의 상기 가열이 시간당 140에서 150℃, 주로 시간당 약 145℃의 비율로 실행되는 것을 특징으로 하는 반도체 소자 제조 공정.8. The process of claim 1, wherein the heating from the dehydration temperature to the peak sintering temperature is performed at a rate of 140 to 150 ° C. per hour, primarily about 145 ° C. per hour. 9. 제1내지 제8항중 어느 한항에 있어서, 상기 피크 소결 온도가 1000에서 1200℃의 범위, 주로, 약 1125℃의 범위내에 있는 것을 특징으로 하는 반도체 소자 제조 공정.The process of claim 1, wherein the peak sintering temperature is in the range of 1000 to 1200 ° C., mainly in the range of about 1125 ° C. 10. 제1내지 제9항중 어느 한항에 있어서, 상기 불활성 가스가 헬륨을 포함하는 것을 특징으로 하는 반도체 소자 제조 공정.10. The process of claim 1, wherein the inert gas comprises helium. 제1내지 제10항중 어느 한항에 있어서, 상기 탈수가 적어도 하나의 cl2, SiF4, 플루오로카본, 클로로플루오로카본 및 ccl4가스가 불활성 가스에 포함된 공기에서 실행되는 것을 특징으로 하는 반도체 소자 제조 오정.The semiconductor according to claim 1, wherein the dehydration is carried out in air containing at least one cl 2 , SiF 4 , fluorocarbon, chlorofluorocarbon and ccl 4 gas contained in an inert gas. Device manufacturing mistake. 제1내지 제11항중의 어느 한항에 있어서, 상기 탈수가 볼륨으로 약8.5% cl2, 25% SiF4, 및 89% He를 포함하는 공기에서 실행되는 것을 특징으로 하는 반도체 소자 제조 공정.The process of any one of claims 1 to 11 wherein the dehydration is carried out in air comprising about 8.5% cl 2 , 25% SiF 4 , and 89% He in volume. 제1내지 제12항중 어느 한항에 있어서, 입지 빔 절차가 e-빔 침착인 것을 특징으로 하는 반도체 소자 제조 공정.13. A process according to any of the preceding claims, wherein the location beam procedure is e-beam deposition. 제1내지 제13항중 어느 한항에 있어서, 상기 반도체가 lmP와 GaAs로 구성된 그룹에서 선택된 Ⅲ-Ⅴ화합물 반도체와 InP 및 GaAs에 매칭된 화합물 입자를 포함하는 것을 특징으로 하는 반도체 소자 제조 공정.The process of claim 1, wherein the semiconductor comprises a III-V compound semiconductor selected from the group consisting of lmP and GaAs and compound particles matched to InP and GaAs. 제1내지 제14항중 어느 한항에 있어서, 상기 포스포실리게이트 유리 영역이 이온 주입 표면과 접촉하는 것을 특징으로 하는 반도체 소자 제조 공정.15. A process as claimed in any preceding claim wherein said phosphosigate glass region is in contact with an ion implantation surface. 제1내지 제15항중 어느 한항에 있어서, 유리 물질과 접촉한 상기 이온 주입 표면이 이온 주입을 활성화하기 위해 어닐되며, 반도체 물질이 이고 상기 어닐이 10초에서 10분까지의 기간동안 750에서 1000℃의 범위내의 온도에서 실행된 급속한 열절 어닐이며, 온도가 낮으면 낮을수록 시간이 더 걸리는 것을 특징으로하는 반도체 소자 제조 공정.The method of claim 1, wherein the ion implantation surface in contact with the glass material is annealed to activate ion implantation, wherein the semiconductor material is and the annealing is at 750 to 1000 ° C. for a period of 10 seconds to 10 minutes. A rapid thermal annealing carried out at a temperature within the range of. The semiconductor device manufacturing process characterized in that the lower the temperature, the longer it takes. 제16항에 있어서, 상기 급속한 열적 어닐이 약 10초동안 800에서 1000℃의 범위내의 온도에서 실행되고 약 10분동안 750에서 850℃의 범위내의 온도에서 실행되는 것을 특징으로 하는 반도체 소자 제조 공정.The process of claim 16 wherein the rapid thermal annealing is performed at a temperature in the range of 800 to 1000 ° C. for about 10 seconds and at a temperature in the range of 750 to 850 ° C. for about 10 minutes. 제1내지 제17항중 어느 한항에 있어서, 상기 포스포실리케이트 유리가 1에서 12몰퍼센트 P2O5와 나머지 SiO2를 포함하며, 상기 실리카가 약 200m2/g의 표면 영역을 갖고, 30에서 50중량퍼센트 실리카를 포함하는 졸을 형성하기 위해 물과 인산을 결합시키며, 상기 인산이 유리에 희망 함유량의 P2O5를 얻기 위해서 통틀어 부가되며, 상기 겔이 3일동안 건조되며, 상기 건조된 겔이 2시간동안 유지되는 약 650℃의 비율로 가열되므로 탈수되며, 상기 탈수가 헬륨, cl2, SiF4를 포함한 흐르는 공기에서 실행되며, 상기 탈수된 겔이 시간당 140에서 150℃의 비율로 1000에서 1175℃의 피크 온도까지 가열되고 그후 냉각로에서 냉각되는 것을 특징으로 하는 반도체 소자 제조 공정.18. The method of claim 1, wherein the phosphosilicate glass comprises 1 to 12 mole percent P 2 O 5 and the remaining SiO 2 , wherein the silica has a surface area of about 200 m 2 / g, and at 30 Water and phosphoric acid are combined to form a sol comprising 50% by weight silica, the phosphoric acid is added throughout the glass to obtain the desired content of P 2 O 5 , the gel is dried for 3 days and the dried The gel is dehydrated as it is heated at a rate of about 650 ° C. which is maintained for 2 hours, and the dehydration is carried out in flowing air containing helium, cl 2 , SiF 4 , and the dehydrated gel is 1000 at a rate of 140 to 150 ° C. per hour Heating to a peak temperature of 1175 ° C. at and then cooled in a cooling furnace. 제1내지 제18항중 어느 한항에 있어서, 상기 반도체 표면이 InP 및 GaAs로부터 선택된 화합물 반도체의 표면이고, 상기 소자가 에벌런쉬 포토다이오드인 것을 특징으로 하는 반도체 소자 제조 공정.19. The process of claim 1 wherein the semiconductor surface is a surface of a compound semiconductor selected from InP and GaAs and the device is an avalanche photodiode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900005861A 1989-05-01 1990-04-26 Fabrication of semiconductor devices using phosphosilicate glasses KR970005142B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP345924 1989-05-01
US07/345,924 US5047369A (en) 1989-05-01 1989-05-01 Fabrication of semiconductor devices using phosphosilicate glasses
US345924 1989-05-01

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KR970005142B1 (en) 1997-04-12
ES2100162T3 (en) 1997-06-16
EP0396307A2 (en) 1990-11-07
DE69030401T2 (en) 1997-07-17
DE69030401D1 (en) 1997-05-15
CA2014934C (en) 1993-05-25
HK108597A (en) 1997-08-22
CA2014934A1 (en) 1990-11-01
JP2511556B2 (en) 1996-06-26
EP0396307A3 (en) 1991-11-27
JPH02306628A (en) 1990-12-20
US5047369A (en) 1991-09-10
EP0396307B1 (en) 1997-04-09

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