KR900009586Y1 - Circuit for controlling dimensious and shape - Google Patents
Circuit for controlling dimensious and shape Download PDFInfo
- Publication number
- KR900009586Y1 KR900009586Y1 KR2019850017500U KR850017500U KR900009586Y1 KR 900009586 Y1 KR900009586 Y1 KR 900009586Y1 KR 2019850017500 U KR2019850017500 U KR 2019850017500U KR 850017500 U KR850017500 U KR 850017500U KR 900009586 Y1 KR900009586 Y1 KR 900009586Y1
- Authority
- KR
- South Korea
- Prior art keywords
- resistor
- circuit
- vertical size
- variable
- video signal
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
- H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
- H04N3/23—Distortion correction, e.g. for pincushion distortion correction, S-correction
Abstract
내용 없음.No content.
Description
제 1 도는 본 고안의 회로도.1 is a circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 캐스코드 영상출력회로 20 : 휘도 가변회로10: cascode video output circuit 20: luminance variable circuit
30 : 수직사이즈 가변회로 1 : 영상신호 입력단자30: Vertical size variable circuit 1: Video signal input terminal
2 : 수직사이즈 회로 R10,R12: 저항2: vertical size circuit R 10 , R 12 : resistance
C1: 콘덴서 C1: 다이오드C 1 : condenser C 1 : diode
VR2: 가변저항VR 2 : Variable resistor
본 고안은 캐스코드 영상출력을 이용한 모니터에 관한 것으로, 특히 휘도가 밝을 때에 수직 사이즈(size)가 변화하는 현상을 보상하기 위한 모니터에서의 수직사이즈 보상 회로에 관한 것이다.The present invention relates to a monitor using a cascode image output, and more particularly, to a vertical size compensation circuit in a monitor for compensating for a phenomenon in which the vertical size changes when brightness is bright.
종래의 TV나 모니터는 휘도가 밝게 되면 비임 전류가 증가하게 됨과 아울러 고압이 낮아지게 되어, 수직 사이즈가 커지는 현상이 발생됨으로써, 눈에 거슬리게 되는 문제점이 있었다.Conventional TVs and monitors have a problem in that the brightness increases, the beam current increases and the high pressure decreases, resulting in an increase in the vertical size.
본 고안은 이러한 점을 감안하여 캐스코드 형상 출력회로의 영상신호의 하이 되는 부분을 수직 사이즈 가변회로에 궤환시킴으로서 수직 사이즈가 안정하게 유지되도록 안출한 것으로서, 이를 첨부한 도면에 의하여 상세히 설명하면 다음과 같다.The present invention is designed to maintain the vertical size stably by feeding back the portion of the video signal of the cascode shape output circuit to the vertical size variable circuit in view of such a point. same.
트랜지스터(Q2), (Q3), 브라운관(3), 코일(L) 저항(R4-R8) 및 콘덴서(C2), (C3)로 구성된 캐스코드 영상출력회로(10)와, 트랜지스터(Q1), 저항(R2), (R3), 가변저항(VR1) 및 콘덴서(C1)로 구성된 휘도 가변회로(20)와, 저항(R12), 가변저항(VR2) 및 통상의 수직사이즈 회로(2)로 구성된 수직사이즈 가변회로(30)를 영상신호 입력단자(1)에 연결 접속한 모니터 회로에 있어서 영상신호 입력단자(1)에 접속된 저항(R11)과 캐스코드 영상출력회로(10)의 트랜지스터(Q3)의 베이스에 접속된 저항(R9)의 접속점(a)에 저항(R10)을 통하여 수직 사이즈 가변회로(30)의 가변저항(VR2)과 저항(R12)사이에 다이오드(D1)를 접속함과 아울러 저항(R10)과 다이오드(D1)의 접속점에 콘덴서(C4)를 접속하여 구성된 것이다.A cascode image output circuit 10 composed of transistors Q 2 , Q 3 , CRT, coil L resistors R 4 -R 8 , and capacitors C 2 , C 3 , and , A luminance variable circuit 20 composed of a transistor Q 1 , a resistor R 2 , a R 3 , a variable resistor VR 1 , and a capacitor C 1 , a resistor R 12 , a variable resistor VR 2 ) and a resistor (R 11 ) connected to the video signal input terminal 1 in the monitor circuit in which the vertical size variable circuit 30 composed of the normal vertical size circuit 2 is connected to the video signal input terminal 1; ) And the variable resistor of the vertical size variable circuit 30 through the resistor R 10 at a connection point a of the resistor R 9 connected to the base of the transistor Q 3 of the cascode image output circuit 10. The diode D 1 is connected between the VR 2 ) and the resistor R 12 , and the capacitor C 4 is connected to the connection point between the resistor R 10 and the diode D 1 .
미설명 부호 B1 *,B2 *는 직률전원이고, 2는 수직 사이즈회로이다.Unexplained symbols B 1 * , B 2 * are power supply units, and 2 is a vertical size circuit.
이와 같이 구성된 본 고안의 작용효과를 설명하면 다음과 같다.Referring to the effect of the present invention configured as described above are as follows.
영상신호 입력단자(1)에 영상신호가 입력되는 상태에서, 가변저항(VR1)의 가변단자를 저항(R2)에 가깝게 하면 트랜지스터(Q1)의 베이스,에미터 전압이 상승하여 영상신호 입력단자(1)에 중첩되는 직류 성분이 높게 되어서 저항(R11), (R9)을 통하여 캐스코드 증폭기의 증폭도가 커져 휘도가 밝아지고, 비임전류가 증가하게 된다.When the video signal is input to the video signal input terminal 1 , when the variable terminal of the variable resistor VR 1 is close to the resistor R 2 , the base and emitter voltages of the transistor Q 1 rise to increase the video signal. The DC component superimposed on the input terminal 1 becomes high so that the amplification degree of the cascode amplifier is increased through the resistors R 11 and R 9 so that the brightness becomes bright and the beam current increases.
이와 같은 상태에서 상기한 중첩되는 직류성분을 저항(R10) 및 다이오드(D1)를 통하여 가변저항(VR2)에 가해주게 되면, 가변저항(VR2)의 전압강하는 증가하게 되어 다이오드(D1)의 캐소드전압은 상승되므로 저항(R12)을 통하여 흐르는 전류는 감소하게 되어 수직사이즈회로(2)의 수직사이즈도 감소하게 된다.In such a state, when the overlapping DC component is applied to the variable resistor VR 2 through the resistor R 10 and the diode D 1 , the voltage drop of the variable resistor VR 2 increases to increase the diode ( Since the cathode voltage of D 1 ) is increased, the current flowing through the resistor R 12 is decreased, so that the vertical size of the vertical size circuit 2 is also reduced.
여기서 콘덴서(C4)에 의하여 영상신호 입력단자(1)의 교류신호성분을 제거하게 된다.Here, the AC signal component of the video signal input terminal 1 is removed by the capacitor C 4 .
이렇게 하여 휘도가 밝아져 고압이 하강되고 편향력감소로 수직사이즈 증가 분만큼 자동적으로 수직 사이즈를 감소시키게 되는 것이다.In this way, the brightness is brightened, the high pressure is lowered, and the vertical size is automatically reduced by the vertical size increase due to the decrease in the deflection force.
한편, 가변저항(VR1)의 가변단자를 저항(R3)에 가깝게 하면 트랜지스터(Q1)의 베이스,에미터 전압이 감소하여 영상신호 입력단자(1)에 중첩되는 직류성분이 감소되어서 저항(R11), (R9)을 통하여 캐스코드 증폭기의 증폭도가 적어져 휘도는 어둡게 되고, 비임 전류가 감소하게 된다.On the other hand, when the variable terminal of the variable resistor VR 1 is close to the resistor R 3 , the base and emitter voltages of the transistor Q 1 are decreased, so that the DC component overlapping the image signal input terminal 1 is reduced, thereby reducing the resistance. Through R 11 and R 9 , the amplification degree of the cascode amplifier decreases, so that the luminance becomes dark and the beam current decreases.
따라서, 저항(R11)과 저항(R9)의 접속점(a)에서 저항(R10) 및 다이오드(D1)를 통하여 흐르는 전류도 감소되어 가변저항(VR2)의 추가 전압강하가 없으므로 수직 사이즈 회로(2)에서 저항(R12)을 통하여 흐르는 전류가 증가하게 되는 것이어서 수직 사이즈가 증가하게 되는 것이다.Accordingly, the current flowing through the resistor R 10 and the diode D 1 at the connection point a between the resistor R 11 and the resistor R 9 is also reduced, so that there is no additional voltage drop of the variable resistor VR 2 . In the size circuit 2, the current flowing through the resistor R 12 is increased so that the vertical size is increased.
이와 같이 하여 저항(R10)의 값을 가변함으로서 휘도 가변저항(VR1)의 조정에 의한 영상신호 입력단자(1)에 중첩되는 직류 전압의 궤환량을 조정하여 수직 사이즈를 일정하게 유지시키게 되는 것이다.By varying the value of the resistor R 10 in this way, the feedback amount of the DC voltage superimposed on the video signal input terminal 1 by adjusting the luminance variable resistor VR 1 is adjusted to maintain the vertical size constant. will be.
이상에서와 같이 동작되는 본 고안의 캐스코드 영상 출력회로의 영상신호의 하이 되는 부분을 수직사이즈 가변회로에 궤환 시킴으로서 수직 사이즈가 안정되게 유지하여 선명한 화면을 제공할 수가 있는 것이다.By returning a portion of the video signal of the cascode video output circuit of the present invention operated as described above to the vertical size variable circuit, the vertical size can be kept stable and a clear screen can be provided.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850017500U KR900009586Y1 (en) | 1985-12-24 | 1985-12-24 | Circuit for controlling dimensious and shape |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850017500U KR900009586Y1 (en) | 1985-12-24 | 1985-12-24 | Circuit for controlling dimensious and shape |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870011533U KR870011533U (en) | 1987-07-18 |
| KR900009586Y1 true KR900009586Y1 (en) | 1990-10-15 |
Family
ID=19247485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019850017500U KR900009586Y1 (en) | 1985-12-24 | 1985-12-24 | Circuit for controlling dimensious and shape |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR900009586Y1 (en) |
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1985
- 1985-12-24 KR KR2019850017500U patent/KR900009586Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR870011533U (en) | 1987-07-18 |
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