KR900008816B1 - Up/down and right/left moving circuit at image apparatus - Google Patents

Abstract

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Description

Up / Down / Left / Right Circuit in Imaging Device

1 is a circuit diagram according to the present invention.

2 is a view illustrating an embodiment of moving the screen left and right and up and down according to the present invention.

3 and 4 are operating waveform diagrams according to the present invention.

* Explanation of symbols for main parts of the drawings

1: central processing unit 2: CRT controller

3: decoder 4, 6, 10, 17: latch 1-4

5, 11: 1st, 2 adder 7, 18: 1st, 2 counter

8: multiplexer 9: DRAM

12: Romans 13: Ram

14: shift register 15: video control logic

16: monitor 20: clock generator

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an image control apparatus in a personal computer, a terminal, and a workstation for computer add design (CAD). In particular, the movement of a text screen is smooth in dots. The present invention relates to a vertical / left / right moving circuit in an image device capable of moving up and down or panning.

When using text mode in the conventional Color Graphic Adapter, the video memory address and raster address signal generated by the CRTC (Cathode Ray Tube Controller) are generated based on the character generation. It has been impossible to move left and right.

Accordingly, an object of the present invention is to generate an image with a new memory and raster address generation by the memory address and raster address generated by the CRTC and the data specified by the central processing unit, and to display the image while moving left / right in a dot unit. To provide the circuitry.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, which is processed by a program according to a mode to output a left / right / up / down shift setting value of an image and outputs data to generate a new memory and a raster address, and Receives and decodes the CRT controller 2 which receives the data of the central processing unit 1 and generates the memory and raster address signals, and generates the vertical and horizontal synchronization signals and the display timing signal. And output data of the central processing unit 1 according to the decoder 3 generating the chip selector and the latch clock signal ad of the CRT controller 2 and the output latch clock a of the decoder 3. A first adder 5 for adding a latching first latch 4, an output of the first latch 4, and an output of a lower address c of the CRT controller 2 to generate a new memory address signal; Exiting the Decoder 3 A second latch 6 latching an output of the CRT controller 2 and an upper address E according to a latch clock C, and a first counter 7 counting an address of the second latch 6. And a DRAM 9 storing an image code value to be displayed from the central processing unit 1, and a row and a column when the central processing unit 1 accesses the DRAM 9; ) And the output D of the first adder 5 and the output F of the second latch 6 or the output D of the first adder 5 when the CRT controller 2 is accessed. And a third multiplexer 8 for selecting the output of the first counter 7, and a third buffer for buffering the data of the CPU 1 with an address signal by the latch clock d of the decoder 3. A second adder 11 for generating a new raster address signal by adding the latch 10, the address output of the third latch 10, and the raster address of the CRT controller 2; The ROM 12 having the image of the character code possessed by (9) and receiving the raster address signal of the second adder 11 to generate the image, and has the same operation as the ROM 12. RAM 13 containing a defined image of central processing unit 1, a clock generator 20 for supplying a clock to the CRT controller 2, and a latch clock of the decoder 3 When the fourth latch 17 receives and buffers the output data of the central processing unit 1 and the output data of the fourth latch 17 is initially decremented to become zero (0). A second counter 18 for adjusting the display timing by delaying the display timing signal up to and receiving the vertical and horizontal synchronization signals Vsync and Hsync and the display timing signal Disp from the CRT controller 2. Even if you display the adjusted image adjusted to the timing by adjusting (18). According to the video control logic unit 15 which regenerates the new horizontal and vertical synchronization signals V-sync and H-sync and the display timing signal, and the output display typing control signal Disp of the video control logic unit 15. A shift register 14 for outputting parallel inputs in series by shifting the generated image of the ROM 12 and the RAM 13 by one bit per dot clock, and a video image signal and video control of the shift register 14 It consists of a monitor 16 which can be moved left and right and up and down in accordance with the vertical and horizontal synchronizing signals V-sync and H-sync of the logic unit 15.

FIG. 2 is an example of a screen left / right and up / down movement according to the present invention. FIG. 2a is an example of display when it is not left / right and up / down movement, and FIG.

3 is an operation waveform diagram according to the present invention, and FIG. 3a is an operation waveform diagram when it is not left / right moved up and down, and FIG. 3b is an example of the character display according to FIG. 3a.

4 is an operation waveform diagram according to the present invention. FIG. 4A is an operation waveform diagram when the left / right and up / down movements are performed. FIG. 4B is an example of the character display according to FIG. 4A.

(3a), (3e) of FIG. 3a, (4c), (4j) of FIG. 4a of the waveforms of FIG. 3, 4 are the character clocks, (3b), (3d) of FIG. Is a display timing signal, (3c), (3f) in FIG. 3a, (4f) and (4m) in FIG. 4a are memory address signals, (3d), (3g) and (4h) in FIG. 3a. , (4i) and (4l) are raster address signals.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 1-4, in which the address signal generated by the central processing unit 1 is decoded by the decoder 3 in the case of FIG. To set the third and fourth latches 10 and 17 to zero, and the data signal of the central processing unit 1 is input to the CRT controller 2 so as to correspond to the character clock of waveform (3a) of the clock generator 20. The display timing signal of (3b) is generated via the line 8, and is input to the first adder 5 through the address bus C to generate an upper 8-bit memory address signal such as (3c, 3f). Then, the raster address signal is generated via the address bus I of the CRT controller 2 as shown in (3d). When the lower 8-bit memory address signal of the CRT controller 2 is output through the address bus E and input to the second latch 6 as shown in (3h) according to the character clock of (3e), the decoder 3 It is latched according to the latch clock C.

The output (D) of the first adder (5) and the output (F) of the second latch (6) in the multiplexer (8) in accordance with the address signal of the central processing unit (Row) and the column (Columm) If the user selects and inputs to the DRAM 9 and designates an address, the image code stored in the DRAM 9 is accessed and the ROM 12 is input to the ROM 12 so that the raster address generated by the CRT controller 2 is added to the second adder 11. When the raster address of the ROM 12 is designated through the corresponding image is generated and the image set by the central processing unit 1 by the RAM 13 is input to the shift register 14 in parallel, the CRT controller 2 The generated vertical and horizontal synchronization signals Vsync and Hsync and the display timing signal Disp are regenerated by the video control logic unit 15, and the display timing signals regenerated by the video control logic unit 15 by the shift register 14. Disp) is input and outputs in series by shifting 1 bit for each clock. The vertical and horizontal synchronizing signals (H-sync and V-sync) input to the monitor 16 and regenerated are also input to the monitor 16 to display a character "A" as shown in 3B.

However, as shown in FIG. 2B, in order to move by u bits in the X axis and v bits in the Y axis, the decoder 3 decodes the address generated by the central processing unit 1 and performs the first to fourth latches 4 and 6. Latch clocks (a, c, d, l) of < RTI ID = 0.0 > 10, < / RTI > 17 and the chip selector signal b of the CRT controller 2 so that the CRT controller 2 is a chip selector and the output of the central processing unit 1 When the data signal is input to the CRT controller 2 and the second to fourth latches 4, 10, and 17, the CRT controller 2 displays the display timing signal 4d according to the generated clock signal 4c of the clock generator 20. And vertical and horizontal synchronization signals Hsync and Vsync and a memory address signal 4f.

The second latch 4 receives the horizontal offset address from the central processing unit 1 and the lower address 8 bits 4f and the first latch 4 generated by the CRT controller 2 in the first adder 4. Is added to the first adder 5 to generate new address signals 4g and 4k. The second latch 6 latches the upper 8 bits of the memory address of the CRT controller 2 along the vertical axis Y by the latch clock C of the decoder 3.

Then, the third and fourth latches 10 and 17 are latched so as to move (u, v) left and right and up and down in a dot unit according to the latch clocks d and l of the decoder 3.

Therefore, when the value latched by the second latch 6 is incremented by the first counter 7 and sent to the multiplexer 8, the central processing unit 1 accesses the DRAM 9 in the multiplexer 8. To do this, select the address by row and column to output.

That is, as shown in FIG. 2B, the X and Y axes are designated in byte units.

When the display code generated by the DRAM 9 is input to the ROM 12 or the RAM 13, the value v latched in the third latch 10 and the raster address generated by the CRT controller 2 are removed. In addition to the adder 11, a new raster address signal is generated as shown in (4a) and (4l) and input to the address of the ROM 12.

When the image is generated in the ROM 12 and the RAM 13 by the raster address signal generated by the output of the second adder 11 and input to the shift register 14, the latch is latched by the fourth latch 17. The display timing signal 4d of the CRT controller 2 is set to the latch value u of the fourth latch 17 as shown by (4e) from the beginning until the second counter 18 decrements the value to zero. Delay by) and input to the shift register 14 to shift the image data in series by 1 bit for every dot clock. When the signal is input to the monitor 16, the video control logic unit 15 receives the vertical and horizontal synchronization signals Vsync and Hsync of the CRT controller 2, and the vertical and horizontal synchronization signals V-sync and H-sync. ) Is regenerated and input to the monitor 16, as shown in FIG. 4B.

That is, the video control logic unit 15 delays the display timing signal 4d generated by the CRT controller 2 by u (dock clock + u) and does not display as much as the left u of the actual image. "E" will display u dots.

At this time, if 0 u 7 and u is equal to or greater than 8, the value of the first latch 4 is increased by one.

The raster address generated by the CRT controller 2 is added to the content v of the third latch 10, and the image that is behind the actual image in the ROM 12 and the RAM 13 is selected as much as the line behind the shift register 14. ) In this case, since the contents of the first and second latches 4 and 6 are X and Y bytes, the actual address of the video memory indicates the position of C + X and E + Y, and thus the second from "A, B, C, D". As shown in the diagram, it is moved to the position "A, B, C, D".

Therefore, the address of the position currently read from the video memory is X + C, Y + E, and the character code of this position outputs the image of the ROM 12, but the display timing (g) is displayed on the video control logic section 15. Since it is shifted by the timing (h) signal, it is shifted bit by bit and the dot image is output to the monitor 16.

As described above, since the conventional CRT controller chip can be used to move the screen left / right in a bit unit, there is an advantage that a high function can be exhibited in real time on the screen.

Claims (1)

A video display device comprising: a central processing unit (1) for processing a program according to a mode to output left and right shift values of an image, and outputting data to generate a new memory and a raster address; A CRT controller 2 which receives the data of 1) and generates a memory and a raster address signal, and generates vertical and horizontal synchronization signals and a display timing signal, and receives and decodes the address signal of the central processing unit 1 to the CRT controller. A first latch for latching the output data of the central processing unit 1 in accordance with the decoder 3 generating the chip selector and latch clock signal a of (2) and the output latch clock a of the decoder 3. (4), a first adder (5) for generating a new memory address signal by adding the output of the first latch (4) and the lower address (c) output of the CRT controller (2), and the decoder (3). Output of A second latch 6 for latching the output of the upper address E of the CRT controller 2 according to the latch clock C, and a first counter 7 counting the address of the second latch 6. And a DRAM 9 storing an image code value to be displayed from the CPU 1, a row and a column when the CPU 9 accesses the DRAM 9, and selecting the CRT. When the controller 2 accesses the output D of the first adder 5 and the output F of the second latch 6 or the output D of the first adder 5 and the first counter 7. A multiplexer 8 for selecting an output of the < RTI ID = 0.0 >) < / RTI > and a third latch 10 for buffering the data of the CPU 1 with an address signal by a latch clock d of the decoder 3, The DRAM 9 has a second adder 11 for generating a new raster address signal by adding the address output of the third latch 10 and the raster address of the CRT controller 2. The central processing unit (1) by operating the same operation as the ROM (12) and the ROM (12) generating a corresponding image by receiving the raster address signal of the second adder (11). RAM (13) containing an image defined by < RTI ID = 0.0 >), < / RTI > a clock generator 20 for supplying a clock to the CRT controller 2, and a latch clock 1 of the decoder 3. 4th latch 17 which receives and buffers the output data of 1), and the output timing of the fourth latch 17 is initially decremented to delay the display timing signal until it becomes zero (0). The second counter 18 to adjust the control unit, and receives the vertical and horizontal synchronization signals (Vsync, Hsync) and the display timing signal (Disp) from the CRT controller 2 to adjust the timing by adjusting the second counter (18). New horizontal to display adjusted adjusted images The ROM according to the video control logic unit 15 which regenerates the direct synchronization signals V-sync and H-sync and the display timing signal and the output display typing control signal Disp of the video control logic unit 15. 12 and a shift register 14 for outputting a parallel input in series by shifting the generated image of the RAM 13 by one bit per dot clock, and the video image signal and the video control logic of the shift register 14 ( The vertical / horizontal synchronization signal (V-sync, H-sync) in accordance with the vertical and horizontal / up / down movement circuit in the image device, characterized by comprising a monitor (16) which can be displayed.

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