KR900008069B1 - Data memory circuit using bit adressing method in programmable logic controller - Google Patents

Abstract

A data memory circuit using bit addressing method capable of applying the memory capacity effectively comprises memories (11-18) having a number of addresses for accessing 1-bit data corresponding to address from a program counter, a multiplexer (30) for detecting and transmitting the memory data read by address of the lowest bit to HLS or CPU, and a latch circuit (20) for transmitting outputs of memories to the multiplexer.

Description

Data memory circuit using bit addressing method in programmable logic controller

1 is a conventional circuit diagram.

2 is a memory map of FIG.

3 is a circuit diagram of the present invention.

4 is a memory map of FIG.

* Explanation of symbols for main parts of the drawings

11-18: memory 20: latch circuit

30: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data memory circuit in a programmable logic controller (hereinafter, referred to as a PLC), and more particularly, to a data memory circuit using a bit addressing scheme that can efficiently use memory storage capability.

In general, the PLC is composed of a system controller, a programmer, and a plurality of input / output modules. The system controller reads input data from input devices mounted in a process through the input / output module. admit.

The input devices used at this time use input relays, switches, proximity switches, sensors, and level switches. When the input operation of the input data from the input / output module is completed, the system controller was performed until the immediately preceding scanning period with the input data by the execution order of the ladder diagram inputted through the programmer. The new intermediate control data and output data are made using the data including the resultant control relay and output data. When the new output data is generated, the system controller outputs the newly generated data to the output device having the process through the input / output module and temporarily stores the data in the memory data for the next step calculation.

In the above description, the system controller consists of a central processing unit (CPU), a hardware logic solver (HLS), and an input output processor (IOP). As follows. The CPU inputs the input data of the input module inputted by the IOP from the IOP and stores it in the data memory embedded in the HLS.

At this time, the HLS processes the data stored in the data memory and stores the processed data in the data memory. The CPU then reads the processed data from the data memory of the HLS and outputs it to the input / output module through IOP.

The data memory embedded in the HLS is configured as shown in FIG. 1 to store data applied from the CPU or the HLS whenever an address is applied. As shown in the memory map shown in FIG. Stores one byte of data.

However, because the I / O device that is the data operand is a relay, a sensor, a proximity switch, and a level switch to which a low or high logic of the "1 or 0" concept is applied, it is displayed in only two states. As it can be represented as 1-bit data rather than 8-bit data that can display 256 states, there was a problem of waste of memory and inefficient use of memory.

Accordingly, an object of the present invention is to provide a data memory circuit using a bit addressing method in a PLC which can efficiently use the memory by accessing one bit of data each time an address is applied.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of the present invention, a plurality of memories 11-18 each having a plurality of different addresses for accessing one bit data at an address corresponding to an address applied from a program counter under the control of the CPU, and the address; A multiplexer 30 which detects data of the memory read out of the plurality of memories by an address of the lowest predetermined bit among the plurality of memories and transmits the data to the HLS or the CPU; and outputs the output of the plurality of memories under the control of the CPU. 4 is a memory map of FIG. 3. Accordingly, the present invention will be described in detail with reference to FIGS. 3 and 4.

First, the operation at the time of writing will be described. The plurality of memories 11-18 are enabled by the chip selector signals CS1-CS8 applied from the CPU and have a large number of addresses from the program counter in the enabled state. Is applied to the memory 11-18.

In this case, the memory including the address corresponding to the address stores 1-bit data supplied through the line 1 at the address. As described above, each memory 11-18 stores data according to an address at a address designated by an address as shown in FIG. 4 memory map. When the address is 0, the first memory 11 is stored in the first memory 11. Data is stored in the first memory of the second memory 12 when the address is one address, and data is stored in the first memory of the third memory 13 when the address is two addresses.

Secondly, when reading data stored in the memory, the chip selector signal CS3 of the arbitrary memory 13 in which the data to be read from the CPU is stored is applied to the arbitrary memory 13, and the chip selector signal CS3 is applied. The memory 13 for inputting the memory 13 is enabled by the chip selector signal and outputs data stored at a address corresponding to an address applied through the plurality of lines 2 to the latch circuit 20.

Then, the latch circuit 20 has zero or one data applied from the memory 13 by the latch signal applied from the CPU and zero data without the remaining data 11, 12, 14-18 in the disabled state. The state is parallel latched by the multiplexer 30.

At this time, the multiplexer 30 detects the data of the arbitrary memory 13 having a 0 or 1 state by the address of a predetermined bit applied through the predetermined number of lines 3, and the HLS or Transfer to the CPU.

As described above, the present invention has an advantage of preventing the waste of memory by efficiently using the memory.

Claims (1)

In the programmable logic controller, under the control of the CPU, a plurality of memories 11-18 each having a plurality of different addresses for accessing one bit data at an address corresponding to an address applied from a program counter, and the lowest of the addresses. A multiplexer 30 which detects data of the memory read out of the plurality of memories by a predetermined bit address and transmits the data to the HLS or the CPU, and transmits the outputs of the plurality of memories to the multiplexer 30 under CPU control. A data memory circuit using a bit addressing method, characterized in that it comprises a latch circuit (20).

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