KR900007065B1 - Direct control method of time switch attached with automatic gain control - Google Patents

Abstract

The circuit for controlling the voice and gain memories with one controller in a digital telephone exchange comprises a CPU (200) processing the PCM coded serial voice data, a counter (200) counting the sequence of time slot incrementally, a voice control memory (20) writing and reading the voice and gain control data to and from the selected address, a latch circuit (30) providing the delayed gain control data to a gain memory (2), and a first (6) and second (8) multiplexers providing the switching address of the CPU to the memory (20) as a writing address and the voice control data to a voice memory (3) as reading address.

Description

Direct control method of time switch with automatic gain control

1 is a mu-Law PCM compand curve.

2 is a circuit diagram of a time switch to which a conventional automatic gain adjusting device is added.

3 is a circuit diagram of a time switch to which an automatic gain adjusting device according to the present invention is added.

4 is a data structure diagram of the gain adjustment memory of FIG.

5 is a flow chart of FIG.

* Explanation of symbols for main parts of the drawings

1: Serial / parallel converter 2: Gain memory

3: voice memory 4: bottle / serial converter

6, 8: multiplexer 20: voice control memory

30: latch circuit

The present invention relates to a gain control circuit of a time switch to which an automatic gain adjusting device is added, and more particularly to a circuit for directly controlling the gain of a PCM audio signal of a time switch to which an automatic gain adjusting device is added.

In general, the time switch, which is a digital exchange part, causes a lot of network loss depending on the characteristics of the line, or the waveform is distorted due to overflow due to excessive level. Attenuation or amplification will occur.

Therefore, in order to solve the above problems, the automatic gain control device (Automatic Gain Contro1) has been built in the time switch (Time Switch) to automatically adjust the gain of the PCM voice signal.

In addition, the PCM audio signal is formed by applying a time-division multiplexed pulse amplitude modulation (Pulse Amplitude Modu1ation) pulse sequence, such as a companding curve of a mu-Low PCM as shown in FIG. It is sent to Law PCM Coder and converted to 8-bit binary code by the coder through the sampling and holding circuit, so that analog data is converted into upper 128, lower 128, and 256 levels of digital data. Voice data converted to

2 is a circuit diagram of a time switch in which a conventional automatic gain adjusting device is highlighted. A serial / parallel converter 1 which converts and outputs PCM serial voice data into parallel data from a subscriber circuit (not shown), and converts in parallel. A gain memory 2 for inputting the output audio data and the gain control data to adjust the gains of the converted voice data by loss of a line or the like and outputting the gain data by a predetermined control signal; A voice memory (3) for recording the voice data and outputting voice data switched by a predetermined control signal by performing time switching operation by input of voice control data, and voice data output from the voice memory (3). And serial converter 4 for converting and outputting the data into serial data, and gain control data, the voice control data, and a predetermined address signal. And a central processing unit (not shown) for generating a control signal, and a sequential stored in the voice control data output from the central processing unit by a predetermined address signal and output from a counter (not shown). When the data is written to the voice control memory 5 and the voice control memory 5 which outputs them by the address signal, the address designated by the central processing unit can be selected and output and the stored data can be read. The multiplexer 6 selects and outputs an address output from the counter, a latch circuit 7 for accurately providing the read data of the voice control memory 5 to the voice memory 3, and the gain memory 2. When writing the output PCM voice data, select the counter data and output it as an address signal, and read the recorded PCM voice data. Multiplex 8 for selecting and outputting the signal as an address signal of voice memory 3, and gain control memory 9 for storing the gain control data by inputting an address output from a counter and a central processing unit (not shown). And a multiplexer 10 for selectively outputting an address output from the central processing unit when data is written to the gain adjusting memory 9, and latching the data of the gain adjusting memory 9 to the gain memory 2; It consists of a latch circuit 11.

The gain control data in FIG. 2 is generated from the central processing unit to adjust the gain of the voice data output from the serial / parallel converter 1, and the level of amplification and attenuation is divided into eight groups. By specifying one of the groups of the gain memory 2 in which the PCM data is stored in advance, the data whose gain is adjusted in correspondence with the input voice data is output to the voice memory 3. Further, the voice control data is time switching data for switching and outputting the gain-adjusted voice data stored in the voice memory 3 by the sequential address.

Now, when voice data is PCM coded in the circuit configured as described above and input to the serial / parallel converter 1, the serial / parallel converter 1 amplifies / attenuates the input PCM voice data. The PCM data is output to the address terminal ADDR of the gain memory 2 in which the PCM data is stored. The gain memory 2 if PCM data sewn to distinguish the level of amplification, attenuation in total of eight groups are stored, gain control memory 9 requires only three bits two groups of ^three, that is, eight groups PCM Data can be distinguished. Since the gain control memory 9 operates like the voice control memory 5 of switching, a group to be selected must be selected for each time slot.

In addition, this memory requires the memory capacity of the required number of bits according to the number of groups to be selected for the number of timeslots, which is the capacity of the time switch. Since the capacity of the gain memory 2 is 256 in mu-Law PCM, if the number of groups is 8

Memory capacity m = 256 x 8byte

Becomes

A central processing unit (hereinafter referred to as CPU), which is not shown, checks the output level of the subscriber circuit and outputs the gain control data corresponding to the level, the predetermined address signal and the write control signal to the address bus 200 and the data bus ( 300 and output to the gain control memory 9 and the multiplexer 10 through the control bus 400, respectively.

The multiplexer 10 which inputs the address output from the CPU selects it according to a predetermined selection signal and outputs it as an address signal of the gain control memory 9, which causes the gain control memory 9 to output the PCM to the subscriber. Gain control data output from the CPU is stored corresponding to the voice data level.

The CPU, which has written gain control data into the gain control memory 9, outputs a read control signal to the control bus 400, if necessary, by reading data written in the gain control memory 9, When the sequential address is output from the counter (not shown) to the counter bus 100, the multiplexer 8, 10 receives the sequential address inputted to the counter bus 100, and the address of the gain control memory 9 and the voice data 3. Will be printed respectively.

Therefore, the gain control memory 9 outputs the gain control data input from the CPU to the latch circuit 11, and the latch circuit 11 latches the gain control data by the control signal input from the control bus 400. Output is performed by the address signal of the gain memory 2.

Therefore, the gain memory 2 adjusts the gain of the PCM voice data to a predetermined value by the gain control data input which outputs the PCM data stored at various levels of amplification and attenuation from the latch circuit 11, and from the control bus 400. PCM audio data gain-adjusted by the output read control signal is output to the voice memory 3. That is, the gain memory 2 outputs the stored PCM data using the voice control data and the PCM voice data as addresses, and the stored PCM data group divided into several levels of amplification and attenuation are designated by the voice control data. The gain-controlled PCM data corresponding to the input PCM voice data is output from the PCM data of the designated group.

The multiplexer 8 inputs the sequential address counted and output from the counter via the counter bus 100, selects the predetermined address by a predetermined selection signal, and outputs the same to the voice memory 3. Therefore, the voice memory 3 inputs and stores PCM voice data output by adjusting the gain in the gain memory 2 using the output of the multiplexer 8 as an address signal. At this time, the CPU outputs the unique address, the voice control data, and the write control signal of the counterpart to the voice control memory 5 and the multiplexer 6 through the address, the data, and the control buses 200-400, respectively. The multiplexer 6 selects an address signal output from the CPU by a predetermined selection signal and outputs it to the voice control memory 5.

On the other hand, the voice control memory 5 stores voice control data in a predetermined memory area by the output address of the multiplexer 6 in response to the address signal of the CPU, and the voice memory 3 in which PCM voice data is input is controlled. The write control signal inputted to the bus 400 is stored in the designated address of the sequential address output from the multiplexer 8. After the above operation is performed, the multiplexer 6 selects the sequential address (counting data) input to the counterbus 100 according to a predetermined selection signal and outputs it as an address signal. Then, the CPU reads the voice control memory 5. The control signal is output through the control bus 400.

Therefore, the voice control memory 5 outputs the voice control data to the latch circuit 7 which adjusts the time by the sequential address of the counter and the read control signal of the CPU, and the latch circuit 7 controls the control bus ( The voice control data, that is, the exchange connection data, is latched and outputted to the multiplexer 8 according to the read control signal inputted to 400. At this time, the voice control data input through the latch circuit 7 and the counterbus 100 and the multiplexer 8 inputting the sequential address receive the voice control data output from the latch circuit 7 by a predetermined selection signal. Output to the address of the memory (3).

Therefore, time switching is performed by inputting the address of the voice control data to output the voice data to the parallel / serial converter 4.

The parallel / serial converter 4 which inputs the switched PCM voice data in the voice memory 3 converts it into serial PCM data and outputs it through the subhighway.

Therefore, the PCM voice data transmitted from the subscriber circuit and attenuated or amplified by the loss of the line or the like is adjusted, switched and output with an appropriate gain.

However, the circuit operated as described above has to have a control circuit for controlling the gain memory 2 in which the gain-specific data is stored at all times, thereby complicating the circuit and increasing the cost.

In addition, by separating and controlling the control of the software controlling the gain control memory 9 and the voice control memory 5, when the load of the software is increased and the traffic is increased a lot, it is difficult to operate the system. Many.

Accordingly, an object of the present invention is to provide a circuit for directly controlling a gain memory by extending bits of the voice memory adjusting memory without requiring a control circuit of a gain memory storing gain-specific data.

It is still another object of the present invention to provide a gain control circuit of an automatic gain control device of a time switch that can increase the system efficiency while reducing the load of the software of the time switch.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a time switch to which an automatic gain adjusting device according to the present invention is added, and a serial / parallel converter 1 for converting and outputting PCM serial voice data output from the subscriber circuit 100 into parallel data; A gain memory (2) for inputting the voice data and the gain control data converted and outputted in parallel to adjust the gain of the voice data converted by loss of a line or the like to a level by the gain control data and outputting the result by a predetermined control signal (2) And a voice memory (3) for outputting the voice data switched by a predetermined control signal by performing time switching operation on the adjusted voice data by input of the voice control data, and outputting from the voice memory (3). A parallel / serial converter 4 for converting and outputting the converted voice data into serial data and checking the level of the PCM coded serial voice data of the subscriber circuit 100; The CPU 200 for outputting the gain control data for controlling the gain of the serial voice data and the voice control data for switching the voice data to the data terminal, and outputting a switching address and a control signal, and increasing the order of the time slots. A counter 300 for outputting a sequential address, voice control data and gain control data output from the CPU 200 are stored by a write address input, and the stored voice control data and gain control data are read by a read address. When writing data to the voice control memory 20 to read out and the voice control memory 20, the switching address outputted from the CPU 200 is selectively outputted, and the stored data is read out. In this case, the first multiplexer 6 which selects and outputs a sequential address output from the counter 300 and the voice of the voice control memory 20 are used. When writing the latch circuit 30 and the PCM audio data output from the gain memory 2 for accurately providing the delay data and the gain control data to the gain memory 2 and the voice memory 3, respectively. Selects the sequential address of the counter 300 and outputs it as a write address signal of the voice memory 3, and selects the voice control data output from the latch circuit 30 when reading the recorded PCM voice data. The second multiplexer 8 outputs the read address signal (3).

4 is a diagram showing the bit configuration of the voice control memory 20 of FIG. 3, wherein the upper 3 bits (GCB) are the gain control bits of the gain memory 2, and the remaining bits (SCB) are the voice control bits. to be.

FIG. 5 is a flow chart of FIG. 3 operated according to the present scheme. FIG. 5 is a first process 11 for checking the input level of PCM data input from the subscriber circuit when the call Cal1, and the input level check of the first process. A second process 12 for selecting and outputting an automatic gain control group data for outputting gain data, a third process l3 for outputting switching data and making a switched connection, and a call state ( The fourth step 14 of determining whether or not the service (Service) is determined by determining whether or not the Call State (end).

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 3 to 5, when PCM voice data is output from the subscriber circuit 100 and input to the serial / parallel converter 1, the serial / parallel converter 1 ) Converts the serial PCM audio data in parallel and outputs them as address signals of the gain memory 2.

At this time, the CPU 200 inputs the PCM voice data output from the subscriber circuit 100 to check the input level of the PCM voice data in FIG. The corresponding AGC group data is selected, and in the third step 13, the gain control data and the voice control data for time switching with the other party are output to the voice control memory 20 through the data bus 1300, and at the same time, the switching address. And a write control signal are output through the buses 1200 and 1400, respectively.

Meanwhile, the first multiplexer 6 that inputs the incremental address (sequential address) of the counter 300 input through the counter bus 1100 and the switching address of the CPU 200 input through the address bus 1200 are predetermined. The output switching address of the CPU 200 is output to the write address of the voice control memory 20 by inputting a control signal (selection signal) of the voice control memory 20. As a result, the voice control memory 20 is input through the control bus 1400. The voice adjustment data and the gain adjustment data are written by the write control signal.

After performing the operation as described above, the CPU 200 outputs the read control signal to the voice control memory 20 through the control bus 1400, in which the first multiplexer 6 is input from the counter bus 1100. The sequential address is selected and output to the read address of the voice control memory 20.

Therefore, the voice control memory 20 reads the gain control upper 3 bits data GCB and the voice control data SCB, which are configured as shown in FIG. 4, and outputs them to the latch circuit 30, and the latch circuit 30 controls the voice control. The gain control data and the voice control data output from the memory 20 are latched by a read control signal output from the control bus l400 to convert the gain control data, which is the upper 3 bits, into the address of the gain memory 2. Output the voice control data to the second multiplexer (8).

Therefore, the gain memory 2 inputs parallel PCM audio data output from the serial / parallel converter 1 as a data signal, gain control data output from the latch circuit 30 as an address signal, and receives a control bus 1400. The PCM audio data whose gain is adjusted by the output read control signal is read out and output to the voice memory 3.

In addition, the second multiplexer 8, which inputs the voice control data output from the latch circuit 30 and the counting data (sequential address) through the counter bus 1100, selects the sequential address by a predetermined selection signal, and selects the voice memory. By outputting to the write address at (3), the voice memory 3 writes it by a predetermined control signal output from the control bus 1400.

On the other hand, the CPU 200 outputs a write control signal for writing gain control data and voice control data to the voice control memory 20, and the second multiplexer 8 outputs the voice control latched by the latch circuit 30. The data is selected by predetermined control and output to the read address of the audio memory 3.

At this time, when the read control signal is output through the control bus 1400, the voice memory 3 outputs the PCM data according to the read address to the parallel / serial converter 4.

The parallel / serial converter 4 which inputs the voice PCM data exchanged and connected in the voice memory 3 converts it into serial data and outputs it.

Therefore, if the CPU 200 controls the upper 3 bits as gain control data and the lower bits as voice control data by extending the number of bits of the voice control memory, the amplification and attenuation are divided into eight groups as described in FIG. It can be seen that the control of the gain memory 2 in which gain-specific data is stored at various levels is controlled without providing a separate control circuit.

On the other hand, if the voice data whose gain is adjusted in the gain memory 2 is switched in the voice memory 3 as described above, does the CPU 200 terminate the call state as in the fourth process 14? If it keeps calling state by judging, it maintains switching state and returns at the end of call.

As described above, the present invention adjusts the voice memory and the gain memory as one control circuit to control the gain memory without requiring a separate control circuit, thereby reducing the cost increase due to the increase in the number of labors and at the same time reducing the load of the software. As a result, there is a huge advantage in improving system efficiency.

Claims (1)

A serial / parallel converter 1 for converting and outputting PCM-coded serial voice data from the subscriber circuit 100 into parallel data, and inputting the voice data converted into the parallel data and outputting the gain level of the input voice data. A gain memory 2 that adjusts and outputs the gain level at a gain level by gain control data input, and the sound data output by the gain adjustment is recorded by a sequential address, and an audio signal is input by the address input of the voice control data which is time switching data. A gain control circuit of a time switch having an automatic gain control device having a voice memory (3) for switching and outputting the signal, wherein the serial circuit is connected to the subscriber circuit (100) to retrieve the level of the PCM-coded serial voice data. Gain control data for controlling gain of voice data and voice control data for switching voice data are used as data terminals. A central processing unit (200) for outputting a switching address, a counter (300) for outputting a sequential address to the voice memory (3) by incrementing the order of time slots, and the central processing unit (200). A voice control memory connected to a data terminal of < RTI ID = 0.0 > and < / RTI > storing the output voice control data and gain control data in an internal area by a write address input and reading the stored voice control data and gain control data by a read address ( 20) and the voice control data and the gain control data, which are connected to an output terminal of the voice control memory 20, are delayed to provide the gain control data to the address of the gain memory 2, and provide the voice control data. The latch circuit 30 outputting to the output terminal and the sequential address output of the counter 300 are commonly input to one input terminal, and another As the input terminal, the switching address of the central processing unit 200 and the voice control data of the latch circuit 30 are input, respectively, and the sequential address of the counter 300 is read out of the voice control memory 20 and the voice. Providing to the write address of the memory 3, providing the switching address to the write address of the voice control memory 20 according to the transition of the selection signal, and providing the voice control data to the read address of the voice memory 3 A gain control circuit of a time switch with an automatic gain adjusting device, characterized in that it comprises a first and a second multiplexer (6) (8).

Images