KR900006974B1 - Method of expanding the number of cpu interfaces - Google Patents

Abstract

If the I/O port region of the personal computer is allocated, it can be devided to 4 communication ports. The user's port is selected by combination of output command data of address taps (A0-9) and communication selection switches (SW1-3). The address taps (A0-2) provides interrupt enable register of UART for logical signal to allocate the corresponding communication port.

Description

Communication port expansion circuit

1 is a circuit diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

SW1-SW3: 1-3 Communication selector switch N1-N3: Inverter

NAl: NANDGATE μ-com: Microcomputers

10: Personal computer parallel bus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to port expansion circuits for data communication between a personal computer and a personal computer and peripheral devices. In particular, the present invention relates to a communication using a personal computer by extending a conventional fixed port by using a simple circuit. It is about communication port expansion circuit which can widen choice of port

In general, a COM port in a personal computer (hereinafter, referred to as a "PC") is an individual port through which a PC can exchange information with other peripheral devices and communication equipment. In the case of a conventional dial-up modem, it is designed to use only port 1 or port 2 when communicating with a PC. However, if the modem occupies port and the peripheral device other than the modem occupies port 1,2, the modem will not communicate. As described above, there is a problem in that one of the desired functions has to be abandoned because the selection range of the communication port is narrow.

Accordingly, it is an object of the present invention to provide a circuit that can expand the available ports to widen the selection of communication ports used in communication between a PC and a modem.

Another object of the present invention is to provide a circuit that can increase the utilization of other peripherals by expanding the port. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

을 통해 인에이블 신호를 발생하도록 연결하며, DO-Dn에 마이크로 컴퓨터(μ-com)의 데이타 버스(D0-Dn)가 연결되고, B24-B25는 인터럽트 요구(Interrupt Reguest) 단(IRQ3, IRQ4)이 연결되고, 상기 A27를 통해 발생된 어드레스단 (A4)을 인버터(N3)에 입력하고, 상기 인버터(N3)로부터 제3커뮤니케이션 선택 스위치(SV氾)의 3,4접점만에 연결하고, 상기 어드레스 단(A4)의 반전하지 않은 신호단을 상기 제3커뮤니케이션 스위치(SW3)의 2.4접점단에 연결하고, 상기 어드레스 인에이블단

을 인버터(N2)에 연결하고, 상기 A23를 통해 발생된 어드레스 만(A8)을 제2커뮤니케이션 선택 스위치(SW2)의 1.3접점단에 연결하며, 상기 어드레스단(A8)의 신호단을 인버터(Nl)를 통해 상기 제2커뮤니케이션 선택스위치(SW2)의 2.4접점단에 연결하고,상기 제2,3커뮤니케이션 선택스위치(SW2, SW3)의 출력단과 인버터(N2) 및 어드레스단(A3, A5-A7,A9)을낸드게이트(NAl)의 입력단에 연결하여 상기 낸드 게이트(NAl)의 출력만을 모뎀측 마이크로 컴퓨터(μ-com)의 칩실렉타단

에 연결하고, 상기 어드레스단(A0-A2)기 상기 마이크로 컴퓨터(μ-com)의 어드레스만(A0-A2)의 출력에 의해 논리적으로 2³(=8)의 순차 신호를 받도록 연결하며, 상기 마이크로 컴퓨터(μ-com)의 인터럽트단(INT)에 제1커뮤니케이션 선택 스위치(SW)를 연결한다.FIG. 1 is a circuit diagram according to the present invention, in which a personal computer (not shown), i.e., A22-A31 of the bus lines A11, A22-A31, B24-B25, and D0-Dn of the parallel bus line 10 is shown. An address signal is generated to the address terminals A0-A9 of the personal computer, and an address enable signal terminal is connected to the Al1.

The enable signal is connected via D-Dn, and the microcomputer (μ-com) data bus (D0-Dn) is connected to DO-Dn, and B24-B25 is interrupt interrupt (IRQ3, IRQ4). Is connected, the address terminal A4 generated through the A27 is input to the inverter N3, and is connected to only 3 or 4 contacts of the third communication selection switch SV 'from the inverter N3, The non-inverted signal terminal of the address terminal A4 is connected to the 2.4 contact terminal of the third communication switch SW3, and the address enable terminal

Is connected to the inverter N2, only the address A8 generated through the A23 is connected to the 1.3 contact terminal of the second communication selection switch SW2, and the signal terminal of the address terminal A8 is connected to the inverter Nl. Is connected to the 2.4 contact terminal of the second communication selection switch (SW2), and the output terminal of the second and third communication selection switches (SW2, SW3) and the inverter (N2) and address terminals (A3, A5-A7, A9) is connected to the input terminal of the NAND gate NAl, and only the output of the NAND gate NAl is the chip selector end of the modem side microcomputer (μ-com).

The address terminal A0-A2 is connected to receive a sequential signal of 2 ³ (= 8) logically by the output of only the address A0-A2 of the microcomputer (μ-com), The first communication selection switch SW is connected to the interrupt terminal INT of the microcomputer μ-com.

The first and second communication selection switches SW1 and SW2 are configured to interoperate with each other, and the third communication selection switch SW3 is also involved in port selection like the SW1 and SW2.

The 1-3 communication selection switch SW1-SW3 may be selected by a user's operation, and any type of switch such as a dip switch may be used.

의 신호를 인버터(N2)에서 반전하여 낸드게이트(NAl)에서 상기 신호와 논리화에 의해 모뎀측 마이크로컴퓨터(μ-com)의 칩실렉터단

를 제어하는데 필요한 신호를 발생하고, 상기 어드레스단(A2-A0)은 모뎀측 마이크로 컴퓨터(μ-com)의 내부 UART레지스터중 인터럽트 인에이블 레지스터(IER:Interrupt Enable Register)를 선택하는데 관여한다.That is, the address signal of the address terminal A4 is transmitted through the inverter N3 or directly through the third communication selection switch SW3 and the address of the address terminals A3 and A5-A9 and the address through the Al1. Able signal stage

Chip selector stage of the modem-side microcomputer (μ-com) by inverting the signal at the inverter N2 and logicalizing the signal at the NAND gate NAl.

Generates the signals necessary to control the signal, and the address stages A2-A0 are involved in selecting an interrupt enable register (IER) in the internal UART register of the modem-side microcomputer (μ-com).

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIG. 1. In the case where the input / output (I / O) port of the personal computer (PC) can be used as 3F8H-2E8H, four communication modules ( COM1-COM4) types. Table 1 is shown in Table 1 below.

TABLE 1

Therefore, the user's port is selected and used according to the output command data of the address terminals A0-A9 and the selection of the 1-3 communication selection switch SW1-SVR3. The address terminals A0-A2 are UART. The logic enable signal is assigned to the interrupt enable register of the corresponding communication port.

For example, when the first communication port (COMl) is selected in Table 1, the user places the first and second communication selection switches SW1 and SW2 to be connected to the contact point 1.3 and selects the third communication. The switch SW3 is placed at the position of the contact point 2.4. In addition, when all eight times are changed from "high" to "low" through the address terminals A0-A2, the address terminals A3-A9 are all output as "high", where the address terminals A0-A2 ) Is the initial "3F8H" when the state of all the "low", and the last "3FFH" when the mode "high", it can be seen that the input and output ports from 3F8H to 3FFH of the first communication port (COMl) is assigned and set. have. At this time, the microcomputer (μ-com) of the modem generates an interrupt signal through the interrupt terminal (INT), and makes an interrupt to the PC to the interrupt request terminal (IRQ4) through the contact point 1.3 of the first communication selection switch SW1. In this case, a predetermined device is selected to use the area of the input / output port up to 3F8H-3FFH, which is the first port. With the third communication selector switch SW3 left at the contact point 2.4, the first and second communication selector switches SW1 and SW2 are operated to move to the contact point 2.4 position, and the address terminals A0-A2. When all the above 8 signals are output from "low" to "high", the logic port is given to the interrupt enable register of the internal UART of the microcomputer (μ-com) to select the corresponding communication port. do. At this time, if all of the "high" is applied through the address terminals A3-A9, there is no change with the first communication port COMl except that it is "low" by the inverter Nl, so that the input / output port address value is "2F8H." "The conversion is up to -2FFH. At this time, the second communication port (COM2) of the table 1, the microcomputer (μ-com) through the interrupt terminal (INT) and through the contact (2.4) of the first communication selection switch (SW1) The request is made to the PC through the Interrupt Request Group (IRQ3). As a result, the port is allocated for data communication through the "2F8H" 2FFH I / O port, which is the PC second communication port (COM2).

Then, the first and second communication selector switches SWl and SW2 are interlocked, and are left in the contact point 1.3 as above, and the third communication selector switch SW3 is moved to the contact point 3.4 and then the address terminal A0-. When the signal for converting A2) 8 times as described above is sequentially output, "high" is output as described above through the address terminals A3-A9. At this time, there is no change except that it is changed to "low" by the butter (N3), so 3E8H-3EFH can get the value until all the address terminals A0-A2 go from "low" to "high". You can select (COM3). The signal is input to the interrupt request terminal IRQ4 through the interrupt terminal lNT to the PC through the first communication selection switch SW1. The third communication selection switch SW3 is left in the same state as when the third communication port COM3 is selected, and the first and second communication selection switches SW1 and SW2 are positioned at the contact point 2.4. Inverted at N2), the state of the address signals A4 and A8 ends. At this time, when the address stages A0-A2 are changed eight times, and changes from 2E8H to 2EFH, an interrupter is requested through the interrupt request stage IRQ4 to select an input / output address port as the fourth communication port COM4.

That is, the signal of the interrupt terminal INT output from the microcomputer μ-com is output to the PC by the interrupt request terminal IRQ3-IRQ4 according to the operation of the 1-3 communication selection switches SW1-SW3. If an interrupt is requested, select a port to communicate between the PC and the modem. The selection of the 1-3 communication selection switch (SW1-SW3) and the port can be summarized by the following Table 2.

TABLE 2

As described above, since the use port of a modem or peripheral device can be easily expanded, there is an advantage of widening the selection of port use when transmitting and receiving data between the PC and the peripheral device.

Claims (1)

In the port expansion circuit between the personal computer and the microcomputer (μ-com) of the modem, the A22 of the bus lines A11, A22-A31, B24-B25, and D0-Dn of the parallel bus line 10 of the personal computer. -A31 is connected to the address terminals A0-A9 of the personal computer so that the address signal is generated, and the address enable signal terminal is connected to A11.

A enable signal is generated through the digital bus, and the data bus D0-Dn of the microcomputer (μ-com) is connected to D0-Dn, and B24-B25 is the personal computer interrupt request terminal (IRQ3-IRQ4). Is connected, the address signal A4 generated through the A27 is input to the inverter N3, and is connected to the 3.4 contact terminal of the third communication selection switch SW3 from the inverter N3, and the address A4. The signal terminal of the inverted terminal of the third communication switch (SW3) is connected to the 2.4 contact terminal, and the address enable terminal

Is connected to the inverter N2, and the address signal of the address A8 generated through the A23 is connected to the 2.4 contact terminal of the second communication selection switch SW2 through the butter N1, and the second, The output terminal of the NAND gate NA1 is connected to the output terminal of the three communication selection switches SW2 and SW3, the inverter N2 and the address A3, A5-A7, and A9 terminals to the input terminal of the NAND gate NA1. Chip selector stage on the side microcomputer (μ-com)

The address terminal A0-A2 is connected to receive the sequential signal to the address terminal A0-A2 of the microcomputer micro-com, and the interrupt terminal of the microcomputer micro-com

And a first communication selection switch (SW1) connected to the communication port extension circuit.

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