KR900006487B1 - Construction of semiconductor device - Google Patents

Abstract

The MOS transistor comprises a first conduction type semiconductor substrate (1); a second conduction type drain region (8) formed on the predetermined area of the substrate (1) and connected to the bit line of DRAM; and gate electrodes 93) formed on the drain region (8). A first conduction type breaker layer (13) is formed beneath the drain region (8).

Description

Contact structure of semiconductor device

1 (a)-(d) is a manufacturing process diagram of one embodiment according to the present invention.

2 (a) is an energy band diagram of a conventional contact portion.

Figure 2 (b) is an energy band diagram according to the present invention.

3 is a cross-sectional distribution of added impurities in the contact region.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact structure of a semiconductor device, and more particularly to a contact structure of a semiconductor device for reducing soft error rate, leakage current, and junction capacitance.

Where a conventional contact (contact) is required N + or P + layer was used. However, by using N + or P + layers, soft error ratio (SER) has become a problem in DRAM memory cells, etc., and in general circuits, there is a problem in junction capacitance and leakage current due to the depth of N + or P + layers. It became.

It is therefore an object of the present invention to provide a contact structure that reduces the soft error rate and reduces leakage current and junction capacitance.

In order to achieve the above object of the present invention, the present invention provides a semiconductor substrate of a first conductivity type, a semiconductor region of a conductivity type opposite to a substrate formed in a predetermined region of the substrate surface, and a predetermined conductive layer on the semiconductor region. A semiconductor device having a semiconductor device, characterized in that a lower portion of the semiconductor region is provided with a blocking layer of the first conductive type in contact with the semiconductor region.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 (a)-(d) are sectional views of a portion of a DRAM memory cell as a manufacturing process diagram of an embodiment according to the present invention.

In FIG. 1 (a), a gate oxide film 2 is formed on a P-type (P−) semiconductor substrate 1, and a polycrystalline silicon gate 3 is formed, and then high concentration N is formed to form a drain and source region of a transistor. Type (N +) ion implantation is performed.

At this time, the region 5 in the ion implantation region of the N type (N +) becomes a drain region of each transistor, and the region 4 becomes a common source region of two transistors.

Then, a photomask is formed on the gate and the upper surface of the substrate to form an insulating layer 6 and to activate the ion implantation region to form drain and source regions 7 and 8 and to form a connection region with a bit line. (9) is formed as shown in FIG. 1 (b).

Then, the insulating film 6 is etched using the photomask 9 as an etching mask, and ion implantation of P-type (P−) is performed through the etched region 10 to remove the photomask 9. .

Then, a conductive film 12 for forming a bit line is formed on the substrate, a predetermined bit line pattern is formed, an insulating film layer l4 is formed on the conductive film 12, and a connection window is formed at a predetermined portion. Then, the metal electrode 15 is formed.

The region 13 under the drain region 6 is a P-type semiconductor region formed by activating the P-type ion implantation region 11.

The ion implantation of the P-type (P−) is low in the source region of the N-type (N +) and is higher than that of the P-type (P−) substrate.

Hereinafter, the effects of the present invention will be described in detail with reference to FIGS. 2 (a)-(b) and FIG. 3.

FIG. 2 (a) is an energy band diagram of a conventional contact region, which shows energy levels of a high concentration (N +) source region and a low concentration (P--) substrate region, where E1 is the energy level of the valence band and E2 is the energy level of the conduction band. Ef is the Fermi level.

FIG. 2 (b) is an energy band diagram of a contact region according to the present invention, which shows energy levels of the source region N + wave blocking region P− and the substrate region P−, which will be displayed as shown in the figure. Can be easily understood by those of ordinary skill in the art.

In general, the alpha particles generated from the assembly material of the semiconductor device enter the substrate region from the surface of the device, and electrons in the excited holes and electrons penetrate into the N + region so that the DRAM detects the bit line and generates a soft error.

However, in the case of the present invention, the electrons generated in the substrate must pass through the P-type (P-) blocking layer formed between the substrate region and the source region before being transferred to the N-type (N +) source region. By exceeding the energy level difference of the region a as shown in the figure, the soft error rate is reduced accordingly.

3 shows a cross-sectional distribution of added impurities in the contact region, indicated by the solid line, shows the distribution of N + impurities and the line 40 shows the distribution of P-impurities in the substrate in contact with the conventional N + source region. Shows the distribution of P-impurities in the Chaman layer according to the present invention.

By forming the barrier layer according to the present invention, as shown in FIG. 3, the junction depth of the N-type source region is reduced by the difference between X2 and X1.

In the above embodiment, the N + contact region formed on the P-type period has been described, but the case of the P + contact formed on the N-type substrate is the same as in the above embodiment, which can be easily understood by those skilled in the art. will be.

As described above, the present invention provides a soft error in a memory cell by forming a blocking layer of the same conductivity type as the substrate between the substrate and the contact region when forming a contact region opposite to the substrate on the substrate of the first conductivity type. In general circuits, it is possible to reduce the depth of the junction.

Claims (3)

A semiconductor substrate 1 of a first conductivity type, a drain region having a conductivity opposite to that of the first conductivity type substrate formed in a predetermined region of the substrate surface and connected to a bit line of a DRAM, and the drain region 8 A Morse transistor of a DRAM having an upper gate electrode 3, wherein the first conductive type blocking layer 13 is provided below the drain region 8 to be in contact with the drain region 8. Contact structure of MOS transistor. The contact structure of MOS transistor according to claim 1, wherein the first conductive blocking layer (13) is a semiconductor region of the same conductivity type having a higher concentration than the substrate. 2. The contact structure of MOS transistor according to claim 1, wherein the blocking layer (l3) of the first conductivity type is a semiconductor region of opposite conductivity type having a lower concentration than the drain region (8).

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