KR900006320B1 - Light emission diode array - Google Patents
Light emission diode array Download PDFInfo
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- KR900006320B1 KR900006320B1 KR1019870014379A KR870014379A KR900006320B1 KR 900006320 B1 KR900006320 B1 KR 900006320B1 KR 1019870014379 A KR1019870014379 A KR 1019870014379A KR 870014379 A KR870014379 A KR 870014379A KR 900006320 B1 KR900006320 B1 KR 900006320B1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 14
- 230000010354 integration Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 5
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000005476 soldering Methods 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 9
- 238000003491 array Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Led Devices (AREA)
- Led Device Packages (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
Abstract
Description
제1도는 조립된 발광다이오드 어레이의 개략도.1 is a schematic diagram of an assembled light emitting diode array.
제2로는 종래의 반도체 기판상의 발광다이오드 어레이의 평면도.Secondly, a plan view of a light emitting diode array on a conventional semiconductor substrate.
제3도는 본 발명의 반도체 기판상의 발광다이오드 어레이의 평면도이다.3 is a plan view of a light emitting diode array on a semiconductor substrate of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
12: 반도체 기판 13: 발광부12: semiconductor substrate 13: light emitting portion
14: 전극.14: electrode.
본 발명은 프린터에 사용되는 고밀도 발광다이오드 어레이에 관한것으로 특히 개개 발광다이오드 전극의 금속배선을 위한 유효면적을 넓혀 줌으로서 단위면적당 발광다이오드 어레이의 고질적화를 이룩할 수 있는 발광다이오드 어레이의 전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density light emitting diode array used in a printer, and more particularly, to a method of forming an electrode of a light emitting diode array capable of achieving high quality of the light emitting diode array per unit area by increasing the effective area for metal wiring of individual light emitting diode electrodes. It is about.
정보기기가 발달함에 따라 그 출력기기로써 고속·고품위·저가의 프린터가 개발되고 있으며, 이러한 출력기기중에는 반도체 발광다이오드 어레이를 이용한 프린터도 개발되고 있다.As information devices are developed, high-speed, high-quality and low-cost printers have been developed as output devices, and printers using semiconductor light emitting diode arrays have also been developed.
발광다이오드 어레이를 이용한 프린터는 같은 광출력방식인 레이저 프린터와는 달리, 다면경을 이용하는레이저 주사 장치와 같은 기계적 가동부를 가지지 않으므로 그 신뢰성이 높고 구성부품수가 적으며 광경로도 짧기 때문에 고속·고품위의 기록특성을 가지는 소형의 프린터로 제작 가능하게 된다.Unlike laser printers with the same light output, a printer using a light emitting diode array does not have a mechanical moving part like a laser scanning device using a multi-facet mirror, so its reliability is high, the number of components and the optical path are short. It is possible to produce a compact printer having recording characteristics.
이러한 발광다이오드 어레이 프린터는 제1도에서 도시하고 있는 바와 같이, PN 접합을 가지는 발광부(도시되지 않음.)가 세라믹 기판(1)상의 반도체 기판(2)에 집적화되고 각각의 발광부의 전극(4)은 외부배선판(5)과 금선(6)으로 연결되는 구조로 되어 있다.In this light emitting diode array printer, as shown in FIG. 1, a light emitting portion (not shown) having a PN junction is integrated into the semiconductor substrate 2 on the ceramic substrate 1, and the
한편 최근에와서는 단순한 글자 출력 이외에 그래픽 기능까지 가지는 프린터가 요구됨에 따라서 상기한발광다이오드 어레이는 더욱 고밀도화가 요구되는데, 반도체 기술의 발달로 PN 접합에 의해 발광부는 수십 ㎛정도의 작은 크기로 제작 가능하기 때문에 mm당 십수개의 발광부를 집적시킬수는 있으나, 금선배선을 위한 발광부의 전극의 기본적인 크기가 요구되므로 단위 면적당 발광다이오드 어레이의 집적도에 제한을 받게 된다.On the other hand, in recent years, as a printer having a graphic function in addition to simple text output is required, the light emitting diode array is required to be more dense. Due to the development of semiconductor technology, the light emitting unit can be manufactured in a small size of several tens of micrometers by PN bonding. Therefore, it is possible to integrate dozens of light emitting units per mm, but since the basic size of the electrode of the light emitting unit for gold wiring is required, the degree of integration of the light emitting diode array per unit area is limited.
따라서 발광부의 전극이 차지하는 면적을 효율적으로 사용하기 위한 수단이 필요하게 되었고, 그 결과 제2도와 같은 방법으로 발광다이오드 어레이의 전극을 설계하기에 이르렀다.Therefore, a means for efficiently using the area occupied by the electrodes of the light emitting part has been required. As a result, the electrodes of the light emitting diode array have been designed in the same manner as in FIG.
이러한 방식은, 발광부(3)를 반도체 기판(2)의 중심에 제조하고 사각형의 전극(4)을 발광부(3)의 양쪽으로 배치함으로써, 종전의 한쪽에 배치한 경우보다 단위면적당 2배의 집적도를 실현할수 있었다.In this manner, the
그러나 그래픽 기능의 기본 규격이 되는 mm당 16개의 발광다이오드 어레이를 집적하기 위해서는 한쪽에 8개의 전극이 필요하게 되며, 이때 한 전극의 중심에서 이웃한 전극의 중심까지의 거리가 125㎛로 되므로각 전극간의 분리를 위한 간격을 고려하면 전극하나의 폭은 100∼120㎛가 되는데, 금선연결의 일반적인방법인 볼 본딩의 경우, 금선의 볼 크기가 100㎛ 내외의 직경으로 되기 때문에 고밀도의 연결기술이 필요하게 되며, 또한, 조립도 매우 어려웠다.However, in order to integrate 16 LED arrays per mm, which is the basic standard for graphic functions, eight electrodes are required on one side, and the distance from the center of one electrode to the center of the neighboring electrode becomes 125 μm. Considering the gap for separation between the electrodes, the width of one electrode is 100 ~ 120㎛. In the case of ball bonding, which is a common method of gold wire connection, a high density connection technology is required because the ball size of the gold wire is about 100 μm in diameter. In addition, the assembly was very difficult.
본 발명은 이와 같은 점을 감안하여 안출한 것으로, 발광부 전극의 헝태를 변형시켜 금선배선을 위한 유효면적을 넓혀주면서 단위면적당 집적도를 향상시킬 수 있는 발광다이오드 어레이의 전극 형성방법을 제공하는 것을 목적으로한 것이다.The present invention has been made in view of the above, and an object of the present invention is to provide a method of forming an electrode of a light emitting diode array which can improve the degree of integration per unit area while widening the effective area for gold wiring by modifying the shape of the light emitting unit electrode. It is.
본 발명의 특징은 발광부의 전극을 요·철형으로 형성하고 이들의 요부와 요부사이에는 철부가, 철부와 철부사이에는 요부가 위치되게 배치하여, 금선배선을 위한 유효면적을 확보시켜 줌과 동시에 단위면적당 발광다이오드 어레이의 집적도를 향상시킬 수 있다는데 있는 것이다.A feature of the present invention is that the electrodes of the light emitting part are formed in a concave-convex shape, and convex portions are disposed between the concave portions and the concave portions, and concave portions are positioned between the concave portions and the concave portions, thereby securing an effective area for gold wiring and at the same time, unit. The integration degree of the light emitting diode array per area can be improved.
이하 첨부도면에 따라 본 발명을 설명한다.Hereinafter, the present invention will be described in accordance with the accompanying drawings.
제3도와 같이, 고밀도 발광다이오드 어레이를 형성시키기 위한 반도체 기판(12)의 중심에 발광부(13)를 형성시키고, 이 발광부(13)와 전기적으로 연결되면서 외부와의 금선연결을 위한 전극(14)을 그 양쪽으로 형성시키되, 이 전극(14)에는 요부(B)와 철부(A)를 형성시켜 요부(B)와 요부(B)사이에는 철부(A)가, 철부(A)와 철부(A)사이에는 요부(B)가 위치되게 형성시킨다.As shown in FIG. 3, the
이와 같은 본 발명의 작용 및 효과를 설명하면 다음과 같다.Referring to the operation and effect of the present invention as follows.
제3도에 도시하는 바와 같이, 전극(14)은 인접한 전극끼리 서로 반대되는 요·철부(B,A)를 가지면서발광부(13)를 중심으로 양쪽으로 배치된다. 이때 외부와의 전기적 접속을 위한 금선은 상기 전극(14)의 철부(A)를 이용하게 되는데, 이 철부(A)는 금선연결을 위한 충분한 유효접속면적을 가지면서도 그 중심간의간격은 종래의 경우보다 훨씬 좋게 된다.As shown in FIG. 3, the
따라서 이와 같은 본 발명은, 반도체 기관의 전체면적이 유효적절하게 활용됨과 동시에 그 연결작업이 수월하게 되므로 발광다이오드 어레이의 집적도 향상과 생산성 향상을 가져오게 되는 특징을 지닌다.Therefore, the present invention has the feature that the overall area of the semiconductor engine is effectively utilized and the connection work is facilitated at the same time, resulting in improved integration and productivity of the light emitting diode array.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019870014379A KR900006320B1 (en) | 1987-12-17 | 1987-12-17 | Light emission diode array |
Applications Claiming Priority (1)
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KR1019870014379A KR900006320B1 (en) | 1987-12-17 | 1987-12-17 | Light emission diode array |
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KR890011057A KR890011057A (en) | 1989-08-12 |
KR900006320B1 true KR900006320B1 (en) | 1990-08-28 |
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KR1019870014379A KR900006320B1 (en) | 1987-12-17 | 1987-12-17 | Light emission diode array |
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