KR900002634B1 - Time division multiplex communications i/o device - Google Patents

Abstract

The equipment comprises a terminal interface (1), a communication line interface (2) connected to a communications line, a communication data I/O circuit (3) which arrays, converts I/O data for the interface (2) and signals, sets a connection route and controls synchronisation, a control part (4) controlling the action of each part with a microcomputer as a main comprising element, an address switch (5) of its own station and a communication condition switch (6). The communication data I/O circuit (3) is independently provided separate from the outer elements comprising the time division multiples communication equipment.

Description

Time Division Multiple Communication I / O Device

1 is a block diagram showing the overall configuration of an embodiment of the present invention.

2 is a block diagram showing an outline of an example of a communication data input / output circuit which is a main part of one embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1: terminal interface 2: communication line interface

3: communication data input / output circuit 4: control unit

5: Self address switch 6: Communication condition switch

11: data bus

12: parallel data transmission-to-serial converter (parallel converter)

13: Transmission data output buffer 14: Transmission timing determination circuit

15: Receive data input buffer

16: Serial-to-parallel converter (serial converter)

17: Receive timing determination circuit 18: Communication connection request detection circuit

19: relative address detection circuit 20: terminal number setting circuit

21: local address input circuit 22: decoder circuit

23: switch status input circuit 24: address bus

The present invention relates to a time division multiplexing device connected between a terminal device and a communication line and performing input / output control for a terminal device of time division multiplexing communication as a communication line.

Background Art Conventionally, in data communication such as LAN (abbreviation for local area network), a time division multiple communication method is generally employed for efficient use of a communication line.

There are various types of time division multiplexing methods. However, two types of synchronization signals, vertical and horizontal, are used as a method suitable for data communication in a relatively small LAN.

In the time division multiplexing communication by this method, a time division multiplexing device is provided between the terminal apparatus and the communication line to transmit data from the terminal and receive data from the communication line.

Conventionally, this type of time division multiplexing communication apparatus includes a terminal interface connected to a terminal, a communication line interface connected to a communication line, an array conversion of input / output data, signals, and the like, and a connection path setting for the communication line interface, And some means for performing synchronous control and control of each of these functions.

However, by standardizing such a device, it is possible to reduce the price of the device and reduce the size and weight of the device.

In this case, since each component of the conventional apparatus is closely related to each other, it has been conventionally considered to standardize as an entire apparatus.

However, in data communication such as a relatively small LAN, the performance of the terminal device and communication line used for each system is varied depending on the use or scale of each system, making it difficult to standardize the whole device. .

For this reason, conventionally, the time-division multiplexing device used for these has been comprised by designing the thing suitable for each data communication system.

In the case of a small LAN or the like, when manufacturing a separately designed time-division multiple communication device, there is a problem that it is difficult to produce a large quantity because of the small number, and the production of hand work on separate parts is expensive. .

In addition, since it is manufactured by separate parts, the number of parts is increased, which takes a lot of time in production, and it is difficult to miniaturize the entire apparatus.

In addition, when the system of the LAN is to be changed, for example, when the transmission speed is changed, etc., in the conventional apparatus, since the configuration of the apparatus is inflexible, it is necessary to replace the entire time division multiple communication apparatus. As a result, there has been a drawback that is very costly to improve the quality of the system.

On the other hand, the present inventors have analyzed and studied various functions of the time division multiple communication device and its circuit configuration, and as a result, it is possible to standardize a part of the device even if it is difficult to standardize the whole device. However, it has been found that even if some of the parts are standardized, the system price can be expected to be lowered, and the flexibility of the system can be changed.

In particular, the communication data input and output circuits have been found to have abrasion of their size and an increase in effect.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems on the basis of this point, and can be widely applied to various data communication systems having different performances, and it is also flexible to change in the same system. In order to provide a time-division multiple communication device that can cope with, and to reduce the number of parts by reducing individual design parts, to be lightweight and compact, and to be mass produced, and to be manufactured at low cost. do.

The present invention provides the above-described time division multiple communication apparatus comprising a component that performs a function as an input / output circuit of communication data in a time division multiple communication apparatus connected between a terminal apparatus and a communication line. It is a separate functional device separate from the circuit components that perform other functions of, characterized in that configured as a module (Module).

There are various kinds of components that perform a function as an input / output circuit of the communication data.

For example,

(1) means for detecting a synchronization signal transmitted on a communication line to determine transmission timing of an own device, and means for determining a reception timing of received data of its own device by detecting a synchronization signal transmitted on a communication line. .

(2) data output means having a function of transmitting data parallel-serial conversion and a buffer, and data input means having a function of buffer and receiving data serial-parallel conversion.

(3) A means for identifying whether or not data transmitted to a communication line is reception of its own device.

(4) Relative address detection means for counting a synchronization signal and detecting a relative address for which communication is desired.

⑤ A means for entering home address.

⑥ A means for setting the number of terminals connected to the communication line.

⑦ Interface means such as data bus.

The present invention combines all or part of these elements, separates them, and modularizes them as independent functional elements.

In addition, the present invention is not limited to the above means as long as it is a circuit portion which is not affected by the change of the system, etc., and can be added to the above means.

Modularization in the present invention is most effective with a monolithic IC in which components are placed on one chip.

However, the present invention is not limited to this, but it is also possible to form a component by a plurality of chip ICs and place it on one printed circuit board.

In addition, it may be performed by a hybrid IC.

The present invention extracts a component that performs a function as an input / output circuit for communication data between a communication line and a terminal device from a component of a time division multiple communication device, and performs other functions of the time division multiple communication device. It is separate from the circuit components it performs.

This is because these components can be used for changing the transmission speed or the like without changing the configuration contents.

As a result, when applied to communication systems of various types and purposes, and when changing from the same system, only different components may be designed or changed separately. It is possible to respond flexibly.

Since a part of the time division multiple communication device can be formed as a standardized mass production product, the price of the entire system can be reduced.

An embodiment of the present invention will be described in detail with reference to the accompanying drawings.

EXAMPLE

An embodiment of the present invention is a time division multiple communication apparatus applied to a single bus type LAN having a bus type communication line, which adopts frame synchronization by a vertical synchronization signal in two types of synchronization signals, vertical and horizontal, This is an example applied to time division multiple communication taking slot synchronization by a horizontal synchronization signal.

The time division multiple communication input / output device according to the embodiment of the present invention is used in a time division multiple communication apparatus in combination as part of its components.

As shown in FIG. 1, this time division multiplexing device includes a terminal interface 1 connected to a terminal device (not shown), a communication line interface 2 connected to a communication line (not shown), The operation of each part is performed using the communication data input / output circuit 3 and the microcomputer as main components for performing input / output data, array conversion of signals, etc., connection path setting and synchronous control for the communication line interface 2, and the like. The control unit 4 to control, the local station address switch 5, and the communication condition switch 6 is provided.

In these components, the communication data input / output circuit 3 is a time division multiple communication input / output device of the embodiment of the present invention.

2 shows an outline of an example of this communication data input / output circuit 3.

The communication data input / output circuit shown in FIG. 2 includes the following components.

Ⓐ A transmission data parallel-to-serial converter 12 (hereinafter referred to as a parallel converter) that performs a function as a data output means to convert an array from parallel to serial, and transmission data as a communication line (not shown) for a while. The transmission data output buffer 13 which is held for a while.

B) a transmission timing determining circuit 14 which is means for detecting the vertical and horizontal synchronization signals from the communication line and setting the transmission timing of the transmission data of the own apparatus.

A receiving data input buffer 15 which performs a function as a data input means for holding the received data input from the communication line for a while and a receiving data serial-to-parallel converter 16 for converting the received data from serial to parallel. (Hereinafter abbreviated as direct converter).

Reception timing determining circuit 17 which is means for detecting the vertical and horizontal synchronization signals from the communication line and setting the reception timing of the reception data of the reception by the own device.

Ⓔ A communication connection request detection circuit 18 which detects whether or not the received data is the reception of its own device and outputs a communication connection request signal to the control unit 4 when the reception data is received by the own device.

A relative address detection circuit 19, which counts the synchronization signal and detects the relative address, and sends it to the reception timing determination circuit 17 based on the reception timing decision.

Ⓖ terminal number setting circuit 20 which is a means for setting the number of terminals as a reference for determining transmission and reception timing.

A local address input circuit (21) which is a means for setting a local station address for the transmission timing determining circuit (14) and the communication connection request detection circuit (18).

Functions as an interface means, and transmits / receives communication data, addresses, and the like, the data bus 11 for connecting the corresponding parts, the connection state between the data bus 11 and the parts, the communication conditions, and the like. A switch status input circuit 23 for inputting a switch status (Status) for determination, and a decoder circuit 22 for receiving control signals and addresses from the control section 4, decoding them, and giving operation instructions to the respective sections. ).

The greatest feature of the embodiment of the present invention is that the above-mentioned circuit elements are modularized as independent functional elements separately from other circuit elements in the time division multiple communication apparatus.

Such modularization is performed in the case of the embodiment of the present invention by converting a functional portion into a single chip as a custom IC or the like, and is actually housed in a dual in line package or the like.

The connection relationship when combining the communication data input / output circuit functionalized as described above with the time division multiple communication device shown in FIG. 1 is as follows.

First, the control unit 4 connects the decoder circuit 22 and the data bus 11.

These are connected so as to transmit data and the like as paradies, respectively.

In addition, with respect to the communication line interface 2, the transmission data output buffer 13 and the transmission timing determination circuit 14, the reception data input buffer 15 and the reception timing determination circuit 17, and the communication connection request detection are performed. The circuit 18 and the relative address detection circuit 19 are connected.

These are connected so as to transmit data and the like as serial, respectively.

The transmission timing determination circuit 14 and the reception timing determination circuit 17 have a counter type.

The former counts the synchronization signal using the local station address inputted by the local station address input circuit 21 and the value input from the terminal number setting circuit 20 as a target value, thereby generating a slot capable of transmitting the own device. Decide

On the other hand, the latter is a slot of reception of the own apparatus by counting the synchronization signal using the relative address input by the upper address detection circuit 19 and the value input from the terminal number setting circuit 20 as target values. Determine.

The switch status input circuit 23 is connected to the communication condition switch 6 shown in FIG. 1 and the local station address input circuit 21 is connected to the local station address switch 5, respectively.

Time-division multiplexing communication applied to the embodiment of the present invention has been made in such a manner that, as described above, frame synchronization is performed by the vertical synchronization signal, and slot synchronization is performed by the horizontal synchronization signal.

This method is configured to set more slots than the number of terminals in one frame, give each slot an address corresponding to the terminal, and give each terminal at least one communication opportunity in one frame. It is done.

In each terminal, communication is carried out by placing a communication data packet in the assigned slot.

At this time, a vertical synchronization signal and a horizontal synchronization signal successively connected thereto are sequentially output from the syncronizer (not shown) at predetermined time intervals.

As an example of such a frame configuration, one frame is divided by 489 horizontal synchronous signals to form 488 slots, one frame is 16.6 ms long, and the vertical synchronous signal is 0.6 ms horizontal. The synchronization signal is 5 s, the slot length is 32.5 s and the data length is 20 s.

In addition, the package inserted in each slot is set as 20 bits in the Example of this invention.

The first one bit is a star art bit, the next three bits are control bits, and the remaining 16 bits are data bits.

When a plurality of terminal devices, for example, 61 terminal devices are connected to a communication line having such a frame structure, each terminal has eight data transmission opportunities in one frame.

Since one package is 20 bits, the data transmission rate per one terminal is represented by the following equation.

8 times × 20 bits × 60 / s = 9600 bits / s

In each terminal, communication is carried out by loading a communication data package in the assigned slot.

Here, a case of transmitting from the terminal side will be described.

Before using the apparatus, the number of terminals of the LAN is set in the terminal number setting circuit 20 in the communication data input / output circuit 3 of the embodiment of the present invention.

This number is maintained as it is unless there is a change in the number of terminals of the LAN.

The decoder circuit 22 receives the control signal from the control part 4, decodes it, and according to the instruction | indication content, the parallel converter 12, the serial converter 16, the relative address detection circuit 19, and the host. The operations of the address input circuit 21 and the switch status input circuit 23 are respectively controlled.

For example, at the time of data transmission, the local station address assigned to the terminal is sent to the transmission timing determination circuit 14 by the data bus 11 via the address bus 24, and the local station addresses are set therein. Put it.

This address is also kept as it is unless there is a change.

Next, the decoder circuit 22 connects the data bus connected to the control unit 4 and the parallel converter 12 by the data bus 11.

The control unit 4 sends the data from the terminal apparatus to the parallel converter 12 via the terminal interface 1 and the control unit 4.

The transmission data converted serially as the parallel converter 12 is stored as the transmission data output buffer 13 for a while.

At this time, the transmission timing determination circuit 14 detects the synchronization signal of the communication line and sets the transmission timing.

The transmission timing is determined based on the vertical synchronization signal based on the number of connection terminals set in advance and the local station address.

That is, a slot capable of transmitting its own device is determined by counting the horizontal synchronization signal subsequent to the vertical synchronization signal with the local address inputted by the local address input circuit 21 as a target value.

As described above, since the data of the own device, which is the number corresponding to the number of slots of one frame divided by the number of preset terminals, can be transmitted, the transmission timing determination circuit 14 is horizontal. The synchronization signal is counted by the number of connection terminals, and the count is repeated to determine the slot.

Such repetition is possible for the above-mentioned recovery amount.

When the count value becomes a value corresponding to the local station address, it is determined that the slot is capable of transmission, and the transmission timing determination circuit 14 determines the transmission data stored in the transmission data output butter 13 on the communication line. Output to the communication line via the interface (2).

At this time, the transmission timing determination circuit 14 outputs a signal to the parallel converter 12 to allow input of the next transmission data.

As a result, the following transmission data is input to the parallel converter 12 as described above.

Next, a case of receiving data from another terminal magnetic value will be described.

Data is input from the communication line via the communication line interface 2 and stored in the received data input buffer 15 for a while.

This received data is converted into serial data from serial data in the serial-to-parallel converter 16.

The communication connection request detection circuit 18 compares the received data with a preset local station address, and sends a communication connection request signal to the control unit 4 when it is determined that the received data is the reception of its own apparatus.

The control unit 4 sends a signal capable of communication to the counterpart device via the communication line, and inputs the address of the host device from the counterpart address detection circuit 19 via the data bus 11.

Upon receiving this, the data from the counterpart device is inserted into the slot assigned to the counterpart device and transmitted on the communication line.

In addition, the reception timing determination circuit 17 detects the synchronization signal of the communication line and sets the reception timing.

The reception timing is determined on the basis of the vertical synchronization signal and determined based on the number of connection terminals set in advance and the relative address detected as the relative address detection circuit 19 as a target value.

In other words, by counting the horizontal synchronous signal behind the vertical synchronous signal with the relative address input by the relative address detection circuit 19 as a target value, the slot of the relative device to be received by the own device is determined.

In addition, as in the case of the above-mentioned transmission, since the counterpart apparatus can transmit data corresponding to the number of slots divided by one frame by the preset number of connected terminals, the horizontal synchronization signal is divided into the number of connected terminals. Count, and repeat counting to determine the slot.

Such repetition is possible for the above-mentioned recovery amount.

When the count value becomes a value corresponding to the relative address, it is determined that the slot is to be transmitted, and the reception timing determining circuit 17 determines the received data input buffer (from the communication line through the communication line interface 2). The received data stored in 15) is transferred to the serial-to-parallel converter 16 to convert serial data into parallel data.

Here, the decoder circuit 22 decodes the control signal from the control unit 4 and connects the serial-to-parallel converter 16 and the data bus to the control unit 4 by the data bus 11. .

As a result, the received data is input to the terminal apparatus via the control unit 4 and the terminal interface 1.

Next, a change of the system, for example, a case of changing the transmission line speed of the communication line to be further described will be described.

In the embodiment of the present invention, it is necessary to change some or all of the circuits for the terminal interface 1, the communication line interface 2, and the control unit 4.

However, with respect to the communication data input / output circuit, which is an essential part of the present invention, in the transmission timing determination circuit 14 and the reception timing determination circuit 17, the horizontal synchronization signal is counted based on the vertical synchronization signal of the communication line. Thus, since the transmission and reception timings are set, even if there is a change in the transmission speed of the communication line, it is possible to respond as it is.

Therefore, when changing the quality improvement of a system, it can respond flexibly.

This means that the part of the communication data input / output circuit of the embodiment of the present invention modularized has versatility.

This makes it possible to use a modularized part of the communication data input / output circuit for a time division multiple communication device such as a LAN having various performances.

Therefore, in the configuration of the time division multiplexing device according to the embodiment of the present invention, the standardization of a part of the device makes it possible to reduce the price of the system and to have flexibility in changing the system. .

In addition, in the embodiment of the present invention, since the portion of the communication data input / output circuit is modularized, the individual design portions in other components are reduced, so that the number of parts is reduced, which makes the time division multiple communication apparatus more suitable. It can be made cheaper because it can be lighter and smaller, and can be produced in large quantities.

This invention is not limited to the above-mentioned embodiment, Various forms are possible.

For example, in the above embodiment, it is conceivable to modularize a part of the circuit components rather than all of them.

For example, a combination of the above-described modularized components is as follows.

Transmission timing determining circuit 14 and receiving timing determining circuit 17;

Ⓑ a parallel converter 12 and a transmission data output buffer 13;

Ⓒ combinations of the above items ⓐ and ⓑ.

Ⓓ The communication connection request detection circuit 19 is added to the above items ⓐ, ⓑ or ⓒ.

Ⓔ The relative address detecting circuit 19 and the terminal number setting circuit 20 are added to the above items ⓐ, ⓑ, ⓒ or ⓓ.

The relative address detection circuit 19 and the terminal number setting circuit 20 are added.

In addition, as in the example of the above modification, when the elements of the circuit to be modularized are less, the effect of circuit simplification of the apparatus as a whole becomes less, but instead, there is an advantage that the versatility becomes larger.

As described above, the present invention can be widely applied to various data communication systems having different performances, and can flexibly cope with changes in the same system. By reducing the number of parts, the weight and size can be reduced, the mass production can be performed in large quantities, and the time-division multiple communication apparatus can be configured at a low price.

Claims (5)

In a time division multiple communication apparatus connected between a terminal apparatus and a communication line, a component for performing a function as an input / output circuit 3 of communication data between the communication line and the terminal apparatus is provided. A time division multiple communication input / output device, characterized in that the module is configured separately from the circuit components that perform other functions of the module. The transmission timing determination circuit according to claim 1, wherein the transmission timing determination circuit is a component for performing a function of the communication data input / output circuit (3), and means for determining a transmission timing of an own device by detecting a synchronization signal transmitted on a communication line. And a reception timing determination circuit (17) which is means for detecting a synchronization signal transmitted on the communication line and determining reception timing of the reception data of the own device. 3. A transmission data parallel-serial converter (12) and a buffer function according to claim 1 or 2, which perform a function in the input / output circuit (3) of the communication data. The transmission data output buffer 13 as a data output means, the reception data input buffer 15 as a buffer function, and the reception data serial-parallel converter 16 as data input means having a received data serial-to-parallel conversion function are provided. Time division multiple communication input and output device provided. The communication connection request detection according to claim 1 or 2, wherein the communication connection request detection is a component for performing a function of the communication data input / output circuit (3), and means for identifying whether or not data transmitted to a communication line is reception of its own device. A time division multiple communication input / output device with a circuit 18 added. 3. A transmission data parallel-serial converter (12) and a buffer function according to claim 1 or 2, which perform a function in the input / output circuit (3) of the communication data. A transmission data output buffer 13 serving as a data output means, a reception data input buffer 15 serving as a buffer function, and a reception data serial-parallel converter 16 serving as data input means having a reception data serial-to-parallel conversion function; A time division multiple communication input / output device having a communication connection request detection circuit (18) which is a means for identifying whether or not data transmitted to a communication line is reception of its own device.

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