KR900001129B1 - Indoor branch-type terminal connection device - Google Patents

Abstract

The apparatus for data communication of a system comprising multi- terminals and a host computer having a certain number of terminal mode includes a line receiver and driver unit (21) for receiving and driving the data from a certain number of grouped data ports, branch apparatus connectors (22,23) for connecting function for the grouped data ports utilizing the line receiver and driver unit, multiplexer/ demultiplexer (24) for multiplexing and demultiplexing the transmitting or receiving data through the data port of the branch apparatus connectors and the line receiverdriver unit, and data transmitter and receiver (25,26) connected between the multiplexer/ demultiplexer and the transmitting line.

Description

Branch branch type terminal connection device

1 is a basic configuration of a branch type terminal connection apparatus according to the present invention.

2 is a block diagram of the main device of FIG.

3 is a block diagram of the branching apparatus of FIG.

4 is a timing diagram of a transmission unit.

5 is a detailed view of the data reception and driver of FIG.

6 is a detailed view of the branch connecting part of FIG.

7 is a detailed view of the data transmitter of FIG.

8 is a detailed view of the data reception of FIG.

The present invention relates to a terminal connection device for short-range premises data transmission, and more particularly, to a branch type terminal connection device for connecting and expanding data terminals by a predetermined number of ports by using a connection device composed of a main device and a branch device. It is about.

In the conventional method of connecting a data terminal (particularly, a dummy terminal) and a terminal port of a computer, a one-to-one connection method, a data multiplexer, or an expensive local area network (LAN) system have been used. In the one-to-one connection method of directly connecting the data terminal and the terminal port of the computer, the number of lines increases in direct proportion to the number of terminals, so the number of lines increases and the maintenance is not easy as the number of terminals increases.

In addition, when using the data multiplexer as in the latter case, additional expensive equipment must be introduced even if additional terminals more than the specified number of access terminals are required, and a new dedicated line is required. The data terminal lines have a tendency to be concentrated and complicated. In addition, when LAN is used, the installation cost is high. Especially, the network connection device is very expensive and the installation cost per terminal is very high.

Accordingly, an object of the present invention is to provide a terminal connection device configured to include a main device and a branch device in the short-range premises data transmission, so that data terminals can be expanded and connected in predetermined units.

It is still another object of the present invention to provide a terminal connecting device for facilitating installation of a transmission line by expanding branching devices in proportion to the number of terminal ports of a connecting terminal or a host computer.

Another object of the present invention is to provide a terminal connecting device that can maintain a clean line installation state by maintaining the main line and the branch device in the premises to centrally connect the connection between the connection device and the terminal, the cost of the line installation cost per terminal In providing.

It is still another object of the present invention to provide a terminal access device that can improve the efficiency of line operation by enabling an existing premises telephone network to be used as a transmission line in short-range premises data transmission.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a basic diagram of an embodiment of the present invention. In the embodiment shown in FIG. 1, the apparatus comprises two first and second main apparatuses and up to four first, second, third and fourth branch apparatuses. Each of the second branch apparatus and the third and fourth branch apparatuses is connected to the first and second main apparatuses, respectively. Here, the first and second host devices each have eight data terminal connection ports (TP1 ... TP8), two branch device connection ports, and a data transmission / reception mode capable of transmitting and receiving data between the main device and the main device.

Therefore, if there are eight or less data terminal ports of the data terminal or computer to be connected, it is sufficient to have only the first and second main devices. If the number is 16 or less, one branch device may be connected to the main device for both transmission and reception, and further, one branch device may be added to satisfy up to 24 devices.

2 is a block diagram of the main device of FIG. In the figure, reference numeral 21 denotes a drive circuit for receiving and driving data reception and data transmission from data port DP1) to data port DP8. It consists of widely used RS-232C line receiver and line driver integrated circuits, and the line receiver and line driver increase and decrease according to the number of data ports. Reference numerals 22 and 23 are branch connection connections consisting of an RS-232C line receiver and drive integrated circuits and a 25-pin RS-232C connector. Reference numeral 24 denotes eight data ports DP1... Which are directly connected to the main unit via the data reception and driver 21. The multiplexer / demultiplexer transmits / receives data to / from the data transmitter 25 and the data receiver 26 by multiplexing / demultiplexing a total of 24 data ports such as digital data transmitted / received by 8 DP8 and 2 branch devices.

Reference numeral 25 denotes a data transmission / reception unit that performs data coding and pulse shaping and transmits the data to the transmission line 74 of two lines. Reference numeral 26 denotes a multiplexer / demultiplexer (hereinafter, referred to as MUX / DEMUX) by reproducing clock and data from a signal received through transmission line 76, finding a frame synchronization bit string, and generating a timing signal synchronized thereto. 24) is a data receiver. The MUX / DEMUX 24 divides the bit strings P1-P24 corresponding to 1: 1 into 24 data ports by the reproduced bit strings and the timing signals generated by the data receiver 26.

3 is a configuration diagram of the branching device of FIG. In the drawings, the part consisting of reference numerals 31, 34, 35, 38 is a conventional RS-232C line receiver, and the part consisting of reference numerals 32, 33, 36, 37 is a conventional RS-232C drive. The part corresponding to 39 is a 25-pin RS-232C connector, which is connected to the main device several tens of meters away by 25 lines. In this case, the RS-232C connector 39 is not used according to the RS-232C signal standard, but is used to connect a data line using a mechanical (mechanical) state of the connector as a means for data connection.

The line receiving integrated circuits 31, 34, 35, and 38 are examples of using a general-purpose line receiver 1489, and the line drivers 32, 33, 36, and 37 are general-purpose. The 1488 line driver is an RS-232C level converter.

4 is a timing diagram in data transmission according to the present invention.

FIG. 5 is a detailed view of the data reception and driver 21 of FIG. 2, in which DP1, DP2... RS-232C connector 51 which is connected to DP8 and connects transmission / reception data, respectively. 58 and the RS-232C 51. (58) is connected between the transmit / receive port of the MUX / DEMUX 24 and the DP1, DP2... A plurality of line receptions (LR1, LR2, ... LR7, LR8) for converting data transmitted from DP7 and DP8 to the RS-232C level to the TTL level to be transmitted to the reception port of the MUX / DEMUX 24, and the MUX / DEMUX The TTL level data outputted from the transmission port of (24) is converted into RS-232C level data, and the DP1... It consists of a plurality of line drivers LD1, LD2 ... LD7, LD8 which transmit to DP8.

FIG. 6 is a detailed view of the branching apparatus of FIG. 2, and includes a plurality of line drivers LD9, LD16 for converting TTL level transmission data output from the transmission port of the MUX / DEMUX 24 into RS-232C level data. And a plurality of line receivers LR9... LR17 for converting the received data transmitted at the RS-232C level into TTL level data and transmitting them to the reception ports of the MUX / DEMUX 24, and the line driver LD9. LD16) and an RS-232C connector 61 which connects the outputs and inputs of the line receivers LR9 to LR17 to the RS-232C connector 39 of the first branch device. It is configured in the same manner as above. In this case, the RS-232C connector 61 of FIG. 6 is a 25-pin connector. In the present invention, the RS-232C connector 61 does not transmit a signal in accordance with the RS-232C signal standard, but only for data connection. It is used as a means, that is, a cable connection means for line connection.

7 is a detailed view of the data transmitter 25 of FIG. HDB3 line code circuit 73 which converts the multiplexed input data at 2.048Mbps transmission rate into HDB3 line code standardized by CCITT and outputs it to output terminals OUTA and OUTB. , The emitters are commonly connected and grounded, and each base is connected to the output terminals OUTA and OUTB of the HDB line code circuit 73 and switched according to the outputs of the output terminals OUTA and OUTB. Both ends of the transistors Q1 and Q2 and the primary coil are connected to the collectors of the transistors Q1 and Q2, and a signal corresponding to the driving of the transistors Q1 and Q2 is transmitted to the transmission line 74. FIG. A transformer T1 that organically outputs to the connected secondary coil, and is connected in series between a resistor R1 and a capacitor C1 between a power supply voltage Vcc and ground, and the series connection node is a primary of the transformer T1. A first filter connected to a coil intermediate tap and the transformer T1 Secondary-side resistor (R2) and a capacitor (C2) between the two ends is made up of serially connected second filter. The HDB3 line code circuit 73 in the above configuration may use an integrated circuit that is already widely used.

FIG. 8 is a detailed view of the data receiving section 26 of FIG. 2, which includes a transformer T2 connected to the transmission line 76 and organically outputting the HDB3 line coded data to the secondary side, and from the transformer T2. AGC for controlling the output of the signal amplification and equalizer 81 by inputting the signal amplification and equalizer 81 for outputting a predetermined amplification and equalization signal, and the output of the signal amplification and equalizer 81. 83), a level output unit 85 for inputting the signal amplification and output of the equalizer 81 to discriminate an output level, and an output of the level detector 85 for inputting a clock for synchronizing a received signal. A clock regeneration circuit 87 for reproducing, a clock regeneration circuit 87 for reproducing a clock for synchronizing a received signal by inputting the output of the level detector 85, and a signal whose level has been determined by the level detector 85 To input HDB3 line to output playback data A line encoder 89 and a frame synchronization circuit 91 for detecting a frame synchronization signal FR from data output from the HDB3 line encoder 89. At this time, the HDB3 line encoder 89 can be used as a general-purpose integrated circuit.

Hereinafter, an operation of the branch type terminal connection apparatus according to the present invention will be described in detail with reference to the drawings.

The data receiving and drive circuit 21 of FIG. 2 is connected to a data port DP1 to a data port DP8 to which a data terminal is connected by using an RS-232C line receiver and a drive which are commonly used as shown in FIG. 5 and an RS-232C connector. The multiplexer / demultiplexer 24 is level-converted transmit and receive data. The branch device connecting portions 22 and 23 are constituted by an RS-232C line receiver and a drive integrated circuit and a 25-pin RS-232C connector as shown in FIG. DP17 and DP18... Transmit / receive data up to DP24 is provided to the MUX / DEMUX 24. At this time, the first, second branch device and the third, fourth branch device as shown in Fig. 3 data port (DPn) ... RS-232C level data output from (DPn + n) is converted into TTL level in each of the line receiving integrated circuits 32 and 35, and then RS-232C level in each of the line drivers 32 and 36 again. Is converted into the RS-232C connector 61 of the branch device connecting portion as shown in FIG. 6 through the RS-232C connector 39.

The transmission signal of the data port P input to the RS-232C connector 61 of FIG. 6 is converted into a TTL level through the line receivers LR9... LR17 of FIG. 6 and input to the multiplexing terminal of the MUX / DEMUX 24. . Therefore, the MUX / DEMUX 24 has a total of 24 data ports DP1, DP2... Which are transmitted / received through the data reception and drive circuit 21 and the branch device connections 22 and 23 configured as shown in FIG. Multiplexes and demultiplexes the DP23 and DP24 data at 2.048Mbps.

At this time, the data multiplexed by the MUX / DEMUX 24 and output to the line 71 is encoded by the HDB3 line in the data transmitter 25 configured as shown in FIG. 7 to be bipolar data and transmitted to the transmission line 74. Looking at the process to be transmitted with reference to Figure 7 as follows.

The multiplexed data from the MUX / DEMUX 24 at a transmission rate of 2.048 Mbps is input to the HDB3 line code circuit 73. The data input to the HDB3 line code circuit 73 is converted into the HDB3 line code recommended by the International Communications Advisory Committee (CCITT) and output. That is, the HDB3 line code circuit 73 converts the data transmitted to the logic X1 or X0 into three levels, i.e., a signal of a ++ signal and a signal of a -0 signal. When more than three "0" s are detected, the logic "1" is inserted and outputted forcibly so that the data of this state may not be transmitted.

The reason why the HDB3 line code circuit 73 detects when the input data is three consecutive with the logic '0' is to allow the receiving side to easily reproduce the received clock from the received data. This is to detect errors.

As described above, when the HDB3 line code circuit 73 encodes and outputs the output data to the output terminals OUTA and OUTB, the transistors Q1 and Q2 are switched, which causes the secondary side of the transformer T1 to be switched. HDB3 line code data is transmitted. At this time, the resistor R1, the capacitor C1, the resistor R2, and the capacitor C2 are used to smooth the waveform of the transmission signal.

Therefore, DP1... When data is transmitted from the DP24 to the host computer, the DP1, DP2..., ... are transmitted through the multiplexer / demultiplexer 24 of the first main unit of FIG. 1. When data of DP23 and DP24 are multiplexed and transmitted through a short-range transmission line (or telephone network) 74 or 76, they are demultiplexed in MUX / DEMUX in the second host device, and the respective terminal ports TP1, TP2,... It is inputted into TP23 and TP24. On the other hand, the DP1, DP2… When data is transmitted to DP23 and DP24, the terminal ports TP1, TP2... Data ports DP1 to TP23 and TP24 are available. Sent to DP24.

At this time, the HDB3 line coded data transmitted from the second host device is received by the first host device through the transmission line 76 through the transmission line 76, and the HDB3 line coded data is received by the data receiver 26 of FIG. The line code is input to the MUX / DEMUX 24. The operation thereof will be described with reference to FIG.

The signal received through the transmission line 76 is input to the signal amplifier and equalizer 81 through the transformer T2. At this time, it is an RC filter for removing high-frequency noise from the resistor R3 and capacitor C3 received signals connected to both ends of the primary coil of the transformer T3.

The signal amplifier and equalizer 81 compensates the difference in the loss of the transmission line according to the frequency of the transmission line so as to approximate the original signal, amplifies the signal to a predetermined level, and inputs it to the level detector 85. In this case, the signal amplification and the gain of the equalizer 81 are constantly controlled by the control of the AGC 83 according to the magnitude of the received signal.

The level detector 85 for inputting the amplified / equalized signal as described above discriminates the input signal as one of? +?? 0??-? Pulses and inputs them to the HDB3 line decoder 89 and the clock regenerator 87. Let's do it.

The clock regenerator 87 inputs a signal discriminated from the level detector 85 to regenerate a clock for synchronizing the received signal, and provides the reception clock RCLK to the MUX / DEMUX 24.

The HDB3 line decoder 89 decodes the signal determined by the ＂+＂, ＂0＂, ＂-＂ pulses to provide the playback data RD to the MUX / DEMUX 24.

The output of the HDB3 line decoder 89 is input by the frame synchronizing circuit 91 to output the frame synchronizing signal FS to the MUX / DEMUX 24 every frame.

At this time, the MUX / DEMUX 24, which has input the decoded reproduction data RD, the reception clock RCLK, and the frame synchronization signal FS as described above, demultiplexes the reproduction data input within the period of each synchronization signal FS. Port DP1, DP2... Transfer to DP23, DP24.

The shape of the serial data string formed by multiplexing in the multiplexer / demultiplexer 24 is shown in FIG.

Referring to FIG. 4, (a) shows a serial bit string repeated at 125 mu sec period. Where F1, F2... F8 represents a sub-frame consisting of 32 bits, which has 15.625 μsec (period (main frame 125 μsec ÷ subframe number 8), and the bit structure of the subframe F1 is as shown in (b), The bit structure of subframe F2 to subframe F8 is the same and its shape is as shown in (c) In (b), the initial eight bits S1, S2… S8 are synchronization data for mainframe synchronization of 125 μsec period. Synchronous data is the first 8 bits of every frame at 125μsec period, and the 24 bits such as P1, P2… P24 that follow are serial bits outputted from the data ports DP1, DP2… DP23, DP24, each representing 1 bit. c) shows the bit structure of F2-F8 with the same shape, where 8 bits indicated by ＂H＂ are always ＂1＂ data, and P1-P24 bits correspond to P1-P24 in (b), respectively. To data ports DP1 to DP24 It represents the continuous addition of the other data bits to be output.

In this case, the remaining subframes F2... The reason why all the initial 8 bits corresponding to S1-S8 of subframe F1 in F7 and F8 are all high is that the synchronization of the main frame input at 125 μsec period is the initial 8 bits S1 of the first subframe F1. This is because -S8 does not need to be used by satisfying the synchronization of the mainframe.

In this case, in the present invention, the subframe F2... Another reason for the initial 8 bits of F8 is to encode the data transmission on the HDB3 line. In the HDB3 line code, when +1 pulses are continued, the + pulse pulses and the-pulse pulses are alternately output, so that the clock reproduction becomes easy on the receiving side. Thus, each subframe F2... The reason why the initial 8 bits are transmitted at F8 at F8 is to facilitate clock regeneration at the receiving end.

That is, as described in FIGS. 4B and 4C, the 24 data ports DP1, DP2... It can be seen that 1 bit per subframe is assigned to the same position with respect to DP23 and DP24.

This is done by sampling the serial data output from each data port at regular intervals once every 15.625µsec periods. P1 of F8... This is the same as sending to P24.

Thus, each data port DP1... The electrical signals (data) of the DP24 can be multiplexed almost identically and transmitted to the other side. Each data port DP1... Since the electric signal of the DP24 can be transmitted, a transceiver can be configured without a buffer for collecting and transmitting data.

As described above, the present invention can reduce the size of the main apparatus and configure an economical system according to the scale by expanding the data terminals in predetermined port units, and can be installed by separating the main apparatus and the branch apparatus up to several dozens of terminals in one place. It is possible to eliminate the disadvantages of messy indoor offices or factories due to the concentration of installation lines, and can meet the demands in a short time without installing additional transmission lines up to a certain number of connected data terminals. (Dummy Terminal) has the advantage of constructing a very economical and maintainable system than the existing method (analog model, LAN, 1: 1 connection, etc.) in the business environment predominantly.

Claims (2)

In the premises branch-type terminal access device having a plurality of data terminals and a host computer having a predetermined number of terminal modes to perform short-range data transmission between the plurality of data terminals and the host computer, grouped by a predetermined number Branch device means consisting of a line receiving and drive circuit for receiving and line driving data transmitted and received from the data port to serve as an interface device for coupling or separating the grouped data ports to the transmission line; Multiplexing or demultiplexing the data transmitted / received from a predetermined number of data ports directly connected to the transmission / reception data of each data port grouped in a predetermined unit via a device means, and then transmitted and received to the terminal port of the host computer. Above each A branch type terminal access device comprising a main device means for performing a data transfer function between a data port and each terminal port. A line receiving and drive path 21 for receiving and driving data transmitted and received from a predetermined number of data ports to which a main device means is directly connected, and grouped by a predetermined number through the branch device means. Branch device connection parts 22 and 23 which perform a connection function to the data ports, and transmit / receive data corresponding to each data port of the line receiving and drive circuit 21 and the branch device connection parts 22 and 23 are stored. And a multiplexer / demultiplexer (24) for multiplexing and demultiplexing, and a data transmitter (25) and a data receiver (26) connected to the multiplexer / demultiplexer (24) and a transmission line for transmitting and receiving data. .

Images