KR890011274A - Data transmission detector - Google Patents

Data transmission detector Download PDF

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Publication number
KR890011274A
KR890011274A KR1019870015310A KR870015310A KR890011274A KR 890011274 A KR890011274 A KR 890011274A KR 1019870015310 A KR1019870015310 A KR 1019870015310A KR 870015310 A KR870015310 A KR 870015310A KR 890011274 A KR890011274 A KR 890011274A
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KR
South Korea
Prior art keywords
signal
address
bus
input
enable signal
Prior art date
Application number
KR1019870015310A
Other languages
Korean (ko)
Inventor
오범석
이창섭
Original Assignee
안시환
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 안시환, 삼성전자 주식회사 filed Critical 안시환
Priority to KR1019870015310A priority Critical patent/KR890011274A/en
Publication of KR890011274A publication Critical patent/KR890011274A/en

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Abstract

내용 없음No content

Description

데이타 전송 감지장치Data transmission detector

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 장치도.2 shows an apparatus according to the invention.

Claims (1)

RS-232C컨넥터, RS-232C 모니터와 키보를 구비한 전송감지장치에 있어서, 어드레스버스(27), 데이타버스(28), 컨트롤버스(29)의 신호를 입출력하고 인더럽트신호(30)를 입력해 전체시스템을 총괄적으로 제어하는 CPU(21)와, 상기 CPU(21)에서 입력되는 어드레스 신호에 따라 메모리선택 인에이블 신호를 만들어내는 어드레스디코더(22)와, 상기 어드레스디코더(22)의 메모리 선택 인에이블 신호에 따라 제작자에 의해 장된 흐름도 제어신호를 상기 어드레스버스(27), 데이타버스(28) 및 콘트롤버스(29)로 입출력하는 롬(23)과, 상기 어드레스디코드(22)의 메모리 선택 인에이블 신호에 따라 어드레스버스(27), 데이타버스(28) 및 컨트롤 버스(29)의 입출력신호를 버퍼링 하는 램(24)과, 상기 어드레스디코더(22)의 메모리 선택 인에이블 신호에 따라 입력단자(Tx)로 입혁되는 신호에 의해 RS-232C편을 모니터링 하여 다른 두단자를 링크레벨의 실체 신호를 출력하고 키입력 신호를 받는 Z80 PIO 및 SIO(25)와 상기 Z-80 PIO,SIO(25)에서 출력하는 링크레벨의 실체신호를 사용자가 감시할수 있도록 디스플레이 시키는 디스플레이 모듈(26)과, 상기 인터럽트선(30)에 구동력을 주는 풀업저항(R9)으로 구성됨을 특징으로하는 장치.In a transmission sensing device having an RS-232C connector, an RS-232C monitor, and a keyboard, input / output signals of the address bus 27, the data bus 28, and the control bus 29, and the interrupt signal 30 is inputted. A CPU 21 which collectively controls the entire system, an address decoder 22 for generating a memory selection enable signal in accordance with an address signal input from the CPU 21, and a memory of the address decoder 22; ROM 23 for inputting / outputting a flow chart control signal stored by the manufacturer according to the selection enable signal to the address bus 27, the data bus 28 and the control bus 29, and memory selection of the address decode 22. RAM 24 buffering input / output signals of the address bus 27, data bus 28, and control bus 29 according to the enable signal, and input terminals according to the memory selection enable signal of the address decoder 22. Signal transformed into (Tx) By monitoring the RS-232C side, the other two terminals output the link level entity signal and receive the key input signal, and the link level entity output from the Z80 PIO and SIO 25 and the Z-80 PIO and SIO 25. And a display module (26) for displaying signals for the user to monitor and a pull-up resistor (R9) for driving the interrupt line (30). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870015310A 1987-12-30 1987-12-30 Data transmission detector KR890011274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870015310A KR890011274A (en) 1987-12-30 1987-12-30 Data transmission detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870015310A KR890011274A (en) 1987-12-30 1987-12-30 Data transmission detector

Publications (1)

Publication Number Publication Date
KR890011274A true KR890011274A (en) 1989-08-14

Family

ID=68807893

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870015310A KR890011274A (en) 1987-12-30 1987-12-30 Data transmission detector

Country Status (1)

Country Link
KR (1) KR890011274A (en)

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