KR890008848A - High Voltage Follower and Sensing Circuit - Google Patents

High Voltage Follower and Sensing Circuit Download PDF

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Publication number
KR890008848A
KR890008848A KR870013611A KR870013611A KR890008848A KR 890008848 A KR890008848 A KR 890008848A KR 870013611 A KR870013611 A KR 870013611A KR 870013611 A KR870013611 A KR 870013611A KR 890008848 A KR890008848 A KR 890008848A
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KR
South Korea
Prior art keywords
voltage
output
supply terminal
node
voltage supply
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KR870013611A
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Korean (ko)
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KR900006165B1 (en
Inventor
임영호
도재영
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강진구
삼성반도체통신 주식회사
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Priority to KR1019870013611A priority Critical patent/KR900006165B1/en
Priority to JP63299760A priority patent/JPH073441B2/en
Publication of KR890008848A publication Critical patent/KR890008848A/en
Application granted granted Critical
Publication of KR900006165B1 publication Critical patent/KR900006165B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

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  • Measurement Of Current Or Voltage (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음No content

Description

고전압 폴로워 및 감지회로High Voltage Follower and Sensing Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 실시예의 회로도.2 is a circuit diagram of an embodiment according to the present invention.

제3도는 입력전압에 따라 발생되는 제1 및 제2출력전압의 변화곡선도.3 is a change curve diagram of first and second output voltages generated according to an input voltage.

제4도는 입력전압의 시간적 변화에 따른 제1 및 제2출력전압의 변화곡선도.4 is a change curve of the first and second output voltages according to the temporal change of the input voltage.

Claims (6)

반도체 장치에 있어서, 외부인가 전압을 입력하는 입력단자(100)와, 제어노오드(60)와, 출력노오드(70)와, 상기 입력단자(100)와 제어노오드(60)사이에 접속되는 상기 입력전압을 강하시키는 전압 강하수단(10)과, 제1바이어스 전압을 제어노오드에 공급하는 제1전압 공급단자(200)와, 제2바이어스 전압이 공급되는 제2전압 공급단자(300)와, 제어노오드(60)와 출력노오드(70)사이의 도전 통로를 제공하기 위한 제어노오드(60)의 전압에 응답하는 스위칭 수단(30)과, 제3바이으서 전압이 공급되는 제3전압 공급단자(400)와, 상기 전압 공급단자(400)와, 출력노오드(70)사이에 접속되어 항상 동일한 전류를 출력노오드(70)에 공급하는 정전류수단(40)과, 상기 출력노오드(70)에 접속되어 상기 노오드(70)의 전압이 소정 전압이상일때 소정 논리레벨을 발생하는 제2출력수단(50)과, 상기 출력노오드 (70) 에 접속된 제1출력단자(700)와, 상기 제2출력수단(50)에 접속된 제1출력단자(600)를 구비하여 외부인가 전압을 폴로워하는 제1출력전압과 제1출력전압에 따라 소정 논리레벨상태를 유지하는 제2출력전압을 각각 제1 및 제2출력단자(600)(700)로 발생함을 특징으로 하는 고전압 폴로워 및 감지회로.In a semiconductor device, an input terminal 100 for inputting an externally applied voltage, a control node 60, an output node 70, and a connection between the input terminal 100 and the control node 60 are connected. A voltage drop means 10 for dropping the input voltage, a first voltage supply terminal 200 for supplying a first bias voltage to a control node, and a second voltage supply terminal 300 for supplying a second bias voltage; And a switching means 30 responsive to the voltage of the control node 60 for providing a conductive passage between the control node 60 and the output node 70, A constant current means 40 connected between the third voltage supply terminal 400, the voltage supply terminal 400, and the output node 70 to always supply the same current to the output node 70, and Second output means 50 connected to an output node 70 for generating a predetermined logic level when the voltage of the node 70 is equal to or greater than a predetermined voltage; A first output terminal having a first output terminal 700 connected to the output node 70 and a first output terminal 600 connected to the second output means 50 to follow an externally applied voltage; And a second output voltage to the first and second output terminals (600) (700) for maintaining a predetermined logic level state according to the voltage and the first output voltage, respectively. 제1항에 있어서, 스위칭 수단(30)이 제어노오드(60)와 출력노오드(70)사이에 접속된 채널과 제2전압 공급단자(300)에 접속된 게이트를 가지며 기판(또는 웰)이 제어노오드(60)에 접속된 P채널모오스 트랜지스터로 구성함을 특징으로 하는 회로.2. The substrate (or well) of claim 1, wherein the switching means (30) has a channel connected between the control node (60) and the output node (70) and a gate connected to the second voltage supply terminal (300). And a P-channel MOS transistor connected to the control node (60). 제2항에 있어서, 전압 강하수단(50)이 직렬접속된 게이트가 드레인에 접속된 다수개의 N채널 인헨스멘트 모오스트랜지스터들(11)(13)(15)로 구성되어 다수개의 N채널 인헨스맨트 모오스트랜지스터(11)(13)(15)의 드레쉬 홀드전압의 합만큼 입력전압을 전압강하 시킴을 특징으로 하는 회로.3. A plurality of N-channel enhancements as set forth in claim 2, wherein the voltage drop means (50) is composed of a plurality of N-channel enhancement mother transistors (11) (13) and (15) having a gate connected in series. A circuit characterized by dropping the input voltage by the sum of the threshold hold voltages of the mant MOS transistors (11) (13) (15). 제2항에 있어서, 정전류 수단(40)이 출력노오드 (70)와 제3전압 공급단자(400)사이에 접속된 채널과 제3전압 공급단자(400)에 게이트가 접속된 디플리션 모오스 트랜지스터로 구성함을 특징으로 하는 회로.The depletion mode according to claim 2, wherein the constant current means 40 has a channel connected between the output node 70 and the third voltage supply terminal 400 and a gate connected to the third voltage supply terminal 400. A circuit comprising a transistor. 제2항에 있어서, 제2출력수단(50)이 출력노오드(70)와 제2출력단자(600)사이에 직렬로 접속된 짝수개의 반전게이트로 구성됨을 특징으로 하는 회로.3. A circuit according to claim 2, characterized in that the second output means (50) consists of an even number of inverted gates connected in series between the output node (70) and the second output terminal (600). 제2항에 있어서, 제1전압 공급단자(200)에 공급되는 전압은 제1전압 공급단자(200)와 제2전압 공급단자(300)사이에 채널이 접속되고 게이트가 제2전압 공급단자(300)에 접속된 N채널 인헨스맨트 모오스트랜지스터(20)의 드레쉬 홀드 전압보다 작은 전압임을 특징으로 하는 회로.The voltage supplied to the first voltage supply terminal 200 is a channel connected between the first voltage supply terminal 200 and the second voltage supply terminal 300, the gate is connected to the second voltage supply terminal ( And a voltage smaller than the threshold hold voltage of the N-channel enhancement MOS transistor (20) connected to (300). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870013611A 1987-11-30 1987-11-30 High-voltage follow and sensing circuit KR900006165B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019870013611A KR900006165B1 (en) 1987-11-30 1987-11-30 High-voltage follow and sensing circuit
JP63299760A JPH073441B2 (en) 1987-11-30 1988-11-29 High voltage follower and sensing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870013611A KR900006165B1 (en) 1987-11-30 1987-11-30 High-voltage follow and sensing circuit

Publications (2)

Publication Number Publication Date
KR890008848A true KR890008848A (en) 1989-07-12
KR900006165B1 KR900006165B1 (en) 1990-08-24

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KR1019870013611A KR900006165B1 (en) 1987-11-30 1987-11-30 High-voltage follow and sensing circuit

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JP (1) JPH073441B2 (en)
KR (1) KR900006165B1 (en)

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* Cited by examiner, † Cited by third party
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JP6371191B2 (en) * 2014-10-17 2018-08-08 旭化成エレクトロニクス株式会社 IC chip

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KR900006165B1 (en) 1990-08-24
JPH022964A (en) 1990-01-08
JPH073441B2 (en) 1995-01-18

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