KR890006185Y1 - 40x40 font devices without memory waste - Google Patents

Abstract

No content.

Description

40 × 40 font device without wasting memory

Fig. 1 (a) and Fig. 1 (b) are conventional 40 × 40 font address structure diagrams.

2 is a structural diagram of a conventional image generating apparatus.

3 is an address generation circuit diagram in FIG.

Figure 4 is a detailed view of the scan address generation circuit of the present invention.

5 (a) and 5 (b) is a 40 × 40 font address structure diagram according to the present invention.

6 is a structural diagram of an image generating apparatus of the present invention.

* Explanation of symbols for main parts of the drawings

1,17 page buffer memory 2,18 character address fetch circuit

3,19: FontROM 4: Vertical scan address generating circuit

5: Horizontal scan address generating circuit CK, 6, 21: Dot clock

20: standard address generation circuit 7,22: shift register

9: System Databus 8,23: Video Data

10114: Latch 11: Adder 1

12: Adder 2 13: Clark

14,311: counter 15: inverter

16: NAND gate Hsync: Passive signal

111: CPU 112: bus control logic

113: memory 211: vertical scan address counter

312: horizontal scan address counter 212,313: reset circuit

The present invention relates to an image generating apparatus of a laser printer, and more particularly, to a scan address generation circuit designed to avoid wasting memory when the font font size is 40 × 40 font in an image generating apparatus that generates characters. .

In the conventional technical configuration of the image generating apparatus, as shown in FIG. 2, the character address fetch circuit 2 is connected to the page buffer memory 1, and the font ROM 3 is connected to the character address fetch circuit 2. As shown in FIG. ), A vertical scan address generation circuit 4, a horizontal scan address generation circuit 5, and a shift register 7 are connected to the font ROM 3, and a dot clock signal 6 is connected to the shift register 7. The structure of the font addresses A16 to A0 for reading fonts from the font ROM 3 containing 40x40 fonts is applied as shown in Fig. 1 (a). As shown in Fig. 2, the letter addresses A16 to A9 for selecting fonts are the upper addresses, and the vertical scan addresses A8 to A3 and the horizontal scan addresses A2 to A0 are lower addresses.

At this time, the circuits generating the letter addresses A16 to A9, the vertical scan addresses A8 to A3, and the horizontal scan addresses A2 to A0 are shown in FIG. 3, and the circuits for generating the letter addresses A16 to A19 are shown in FIG. The CPU 111 is connected to the bus control structure 112, the bus control structure 112 is connected to the memory 113 and at the same time through the latch 114 is configured to output the 8-bit letter address (A16 ~ A9) The 6-bit vertical scan address (A8 to A3) generating circuit outputs the vertical scan addresses (A8 to A3) from the vertical scan address counter (211) receiving the horizontal synchronization signal (Hsync) and outputs the vertical scan addresses (A8 to A3). A3) is connected to the reset terminal R of the vertical scan address counter 211 via the reset circuit 212, and a circuit for generating the horizontal scan addresses A2 to A0 is provided with a dot clock CK. The counter 311 outputs the 3-bit horizontal scan addresses A2 to A0 via the horizontal span address counter 312. The horizontal scan addresses A2 to A0 output from the flat scan address counter 312 output 3-bit horizontal scan addresses A2 to A0 via the reset circuit 313, and are output from the horizontal scan address counter 312. The horizontal scan addresses A2 to A0 are connected to the reset terminal R of the horizontal scan address counter 312 via the reset circuit 313. The addresses A16 to A0 generated in the circuit as described above are When connected to the address terminal of the font ROM 3, the upper and lower addresses become.

That is, the letter addresses A16 to A9 output from the letter address fetch circuit 2 are connected to the address terminals A16 to A9 of the font ROM 3, and the vertical scan addresses A8 to A3 are the font ROM 3; When connected to the address terminals A8 to A3 and the horizontal scan addresses A2 to A0 are connected to the address terminals A2 to A0 of the font ROM 3, the letter address becomes the upper address and the vertical scan address and the horizontal scan The address is a well-known technique to be a lower address, and the operation description of the above described technical configuration will be described with reference to FIG. 1 and FIG. 2 as follows.

The character address of one page of the character to be imaged is in the page buffer memory 1, the character address fetch circuit 2 calls the character address in the page buffer to form the upper address of the font address, and the scan address is vertical. The scan address and the horizontal scan address are made from separate counter circuits as shown in FIG. 3, which form a subaddress of the font address to read the corresponding font data.

In this case, the page buffer memory 1 of FIG. 2 is a memory in which the CPU stores a letter address of a character to be printed (usually ASCII value as it is). In general, the CPU accesses and accesses the character address fetching circuit ( 2) also accesses this, so the dual port memory or the busple buffer is used for control. In this case, since the data is in parallel, the dot clock 6 is synchronized by the shift register 7. And converts it to serial video data.

However, in the above font address, when the font size is 32 × 32 or 64 × 64, there is no waste of memory. However, when the font size is 40 × 40, the horizontal address is 5, 6, In the case of 7 and the vertical address up to 40-63, the address is not used. In this case, the memory occupies 64 × 64 fonts and uses 40 × 40 fonts, resulting in 60.9% of memory waste.

That is, the structure of the font ROM 3 is as shown in FIG. 1 (b), and the horizontal scan address (HSA) indicating the number of times in the horizontal direction of the font and the vertical indicating the number of times in the vertical direction. The scan address VSA is configured as shown in the first (a) and the first (b) diagrams. The HSA and the VSA are signals generated by separate counter logics.

In the case of 40 × 40 font, as shown in Figure 1 (b), after accessing address 0,1,2,3,4, the actual address of the sixth byte, that is, the first byte of the second column of the font is set to "1". ", HSA is" 0 ", not 5, but 8

That is, three bytes (24 bits) of addresses 5, 6, and 7 are actually areas that are not used even though they exist as areas of the font ROM on the address.

Similarly, 13, 14, 15, 21, 22, 23, etc. are not used, and eventually 40 × 64 memory is needed to access 40 × 40 fonts.

However, since 6 bits are required to represent the vertical address from 0 to 39, it must always represent 0 to 39, so the next character from 40 cannot be inserted, so the area occupied in memory without being used until 40 to 63 (24 bits). Becomes

Eventually, 64x64 memory is required, but 40x40 fonts waste memory space.

Therefore, the present invention is constructed as shown in FIGS. 4 and 5 to eliminate the waste of the memory.

Vertical scan in an image generating device comprising a page buffer memory (1), a character address fetch circuit (2), a font ROM (3), a vertical scan address (4), a horizontal scan address generation circuit (5), and a shift register (7) Instead of the address generating circuit 4 and the horizontal scan address generating circuit 5, a latch 10, an adder 1 11, an adder 2 12, a counter 13, an inverter 15, and a NAND gate ( The above-described technical configuration is described in more detail as an image generating apparatus without a memory waste using a 40 × 40 font, which is configured by connecting a scan address generation circuit 20 composed of 16).

In FIG. 6, the character address fetch circuit 18 is connected to the page buffer memory 17, the font ROM 19 is connected to the character address fetch circuit 18, and the scan address generation circuit 20 is connected to the font ROM 19. ), The font ROM 19 is configured as shown in FIG. 4 by the scan address generation circuit in the configuration in which the video data 23 is output from the shift register 22 by connecting the shift register 22. As shown in FIG.

That is, the system data bus 9 is connected to the input terminal of the latch 10, and the outputs Q7 to Q0 of the latch 10 are applied to the adder 1 (ADDER1) 11 and the adder 2 (ADDER2) 12, respectively. And when the clock 13 is synchronized with the counter 14, the outputs Q0, Q1 and Q2 of the counter 14 are connected to the input of the adder 2 12, and at the same time The output Q0, the inverted output Q1 and the output Q2 are applied to the NAND gate 16, and the output terminal of the NAND gate 16 is an enable terminal (a chip of the counter 14). ) And the carry-in (Cin) of Adder 1 (11) is connected to the carry-out (COUT) of Adder 2 (12).

The output of adder 1 (11) and the output of adder 2 (12) form a scan address.

Referring to the description of the operation of the present invention according to the fourth, fifth, and sixth as follows.

The central processing unit (CPU) knows by counting the horizontal synchronization signal the number of lines currently to be scanned in the vertical direction in the font and latches the basic address values in the data latch 10 before scanning starts. .

The basic address value is a value of the first column in FIG. 5 (b) and increases in the order of 0, 5, 10, ... 195 as the number of scans increases from 1 to 40. FIG.

The counter 14 continuously cycles the data in the order of 0, 1, 2, 3, 4, 0, 1, 2, 3, and 4 with the clock 13 changing.

The output of this counter 14 is added by the latch 10 outputs (Q3 to Q0) and adder 2 (12) and adds another adder 1 (11) and adder 2 to handle carry (CARRY). The output of (12) becomes a scan address as the sum of the counter outputs, indicating how many bytes to access the base address and the font, which are the outputs of the latch 10, horizontally.

The scan address generation circuit 20 is described in FIG. 5 as follows.

The character address of the character to be printed is in the page buffer memory 17, and the character address fetch circuit 18 creates the lower address of the font address as shown in the fourth (a), and the scan address generating circuit (above the font address). 20) and the data accessed by the font address is synchronized with the dot clock 21 in the shift register 22 so that the parallel data is converted into serial data, and the video data 23 is generated as an output. Unlike the conventional apparatus in which an address is divided into a vertical scan address 4 and a horizontal scan address generation circuit 5, the address is generated in the scan address generation circuit 20 at one time so that the scan address occupies the upper part and the letter address is the lower part. It takes wealth.

Therefore, as shown in FIG. 4 (b), all the standard address values in the font are used from scan addresses 0 to 199 and occupy the upper part of the font address. Therefore, when the font size is 40 × 40 font, 64 × 64 60.9% of the memory is wasted because the memory of the font is used, but the scan address generation circuit 20 provides the advantage that no memory is wasted.

Claims (2)

To an image generating device comprising a page buffer memory 11, a character address fetch circuit 2, a font ROM 3, a vertical scan address generation circuit 4, a horizontal scan address generation circuit 5, and a shift register 7. In place of the vertical scan address generation circuit 4 and the horizontal scan address generation circuit 5, the latch 10, the adder 1 (11), the adder 2 (12), the counter 14, the inverter 15, and the NAND gate ( 16 x 40 font device, characterized in that configured by connecting the scan address generation circuit 20 configured by connecting to. The 40 x 40 font device according to claim 1, wherein the address of the font is configured as an upper byte of a scan address and a lower address of a character address.