KR890004120B1 - Detecting circuit of digital pll stade - Google Patents

Detecting circuit of digital pll stade

Info

Publication number
KR890004120B1
KR890004120B1 KR8706583A KR870006583A KR890004120B1 KR 890004120 B1 KR890004120 B1 KR 890004120B1 KR 8706583 A KR8706583 A KR 8706583A KR 870006583 A KR870006583 A KR 870006583A KR 890004120 B1 KR890004120 B1 KR 890004120B1
Authority
KR
South Korea
Prior art keywords
input terminal
stade
detecting circuit
pll
digital pll
Prior art date
Application number
KR8706583A
Other languages
Korean (ko)
Other versions
KR890001294A (en
Inventor
Myong-Sik Ham
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to KR8706583A priority Critical patent/KR890004120B1/en
Publication of KR890001294A publication Critical patent/KR890001294A/en
Application granted granted Critical
Publication of KR890004120B1 publication Critical patent/KR890004120B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The circuit is for preventing the error detection of the PLL state caused by a control voltage variation of a voltage controlled oscillator. The oscillating output of the VCO (13) is provided to a data input terminal (D) of a flip-flop (21) through a divider (14) and a reference signal is provided to a clock input terminal (CK). The output terminal (Q) of a D flip-flop (21) is connected to an input terminal (13) of a retriggerable one-shot multivirator (22) to provide logical high or low signal according to the locking state of the PLL.
KR8706583A 1987-06-27 1987-06-27 Detecting circuit of digital pll stade KR890004120B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR8706583A KR890004120B1 (en) 1987-06-27 1987-06-27 Detecting circuit of digital pll stade

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR8706583A KR890004120B1 (en) 1987-06-27 1987-06-27 Detecting circuit of digital pll stade

Publications (2)

Publication Number Publication Date
KR890001294A KR890001294A (en) 1989-03-20
KR890004120B1 true KR890004120B1 (en) 1989-10-20

Family

ID=19262410

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8706583A KR890004120B1 (en) 1987-06-27 1987-06-27 Detecting circuit of digital pll stade

Country Status (1)

Country Link
KR (1) KR890004120B1 (en)

Also Published As

Publication number Publication date
KR890001294A (en) 1989-03-20

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Payment date: 20060920

Year of fee payment: 18

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