KR890004074Y1 - Invertor control apparatus - Google Patents

Abstract

No content.

Description

Inverter control unit

1 is a block diagram according to the present invention.

2 is a detailed circuit diagram of FIG. 1 according to the present invention.

* Explanation of symbols for main parts of the drawings

10 latch portion 20 disturbance detection unit

30: logic selector 40: micom unit

50: input / output section 60: reset section

The present invention relates to an inverter (Inverter), in particular, when the disturbance (overvoltage, overcurrent, overvoltage, under-voltage, error) occurs during the normal operation of the inverter to display by the processing by the microcomputer to allow the normal operation by quick operation will be.

In general, an inverter is a device that receives commercial AC power, converts it to DC, and then converts it back.

In this case, it is impossible to control the induction motor because AC power of 110V or 220V is 60Hz.

Therefore, for this purpose, if the output frequency is changed from 0 to 320HZ by converting to DC again and then back to AC, the input power frequency of the induction motor is changed, thereby enabling the control of the induction motor.

However, when disturbances such as over current (OC: Over Current), over voltage (OV), under Vltage (IV), and error (E: Error) occur, the operator directly operates the motor. The operation status was checked from time to time and treated.

As a result, when the instability condition occurred during the operation of the motor, it was not easy to detect the cause of the problem, which resulted in delay in treatment time or inconvenience in operation.

Therefore, the object of the present invention is to detect the disturbance when the occurrence of the prompt display by the treatment of the microcomputer to deal with the disturbance in accordance with the inverter to allow the normal operation can be quickly again.

Another object of the present invention is to provide a circuit that can increase the port expansion rate by using a dual port by combining the disturbance detection and key input.

The present invention for performing the above object is a latch unit for controlling the operation required for the initial normal operation in the inverter, and a disturbance detection that can detect a state signal when a disturbance such as undervoltage, overvoltage, overcurrent and error occurs A logic selector capable of selectively outputting a signal according to the type of disturbance and a key in a steady state during operation by logically inputting the input of the disturbance detection unit and the latch unit, and an output signal of the latch unit and the logic selector unit. Receive and compare the stored setting data and output the display data according to the type of disturbance to control the normal operation, and display the type of disturbance checked by the micom part for easy understanding by the user. Input / output section capable of inputting a signal, and when a disturbance occurs, After turning on the reset switch to when a steady state is characterized in that it constituted by a reset control to return to the microprocessor portion normal routine.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram according to the present invention, and a latch unit 10 for controlling an operation required for initial normal operation, and a disturbance detection capable of detecting a status signal when disturbances such as undervoltage, overvoltage, overcurrent, and error occur. Logic selection unit 30 for selectively outputting a key and a signal according to the type of disturbance during operation by logicalizing the inputs of the unit 20 and the disturbance detection unit 20 and the latch unit 10. And a micom unit 40 for receiving the output signals of the latch unit 10 and the logic selecting unit 30 and comparing the stored setting data to output display data according to the type of disturbance and controlling the formal operation. The mouth that can display the kind of disturbances checked by the microcomputer 40 so as to be easily understood by the user to input a key according to the normal operation. The micom unit 40 returns to the normal routine when the reset switch is turned on when the output unit 50 and the relay are driven in accordance with the output of the latch unit 10 when the disturbance occurs, and the switch is turned to the normal state after the disturbance treatment. It consists of the reset part 60 which controls to return.

Therefore, the embodiment will be described based on the above-described configuration. When the system is turned on and the input / output unit 50 inputs the normal operation key through the input keyboard and latches the normal state in the latch unit 10, the INT of the micom unit is Since the interrupt is not interrupted in the HIGH state, the microcomputer unit 40 runs the normal routine and enters. The key input of the output unit 50 is accepted through the logic selecting unit 30 and performs normal operation. At this time, when disturbance occurs during normal operation, the disturbance detection unit 20 detects and converts the output of the latch unit 10 to a low state.

Subsequently, the switch state of the reset unit 60 is controlled and the microcom unit 40 is interrupted, and the logic selector 30 selects the signal generated by the disturbance detection unit 20 and inputs the signal to the micom unit 40. .

Accordingly, the microcomputer 40 checks the mouth according to the type of disturbance. Predetermined display is performed through the display device of the output unit 50 so that an operator can quickly process the disturbance.

When the disturbance is eliminated and the initial reset switch of the reset unit 60 is pressed, it is operated in the normal state again.

FIG. 2 is a specific circuit diagram of FIG. 1 according to the present invention. The resistor R ₆ and the capacitor C ₁ are input to the NAND gate NA ₁ with the power supply Vcc input, and the NAND gate NA _{The portion} formed by the output terminal of ₁ ) as the input of the NAND gate NA ₂ corresponds to the latch portion 10, and constitutes the diodes D _1- D ₄ from the power supply Vcc through the resistor R ₁ . The photocoupler (PT ₁ -PT ₄ ) connected through the resistor (R ₅ ) corresponds to the disturbance detection unit 20, the output of the latch unit 10 passes through the inversion gate (N ₁ ) disturbance detection unit A portion configured to be input to the AND gates A ₁ -A ₈ like the output signal of 20 corresponds to the logic selector 30, and the latch 10 and the logic selector 30 The central processing unit (CPU) configured to receive an output and process the program corresponds to the microcomputer unit 40, and displays a predetermined display on the type of disturbance checked by the microcomputer unit 40. A portion composed of a keyboard (KEB) for inputting a state of a key required for operation by the ray (CRT) and the micom unit 40 and the logic selection unit 30 corresponds to the input / output unit 50, the latch The output signal of the unit 10 is applied to the base of the transistor Q ₅ through the resistor R ₇ and the diode D ₁ and the relay Ry are connected in parallel to the collector of the transistor Q ₅ , and the relay A portion of the reset switch RST and the photocoupler PT ₅ corresponding to Ry corresponds to the reset unit 60.

Therefore, when the specific embodiment of the present invention will be described in detail, the power supply (Vcc) through the resistor (R ₆ ) at the initial power-up is in the "low" state until the charge of the capacitor (C ₁ ) of the NAND gate (NA ₁ ) Put the output "high" and this output is again inputted to NAND gate (NA ₂ ), which makes the output "low", which in turn becomes one input of NAND gate (NA ₁ ) so that capacitor (C ₁ ) Even when charged and changed from a "low" state to a "high", the output of the NAND gate NA ₁ remains in a "high" state.

Therefore, the interrupt stage INT of the CPU does not enter the interrupt routine and follows the normal flow.

In addition, since the "high" signal is applied to the AND gates A ₁ , A ₃ , A ₅ , and A ₇ to enable the gate, the key input according to the normal operation is received from the keyboard KEB and the OR gate (OR ₁ -OR). ₄ ) Input to the central processing unit (CPU) through the operation is performed under normal conditions.

When a disturbance occurs during operation i.e., lack jeonap, over-voltage, ilbyeok of the NAND gate (NA ₂₎ when one is on the conduction of current, such as an error occurs when the photo coupler (PT ₁ -PT ₄₎ is converted to a "low" since the output of the NAND gate (NA ₂₎ is a "high" input to the NAND gate (NA ₁₎ the output of the NAND gate (NA ₁₎ is a "low".

At this time, the signal interrupts the CPU to execute the interrupt routine. Also, the "high" of the NAND gate (NA ₂ ) output turns on the transistor (Q ₅ ) to drive the relay (Ry). The contact of (Ry) is corrected toward the reset switch.

On the other hand, since the "low" of the NAND gate NA ₁ is inverted at the inverting gate N ₁ and becomes "high", the gate is enabled when it is input to the AND gates A ₂ , A ₄ , A ₆ , and A ₈ . and also "low" is directly aND gate _{(a 1, a 3, a} 5, a 7) because is the disabling said gate _{(a 1, a 3, a} 5, a 7) of the normal condition when the photo coupler Disturbance signal detected at (PT ₁ -PT ₄ ) is inputted to CPU by O gate (OP ₁ -OP ₄ ) through AND gate (A ₂ , A ₄ , A ₆ , A ₈ ) do.

Therefore, the central processing unit (CPU) checks this and displays it according to the type of disturbance through the display (CRT). In case of over current, "OC" is displayed, over voltage range "OV" is displayed, and in case of under voltage, "UV" is displayed. In case of an error, "E" is displayed to request the operator to take action.

Here, when the operator takes care of the disturbance and presses the reset switch RST, the photocoupler PT ₅ is driven to reset the central processing unit (CPU).

Therefore, since all the disturbances have been processed at this time, the input of the NAND gate NA ₂ is “high”, and the output of the NAND gate NA ₂ is converted to “low”. At this time, since the normal power is supplied, the output of the NAND gate NA ₁ becomes "high", and the normal operation as described above is performed again from the beginning.

As described above, the occurrence of disturbance during the operation of the inverter is displayed by the processing of the microcomputer, so that the treatment can be performed quickly, and the use of the logic gate combination can further expand the use port for other purposes.

Claims (1)

In the inverter, a latch unit 10 for controlling an operation required for initial normal operation, a disturbance detection unit 20 capable of detecting a status signal when a disturbance such as undervoltage, overvoltage current, and error occurs, and the disturbance detection A logic selector 30 capable of selectively outputting a steady state key with a signal according to the type of disturbance during operation by logically inputting the inputs of the unit 20 and the latch unit 10, and the latch unit 10 and A microcomputer 40 for controlling normal operation and outputting display data according to the type of disturbance by comparing and processing the stored setting data by receiving the output signal of the logic selector 30, and the microcom unit 40 is checked. Display the type of disturbance so that the user can easily understand and input the key according to the normal operation, and when the disturbance occurs, the reset switch of the relay is driven in accordance with the output of the latch unit 10 Normal condition after treatment If the set switch-on drive control circuit, characterized in that the microcomputer unit 40 is composed of a reset section 60 for controlling to return to a normal routine.