CN218162422U

CN218162422U - Controllable safe switching on and shutting down circuit of chronogenesis

Info

Publication number: CN218162422U
Application number: CN202221966736.0U
Authority: CN
Inventors: 郑春雨; 任智强; 王剑峰
Original assignee: Jiangsu Wuyou Microinvasive Medical Technology Co ltd
Current assignee: Jiangsu Wuyou Microinvasive Medical Technology Co ltd
Priority date: 2022-07-28
Filing date: 2022-07-28
Publication date: 2022-12-27
Anticipated expiration: 2032-07-28

Abstract

A time sequence controllable safe on-off circuit comprises a key input unit, a key detection unit, a logic control unit, a chip control unit and a power supply switch unit, realizes stable on-off and safe off with lower cost, shows that the time of the off process is controllable, software developers can automatically close the running process after receiving a shutdown instruction according to the requirements of projects, automatically close the power supply of a system after storing important data, and can freely control the time from the time of receiving the shutdown instruction to the time of starting to shut down according to the requirements.

Description

Controllable safe switching on and shutting down circuit of chronogenesis

Technical Field

The utility model relates to a switching on and shutting down power management technical field, concretely relates to controllable safe switching on and shutting down circuit of chronogenesis.

Background

When the existing product is designed, if a chip without a power management function is used, the functions of starting and shutting down can be realized only by depending on a single chip microcomputer, a solution scheme using the single chip microcomputer needs software development, software version management and control, upgrading maintenance and the like, the consumed time is long, the risk of stability exists, and the hardware cost of the single chip microcomputer is generally high. The existing scheme has the problems of high cost, high development difficulty, inflexible and controllable time from the time of receiving a shutdown instruction to the time of shutdown, and no enough time for storing key data is reserved for software, so that data damage and even system crash are easily caused.

Disclosure of Invention

In view of the problems existing in the background art, a safe power on/off circuit with controllable time sequence is provided, so that the problem of power off safety of a power on/off power management function chip is solved at lower cost.

A time sequence controllable safe startup and shutdown circuit comprises a key input unit, a key detection unit, a logic control unit, a chip control unit and a power supply switch unit, wherein the key input unit is connected with the key detection unit; the power supply switch unit is connected with the chip control unit and controls the on-off state of the power supply switch unit.

Further, the key input unit outputs a high level when a key is pressed, and outputs a low level when the key is released.

Further, the key detection unit detects the level change of the key input unit and feeds the level change back to the chip control unit.

Further, the logic control unit is an or gate circuit, which respectively receives the output signals of the key input unit and the chip control unit as inputs, and when any one of the two inputs is a high-level output signal, the output is a high level.

Furthermore, the output signal of the logic control unit controls the power supply switch unit, the output signal is a high level to turn on the power supply, and the output signal is a low level to turn off the power supply.

Further, the chip control unit is an SOC chip without a power management function.

The utility model discloses the beneficial effect who reaches does: the software developer can automatically close the running process after receiving the shutdown instruction and automatically close the power supply of the system after storing important data according to the requirements of the project, and the time from the receiving of the shutdown instruction to the starting of shutdown can be freely controlled according to the requirements.

Drawings

Fig. 1 is a schematic diagram of a boot process in an embodiment of the present invention.

Fig. 2 is a schematic diagram of a shutdown process in an embodiment of the present invention.

Fig. 3 is a schematic diagram of a key input unit according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a key detection unit according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of a logic control unit according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of a chip control unit in an embodiment of the present invention.

Fig. 7 is a schematic diagram of a power supply switch unit in an embodiment of the present invention.

Fig. 8 is an overall schematic diagram of the safety on-off circuit in the embodiment of the present invention.

Detailed Description

The technical solution of the present invention will be further described in detail with reference to the accompanying drawings.

A time sequence controllable safe startup and shutdown circuit refers to fig. 8 and comprises a key input unit, a key detection unit, a logic control unit, a chip control unit and a power supply switch unit, and normal startup and safe shutdown can be realized without depending on software processes such as any single chip microcomputer and the like.

Referring to fig. 3, the KEY input unit includes a VCC voltage input, a switch SW, a 1K Ω series resistor, and a ground terminal including a 10nF capacitor, and outputs a signal KEY _ OUT at a high level when the KEY is pressed and at a low level when the KEY is released.

Referring to fig. 4, the KEY detection unit receives a KEY _ OUT input, includes a 10K Ω series resistor and a ground terminal including a 20K Ω resistor, may detect a level change of a KEY, and outputs a signal KEY _ DET to the chip control unit. The key detection unit can perform necessary level conversion according to the output voltage of the key input unit and the input voltage requirement of the chip control unit.

Referring to fig. 5, the logic control unit is an or gate circuit having two input sources and one output signal. The input source 1 is an output signal of the key input unit, the input source 2 is an output signal of the chip control unit, any one of the two input sources is high level, the output signal POWER _ CTRL can be changed into high level, the output signal controls the power supply switch unit, the output signal is high level to turn on the power supply, and the output signal is low level to turn off the power supply.

The chip control unit is a system working unit circuit of the whole product and can be any SOC chip without a power management function. Referring to fig. 6, the KEY detection unit input signal KEY _ DET is received and output to the logic control unit signal SW _ PWR _ CTRL.

Referring to fig. 7, the power supply switch is a power supply switch circuit of the whole chip control unit, and includes a MOS transistor 2N7002 receiving a power _ CTRL signal, a constant current source chip FDS6675BZ and peripheral circuits thereof, receives a voltage input VCCIN, and outputs a voltage VCCOUT to the chip control unit. The power supply switch unit is controlled by the output signal of the logic control unit, and a proper MOS device can be selected according to the power consumption of the whole product.

The safe power on/off circuit with controllable time sequence relates to two parts of power on and power off.

Referring to fig. 1, the description and flow of the boot portion are as follows: when a user presses a key, the key input unit outputs a high level, the logic control unit outputs the high level after detecting the high level, the chip control unit starts to work and outputs the high level to the logic control unit, the logic control unit is maintained to output the high level, and the power supply switch unit is continuously started to supply power.

Referring to fig. 2, the shutdown part is described and flows as follows: the chip control unit continuously detects whether the key input unit has a key pressing signal or not in normal work. And after receiving a signal of pressing a key, the chip control unit enters a shutdown flow, and outputs a low level to the logic control unit after processing the ongoing process, and the logic control unit outputs the low level to close the power supply to complete the process of safe shutdown.

The timing sequence of the circuit is mainly controllable in that when a user needs to shut down, even if the key input unit outputs a low level to the or gate circuit of the logic control unit to require shutdown, the chip control unit needs to complete a safe shutdown process and then the SOC outputs a SW _ PWR _ CTRL low level signal to the logic control unit and the low level signal output by the key input unit to shut down the power supply.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the disclosure of the present invention should be included in the protection scope of the claims.

Claims

1. The utility model provides a controllable safe switching on and shutting down circuit of chronogenesis, includes key input unit, button detecting element, logic control unit, chip control unit, power supply switch unit, its characterized in that:

the key input unit is connected with the key detection unit, the key detection unit is connected with the chip control unit, the logic control unit simultaneously receives the input of the key input unit and the chip control unit, and the output of the logic control unit is connected to the power supply switch unit; the power supply switch unit is connected with the chip control unit and controls the on-off state of the power supply switch unit;

when the computer is started, the logic control unit receives a starting key signal of the key detection unit, controls the power supply unit switch unit to be switched on, and starts power supply; when the device is powered off, the logic control unit receives a power-off key signal of the key detection unit and a safe power-off process signal output by the chip control unit at the same time, and controls the power supply switch unit to be switched off to stop supplying power.

2. The timing-controlled safety switching circuit of claim 1, wherein: the key input unit outputs a high level when a key is pressed and outputs a low level when the key is released.

3. The timing-controllable safety on-off circuit as claimed in claim 1, wherein: the key detection unit detects the level change of the key input unit and feeds the level change back to the chip control unit.

4. The timing-controllable safety on-off circuit as claimed in claim 1, wherein: the logic control unit is an OR gate circuit which respectively receives the output signals of the key input unit and the chip control unit as input, and when any one of the two inputs is a high-level output signal, the output is high level.

5. The timing-controllable safety on-off circuit as claimed in claim 4, wherein: the output signal of the logic control unit controls the power supply switch unit, the output signal is a high level to turn on the power supply, and the output signal is a low level to turn off the power supply.

6. The timing-controllable safety on-off circuit as claimed in claim 1, wherein: the chip control unit is an SOC chip without a power management function.