KR890002757A - Static RAM Chip Selector Access Time Reduction Circuit - Google Patents

Static RAM Chip Selector Access Time Reduction Circuit Download PDF

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Publication number
KR890002757A
KR890002757A KR1019870008418A KR870008418A KR890002757A KR 890002757 A KR890002757 A KR 890002757A KR 1019870008418 A KR1019870008418 A KR 1019870008418A KR 870008418 A KR870008418 A KR 870008418A KR 890002757 A KR890002757 A KR 890002757A
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KR
South Korea
Prior art keywords
access time
output
chip selector
signal generation
static ram
Prior art date
Application number
KR1019870008418A
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Korean (ko)
Other versions
KR900003589B1 (en
Inventor
정태성
김병윤
박희철
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870008418A priority Critical patent/KR900003589B1/en
Publication of KR890002757A publication Critical patent/KR890002757A/en
Application granted granted Critical
Publication of KR900003589B1 publication Critical patent/KR900003589B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P20/00—Technologies relating to chemical industry
    • Y02P20/50—Improvements relating to the production of bulk chemicals
    • Y02P20/52—Improvements relating to the production of bulk chemicals using catalysts, e.g. selective catalysts

Abstract

내용없음No content

Description

스테이틱 램의 칩 실렉터 억세스타임 단축 회로Static RAM Chip Selector Access Time Reduction Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 4도는 본 발명에 따른 회로도. 제 5도는 본 발명에 제 4도의 제1,2신호 발생 회로. 제 6도는 본 발명에 따른 제 4도의 동작 파형도.4 is a circuit diagram according to the present invention. 5 is a first and second signal generating circuit of FIG. 4 according to the present invention. 6 is an operational waveform diagram of FIG. 4 in accordance with the present invention.

Claims (1)

스테이틱 램의 칩 실렉터 억세스 타임 단축회로에 있어서, 외부 칩 실렉터 신호에 의해 소정 펄스를 발생하는 제 1,2신호 발생회와, 상기 제 1신호 발생회로의 출력에 따라 스위칭되고 차아지 전원을 공급하는 제 1수단과, 상기 제 2신호 발생회로의 출력에 따라 스위칭 되어 사이 제 1수단의 전원을 어드레스 변환에 따라 차아지 되도록 제어하는 제 2수단과, 상기 제 2수단의 제어에 따라 어드레스 변환시 상기 제 1신호 발생회로의 칩 실렉터 변환과 상기 제 1,2수단을 통해 빨리 차아지하여 어드레스 억세스 타임과 칩 실렉터 억세스 타임이 같은 상태에서 데이타라인, 센스앰프, 데이타 버퍼를 제어하는 제 3수단과, 상기 제 3수단의 출력에 따라 인버팅되며 출력의 응답 속도를 상승시키는 제 4수단과, 상기 제 2수단의 출력을 지연하고 인버팅하여 상기 제 3수단의 어드레스 변환시 공급전원을 차아지 하도록 제어하는 제 5수단으로 구성됨을 특징으로 하는 회로.A chip selector access time reduction circuit of a static RAM, comprising: first and second signal generation cycles generating a predetermined pulse by an external chip selector signal, and switched with an output of the first signal generation circuit and supplying a charge power source A second means for controlling the power supply of the first means to be charged according to the address conversion, and being switched according to the output of the second signal generation circuit; and during the address conversion under the control of the second means. Third means for controlling data lines, sense amplifiers, and data buffers in a state in which the address selector access time and the chip selector access time are equally fast through the chip selector conversion of the first signal generation circuit and the first and second means; Fourth means for inverting according to the output of the third means and increasing the response speed of the output; and delaying and inverting the output of the second means for the third means. And fifth means for controlling the supply power to be charged during address translation of the means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870008418A 1987-07-31 1987-07-31 Access time shorten circuits KR900003589B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870008418A KR900003589B1 (en) 1987-07-31 1987-07-31 Access time shorten circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870008418A KR900003589B1 (en) 1987-07-31 1987-07-31 Access time shorten circuits

Publications (2)

Publication Number Publication Date
KR890002757A true KR890002757A (en) 1989-04-11
KR900003589B1 KR900003589B1 (en) 1990-05-26

Family

ID=19263488

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870008418A KR900003589B1 (en) 1987-07-31 1987-07-31 Access time shorten circuits

Country Status (1)

Country Link
KR (1) KR900003589B1 (en)

Also Published As

Publication number Publication date
KR900003589B1 (en) 1990-05-26

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