KR890002035Y1 - Display control device - Google Patents

Abstract

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Description

Display controls

1 is an overall circuit diagram of a display device including the device of the present invention.

2 is a detailed circuit diagram of part (a) of FIG.

3 is a diagram illustrating a screen display state of Korean and English characters.

4 is a waveform diagram for explaining the operation of the circuit of FIG.

The present invention relates to a device for displaying Korean and English data on a screen, and more particularly to a display control device for setting the size ratio of Korean and English characters to 3: 2.

Conventionally, as shown in FIG. 3A, Korean consists of 2 bytes of BYTE data, and English consists of 1 byte of BYTE. It becomes 1.

However, since the size ratio of Korean characters is relatively larger than English characters, it is difficult to see the imbalance when printing on the screen of a monitor or printer. Especially, the size ratio of Korean characters to English characters is adjusted to 3: 2. If there is, the format printed on the screen and the paper (FORMAT) is different, so when the graphic design is a lot of inconvenience.

Therefore, in the present invention, since the clock control logic for memory control is separately configured in the display control device so as to eliminate such a conventional problem, the size of Korean and English characters is 3: 3 on the screen of the monitor or TV. The purpose of the present invention is to provide a display control device that can be conveniently used, and in particular, when the Hangul alphabet size of the printer becomes 3: 2, without any inconvenience in using a graphic. The accompanying drawings will be described in detail as follows.

First, referring to FIG. 1, the present invention is a memory 1, a central processing unit interface (1), a horizontal row counter (3), an N splitter (4), a scan line divider (5), a column counter (6), and a 2M split counter. (7) A display device comprising a clock generator (8), a character generator (9), a video signal generator (10), and a monitor (11), wherein the Hangul data simultaneous output device (12) and the Hangul data control logic (13) are provided. And a 3: 2 controller (a) composed of a clock control logic 14 and a description of the effect of such a configuration, as shown in FIG. 2, the 3: 2 controller 2 has an AND gate of the counter 20. (21), flip-flop (22), OR gate (23), first to third latches (24, 25, 26) and AND gate (27), inverter (28) and exclusive NOR gate (29). Consists of

Here, Korean and English characters are distinguished as the most significant bit (MSB) of the character.

Here, the most significant bit (MSB) refers to the most significant bit of one byte (one data) in which the original language is the most significient bit and is composed of eight bits.

That is, if one byte consists of 8 bits of D ₀ -D ₇ , the bit of D ₇ becomes the most significant bit.

If the MSB is 1, 2 bytes constitute Korean Hangul characters by adding up the next byte. If the MSB is 0, the Korean Hangul characters consist of 1 byte.

Counter 20 loads the first state of counter 20 as this MSB.

(For example, since the power supply Vcc is always applied to the inputs A and D in the input ABCD of the counter 20, the state is “1” and the input C is always “0” because it is grounded. 1101, 1001).

As the clock signal as shown in FIG. 4A is input, the coefficient of the counter 20 increases, and in the case of the English language, it goes up to the case of the Korean language (1011) of the output (Q _A -Q _D ) of the counter 20. Since the input of the exclusive NOR gate 29 is in a state of "0, 0" or "1, 1", the output of the exclusive NOR gate 29 becomes 1, and a new value is loaded on the counter 20 ( LOAD).

Therefore, 3 clocks are maintained in Korean and 2 clocks are maintained in English. In this case, as shown in FIG. 4, the output Q _A from the counter 20 determines whether to increase the memory row.

That is, in the case of Hangul, after one clock is stopped as 1, 0, and 1, the sequence counter 6 is operated as shown in FIG. 4 to read the next 1-byte data of the memory 1.

In English, it becomes 0, 1, 0, so the next clock stops.

The read data of the memory 1 is output in parallel by the flip-flop 22 and the first through the third latches 24-26 in the case of Korean, and in the case of an English character, the two-byte signal data is output in parallel. The data is output.

If the MSB is “0”, it is English. Therefore, English data is output through the first latch 24 and the second latch 25. If the MSB is “1”, the English data is Korean. Since the byte is output through the first latch 24 and the second latch 25 and the next byte is output through the third latch 26, each of the first, second, and middle characters is represented by 5 bits. .

The data stored in the second and third latches 25 and 26 are held for two clock signals in English and three clock signals in Korean (see FIG. 4 a and g), and are outputted through the character generator. In the case of English image data, the size of two clock times and the size of three clocks in Korean, the size ratio of English and Korean on the screen becomes 2: 3 as shown in FIG.

As described above, according to the present invention, the size ratio of Korean: English can be set to 3: 2 on the monitor screen. The efficiency is very improved.

Claims (2)

A display device comprising a memory, a central processing unit interface, a column counting unit, an N splitter, a scan line divider, a horizontal row counting machine, a 2M splitting counter, a clock generator, a character generator, an image signal generator, and a monitor, comprising: , DISPLAY control device provided with a 3: 2 controller comprising a Hangul data control logic (13) and a clock control logic (14). 3. The controller of claim 1, wherein the 3: 2 controller comprises a counter 20, an AND counter 21, a flip-flop 22, an OR gate 23, and a first to third latch 24, 25, 26. And an AND gate 27, an inverter 28, and an exclusive NOR gate 29.