KR890001797B1 - Refresh control circuit of dram - Google Patents

Abstract

Using the cycle steal mode in controlling the reflesh of DRAM, the refleshing control circuit for a DRAM makes not only the control circuit simple but also the reflesh function stable. The cycle steal mode method is that the reflesh control circuit steals the memory access bus from the CPU. That is, the reflesh control circuit delays the normal operation by stealing the memory access bus which is operated in the CPU. This circuit also make the cost reduction.

Description

DRAM refresh control circuit

1 is a block diagram according to the present invention.

2 is a detailed circuit diagram of FIG. 1 according to the present invention.

3 is a waveform diagram of each part of FIG. 2 according to the present invention.

* Explanation of symbols for main parts of the drawings

10: refresh logic 20: selection unit

30: memory timing unit 40: memory unit

CNT1-CNT3: 1-3 counter DF1-DF6: Difl-flop

MUX1-MUX2: Multiplexer DRAM: DRAM

NA1-NA4: NAND gate NR1: Noah gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh control circuit of a dynamic random access memory (DRAM), and in particular, a cycle steal mode (Cycle Steal Mode) method is used to control refresh of a DRAM, but the control circuit is simplified and refreshed. A refresh control circuit of a DRAM in which a function is made safe.

In general, DRAM stores bits and information as charges of a metal oxide semiconductor (MOS) capacitor, and each bit is determined whether or not data information is stored in one capacitor's charging and discharging state. That is, the state of information can be known by one capacitor per bit as "high" in the charged state and "low" in the discharge state. Here, the read operation is performed by the discharge of the capacitor, and the write operation is performed by the charging. In DRAM, data must be kept from being discharged compared to a reference voltage in order to retain a write. For this purpose, an operation that must be rewritten must be performed. The rewriting operation is called refresh

In the case of MOS integrated circuits, the charge of the discharge DRAM generally has to be recharged every 2ms due to leakage current within several ms when the chip state of the integrated circuit is bad. Therefore, the basic function of DRAM is to refresh the entire address within the DRAM within 2ms. In addition, the operation of the DRAM is continuously performed by timing adjustment and the like by receiving a periodic refresh pulse supply and a multiplexed address signal.

Among the processors that use DRAM as memory, the refreshable processor is Z-8000 (Zilog), and the other processors require a refresh controller. For example, in the series of processors MCG8000, there is no refresh controller, so it has been useful to design it yourself or to use chips from other series to meet your needs. There are also several techniques for refreshing, such as Burst mode, Cycle Steal Mode, Invisible or Trans parent mode. The refresh method is mentioned. The cycle still mode refresh method related to the present invention is a method in which the refresh control circuit steals the memory access bus right from the CPU. That is, the refresh control circuit may steal the normal operation by stealing the memory access bus right that the central processing unit (CPU) is currently performing. A conventional cycle steel mode refresh control circuit has a built-in timer for supplying refresh pulses at regular intervals (typically 16 μs) to refresh the enable signal for a memory access arbiter. It is supplied separately by the timer. However, since the refresh control circuit of the above scheme is constituted by many gate circuits (TTLs), the circuit itself is not only complicated but also has a drawback in that a large delay time is generated.

It was difficult to supply a stable refresh pulse due to the timing delay of the pupil, and there was a problem that a low-cost system could not be constructed. Therefore, an object of the present invention is to provide a stable refresh pulse by using a cycle still mode method, but simply by the circuit configuration to remove the delay, the clock signal for refreshing from the outside and the memory access limiter by the frequency division to supply a stable refresh pulse. It is to provide a circuit so that.

Another object of the present invention is to provide a circuit which can achieve cost reduction in constructing a memory refresh control circuit using a cycle steel mode method. The present invention for achieving the above object is a refresh logic unit for generating a refresh logic signal in accordance with the external supply clock and the memory enable period, and normal memory in accordance with the memory access time control and the output of the refresh logic unit in accordance with the normal operation A memory timing section for controlling operation, a selection section for multiplexing the address signals of the memory according to normal operation (write / read) or refresh by the refresh logic section and the echo timing section, and a memory section which is a DRAM device. Characterized in that configured. Hereinafter, with reference to the drawings of the present invention will be described in detail. 1 is a block diagram according to the present invention, and includes a refresh logic unit 10 for generating a refresh signal according to an external clock signal input to the clock input terminal 1 and a memory enable signal supplied from a CPU. And a memory timing unit 20 for generating a memory access timing signal by combining signals input to the control signal terminal 2 connected to the CPU, and a selection unit for selecting a memory address signal in the refresh address signal or normal operation. 30, and a memory unit 40 capable of storing a large amount of data consisting of a DRAM (DRAM).

Briefly describing an embodiment according to the above configuration, when the memory enable signal is asserted in order to access the memory unit 40 from the central processing unit (hereinafter referred to as "CPU"), the memory timing unit 20 Memory access address and bit are adjusted in normal operation according to the generated control signal, and memory refresh is enabled by blocking normal operation address in refresh operation. At this time, an address is selected according to the normal / refresh operation to access the memory 40 to be accessed by the selector 30.

2 is a detailed circuit diagram of FIG. 1 according to the present invention, in which CNT1-CNT3 is a 1-3 counter, DF1-DF6 is a D flip flop, NA1-NA4 is a NAND gate, NR1 is a NOR gate, N1 is an inverted gate, MUX1-MUX2 is a multiplexer, DRAM is a DRAM memory, R1-R3 is a resistor, and the 614.4KHZ signal through the first clock stage 11 is the first counter. 8 KHZ through the second clock stage 12 is input to the clock terminal CK2 of the second counter CNT2, and the output of the second counter CNT2 is inputted to the clock terminal CK1 of the CNT1. The inverter N1 is inverted and input to the clock terminal CK of the deflip-flop DF2, and the output of the first counter CNT1 is input to the clock terminal CK of the deflip-flop DF1. The output of the counter CNT1 is counted at the third counter CNT3, and the output of the output terminal Q1 of the flip-flop DF1 and the output of the RAM enable stage RAMEN are logically logicized by the NAND gate NA1. To be applied to the preset end PR2 of DF2. And the corresponding portion corresponds to the refresh logic unit 10, and 8MHZ through the third clock stage 31 is applied to the clock terminal CK1 of the deflip-flop DF3, and the signal and the DRAM are passed through the terminal 32. The normal / refresh signal through the enable signal terminal 33 is input to the noble gate NR1, and the output of the noble gate NR1 is applied to the clear terminal CLR of the flip-flop DF3-DF6. And a clear end (CLR) of the flip-flop (DF3-DF6), the flip-flop (DF3-DF6) is coupled in series, the signal from the power supply terminal (Vcc) through the resistor (R3) is It is applied to the preset stage PR of the flip-flop DF3-DF6 to generate a data recognition signal DTACK from the flip-flop DF6, and the output of the output terminal Q1 of the DF5 and the UDS of the CPU ( Up Data Strobe) and Low Data Strobe (LDS) signals are inputted through the nodes 34 and 35 to the outputs of the OA gate NAND gates NA3 and NA4 and the predetermined address signal multiplexer MUX2 at the address stage 37. Be The lock part corresponds to the memory timing unit 20, the multiplexer MUX1 connected to the output terminal of the refresh logic unit 10 corresponds to the selection unit 30, and the DRAM corresponds to the memory unit 40. do.

The waveforms of FIGS. 3 (a) and 3 (n) are waveforms according to the operations of FIG. 2, and the waveforms of FIGS. 3 (a) and 3 (i) are memory (DRAM) access time waveforms. The third (j) to third (n) waveforms are refresh waveforms. Therefore, a specific embodiment of the present invention will be described in detail with reference to Figs. 2 and 3, and when the CPU clock is 8MHZ like the third (a) wave form, the signal of this clock is decoded through the third clock stage 31. The input Q of the flip-flop DF3-DF6 is latched high when it is input to the clock terminal CK1 of the flip-flop DF3 and the output of the no-gate NR1 is in the "low" state. At this time, when the DRAM memory enable (hereinafter referred to as RAMEN) signal is input to the noar gate NR1 for the DRAM access from the CPU such that the DRAM memory enable signal is " low " The state of the output terminal Q of the flip-flop DF3 is switched by the clock terminal CK1 of the third clock stage 31. This outputs the DRAM's Low Address Strobe (RAS) signal from rising edge to rising edge in response to the input clock of the third clock stage 31 as a waveform. Let's do it. In this case, since the address must remain safe for a while after the RAS becomes “low”, the NAND gate NA2 is transferred to the clock terminal CK of the deflip-flop DF4 so as to have a hold time. The 8KHZ signal input to the third clock stage 31 is inverted and input.

Since the output of the output terminal Q of the flip-flop DF4 changes at the rising edge of the signal, the address is multiplexed before the CAS (Column Address Strobe) of the DRAM drops to "low". The time of multiplexing in the above operating state is about 62.5 μs and becomes the third (g) wave form. Subsequently, the 8MHZ signal of FIG. 3 (a) is input to the clock stage CK3 of the flip-flop DF5, and when the signal of the output stage of the flip-flop DF4 is latched at the rising edge, the output terminal of the flip-flop DF5 Since Q is connected to the input terminals of the NAND gates NA3 and NA4, the output signal of the flip-flop DF5 and the upper and lower inputs through the upper and lower data strobe input terminals 34 and 35 are provided. Data Stove (UDS, LDSS) signals are logicized by the oragate NAND gates NA3 and NA4. That is, when the upper and lower data stove signals and the output signals of the output terminal Q of the flip-flop DF5 are input to the NAND gates NA3 and NA4, the address terminals are outputted according to the output of the NAND gates NA3 and NA4. The address signal of (37) is multiplexed by the multiplexer MUX2. In this case, a total of 8 bits are output, each of 4 bits, through the output terminals Q1 and Q2 of the multiplexer MUX2. This signal becomes a CAS (Column Address Strobe) signal of the DRAM. Since this signal is output in synchronization with the third (a) wave form input, it is generated like the third (h) wave form 125 mu s after the above-described RAS generation.

On the other hand, since the output (Q) state of the deflip-flop (DF5) is input to the input terminal (D) of the de-flop-flop (DF4) and the latch clock of the de-flop-flop (DF6) is output from the NAND gate (NA2) At the rising edge, " low " is generated to the output terminal Q of the deflip-flop DF6. This signal becomes the third (i) wave form as the data recognition signal DTACK. Therefore, when CAS is switched to "low" after 125 mu s, the column address (CAS) is selected to perform data write / read to the designated address from the CPU. In the refresh execution time, when the RAMEN signal becomes "high", a refresh pulse is generated to refresh the entire memory address.

The external input 614.4KHZ is inputted to the first clock stage 11 of the first counter CNT1 and 8KHZ is inputted to the second clock stage 12 of the second counter CNT2.

The 76.8 KHZ divided into 8 divisions of 614.4 KHZ is input to the clock terminal CK of the deflip-flop DF1, where the clear terminal CR of the de-flop flop DF1 is "high" and the data input terminal D is When it is "low", the output Q of the diplip-flop DF1 becomes "high" at the rising edge of the signal 76.8KHZ input to the clock input terminal CK, and the (RAMEN) signal is also the NAND gate NA1 from the CPU. NAND gate NA1 outputs "low" because it is input to " high ", and this signal is applied to the preset terminal PR2 of the flip-flop DF2 to output the output terminal of the flip-flop DP2. Q2 of Q2 and Q2 is converted to "high" and (Q2 is outputted as "low", respectively, where the "high" signal of the output terminal Q2 of the flip-flop DF2 is a normal / refresh selection node. The deflip-flop DF3-DF6 is cleared when the refresh selection signal is applied to the noar gate NR1 as shown in the waveform of FIG. 3 (j) at (32).

At this time, the address output for the read / write memory cycle during the refresh cycle is cut off in the multiplexer MUX1, while the " low " signal of the output Q of the deflip-flop DF2 is applied to the second counter CNT2. It is applied to the clear terminal CLR of and is applied to the preset PR1 terminal of the deflip flop DF1. At this time, the second counter CNT2 is cleared, and a counting signal is outputted as 8 waveforms of 8KHZ at 1MHZ as shown in the waveform of FIG. 3 (k) to the clock stage CK1 of the refreshing third counter CNT3. Addressing counts when entered. The output 1MHZ of the second counter CNT2 inverted by the inverting gate N1 is input to the clock terminal CK of the flip-flop DF2 to have a pulse width of 500 μs in the waveform of FIG. A signal of the flash period (7,6 8KHZ = 13μs) is generated through the output terminal Q2 of the deflip-flop DF2.

The output signal of the output terminal Q2 of the deflip-flop DF2 selects and supplies a reflection address through the multiplexer MUX1. In other words, it can be seen that the signal of Fig. 3 (n) is validated in the refresh period " low ". When the RAMEN signal is asserted from the CPU again after the cycle is executed, the output of the NAND gate NA1 becomes "high", and at this time, the preset terminal PR2 of the flip-flop DF2 is "high". At the rising edge of the input signal of the clock stage CK, the output Q of the deflip-flop DF2 is changed to "low" and the output Q is changed to "high".

The second counter CNT2 is cleared when the output terminal Q2 "high" of the flip-flop DF2 is applied to the clear terminal CLR of the second counter CNT2. At this time, the input of the counter CNT2 is cut off, and at the same time, the refresh address signal input to the DRAM DREM is cut off.

On the other hand, the signal " low " of the output terminal Q2 of the flip-flop DF2 is input to the noar gate NR1 to control the DRAM write / read cycle in a steady state cycle, and then the flip-flop. The preset terminal PRI of the flop DF1 is " high " to enable the next refresh (after about 13 mu s) by the refresh cycle.

As described above, when the (RAMEN) signal is in the "high" state, it detects this and divides the external clock input signal (614.4KHZ, 8MHZ) for 8 minutes, and the refresh cycle is supplied at 76.8KHZ at regular intervals. Since it is applied as a flash counter clock, the steady state of the DRAM memory is stabilized, and the control logic of the DRAM by the cycle still mode is simple, which can reduce the cost of the product and eliminate the unstable refresh operation caused by the gate delay. have.

Claims (3)

In a cycle still mode DRAM refresh control circuit having a DRAM 40 and a central processing unit, a refresh signal according to an external clock signal input to a clock input terminal and a memory enable signal supplied from the central processing unit. Is generated by the refresh logic unit 10, a memory timing unit 20 generating a memory access time signal by adjusting a signal input to a control signal terminal connected to the central processing unit, and the refresh signal or normal operation. And a memory unit (40) capable of storing a large amount of data composed of a DRAM (DRAM). 2. The device of claim 1, wherein the refresh logic unit 10 latches the outputs of the first and second counters CNT1-CNT2 and the outputs of the first counter CNT1. The flip-flop DF1, the output of the flip-flop DF1, the NAND gate NA1 that logics the DRAM enable signal, and the inverted output of the second counter CNT2 are used as clock signals. A pre-flip flop DF2 which is preset by the output signal of the NAND gate NA1 and generates a mode signal for refresh pulse generation and refresh control at a predetermined period, and an output of the second counter CNT2. And a third counter (CNT3) which counts and generates an address signal. The NOR gate NR1 of claim 1, wherein the memory timing generator 30 inputs a normal / refresh control signal from the CPU to initialize a timing operation. A deflip-flop DF3 controlled according to an output to generate a RAS signal of the DRAM, and a def-flop DF1- generating a CAS control signal of the DRAM by continuously latching an output of the de-flop DF3. DF5), a NAND gate (NA3-NA4) which logics an upper / lower data strobe signal from the central processing unit and a DRAM (RAS) control signal generated in the flip-flop (DF4-DF5), and the NAND gate. A multiplexer (MUX2) for selecting an address signal according to the output of (NA3-NA4) to generate the CAS signal of the LAN, and a deflip-flop for latching the output of the deflip-flop (DF5) to generate a data recognition signal ( DF6), characterized in that RAM refresh control circuit.

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