KR880700463A - 분리 트렌치의 n 및 p 형 도우핑 방법 - Google Patents
분리 트렌치의 n 및 p 형 도우핑 방법Info
- Publication number
- KR880700463A KR880700463A KR870700264A KR870700264A KR880700463A KR 880700463 A KR880700463 A KR 880700463A KR 870700264 A KR870700264 A KR 870700264A KR 870700264 A KR870700264 A KR 870700264A KR 880700463 A KR880700463 A KR 880700463A
- Authority
- KR
- South Korea
- Prior art keywords
- doping
- isolated trenches
- trenches
- isolated
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US758,717 | 1985-07-25 | ||
US06/758,717 US4653177A (en) | 1985-07-25 | 1985-07-25 | Method of making and selectively doping isolation trenches utilized in CMOS devices |
PCT/US1986/001463 WO1987000687A1 (en) | 1985-07-25 | 1986-07-09 | Selectively doping isolation trenches utilized in cmos devices |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880700463A true KR880700463A (ko) | 1988-03-15 |
KR940005719B1 KR940005719B1 (ko) | 1994-06-23 |
Family
ID=25052805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019870700264A KR940005719B1 (ko) | 1985-07-25 | 1986-07-09 | 분리 트렌치의 n 및 p형 도우핑 방법 |
Country Status (7)
Country | Link |
---|---|
US (1) | US4653177A (ko) |
EP (1) | EP0232322B1 (ko) |
JP (1) | JPS63500482A (ko) |
KR (1) | KR940005719B1 (ko) |
CA (1) | CA1243420A (ko) |
DE (1) | DE3669954D1 (ko) |
WO (1) | WO1987000687A1 (ko) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202426A (ja) * | 1985-03-05 | 1986-09-08 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US5057444A (en) * | 1985-03-05 | 1991-10-15 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating semiconductor device |
DK77287D0 (da) * | 1987-02-16 | 1987-02-16 | Novopan Traeindustri | Spaanplade og fremgangsmaade til fremstilling deraf |
US5200353A (en) * | 1987-06-29 | 1993-04-06 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having trench capacitor |
US4982263A (en) * | 1987-12-21 | 1991-01-01 | Texas Instruments Incorporated | Anodizable strain layer for SOI semiconductor structures |
US5416354A (en) * | 1989-01-06 | 1995-05-16 | Unitrode Corporation | Inverted epitaxial process semiconductor devices |
US5021355A (en) * | 1989-05-22 | 1991-06-04 | International Business Machines Corporation | Method of fabricating cross-point lightly-doped drain-source trench transistor |
US5110755A (en) * | 1990-01-04 | 1992-05-05 | Westinghouse Electric Corp. | Process for forming a component insulator on a silicon substrate |
JP2641781B2 (ja) * | 1990-02-23 | 1997-08-20 | シャープ株式会社 | 半導体素子分離領域の形成方法 |
EP0445471A3 (en) * | 1990-03-06 | 1994-10-26 | Digital Equipment Corp | Method of forming isolation trenches in a semiconductor substrate |
JP3383377B2 (ja) * | 1993-10-28 | 2003-03-04 | 株式会社東芝 | トレンチ構造の縦型のノーマリーオン型のパワーmosfetおよびその製造方法 |
GB9410874D0 (en) * | 1994-05-31 | 1994-07-20 | Inmos Ltd | Semiconductor device incorporating an isolating trench and manufacture thereof |
US5382534A (en) * | 1994-06-06 | 1995-01-17 | United Microelectronics Corporation | Field effect transistor with recessed buried source and drain regions |
KR0165457B1 (ko) * | 1995-10-25 | 1999-02-01 | 김광호 | 트렌치 소자분리 방법 |
US5874346A (en) * | 1996-05-23 | 1999-02-23 | Advanced Micro Devices, Inc. | Subtrench conductor formation with large tilt angle implant |
US5767000A (en) * | 1996-06-05 | 1998-06-16 | Advanced Micro Devices, Inc. | Method of manufacturing subfield conductive layer |
US5770504A (en) * | 1997-03-17 | 1998-06-23 | International Business Machines Corporation | Method for increasing latch-up immunity in CMOS devices |
CN1199926A (zh) * | 1997-05-21 | 1998-11-25 | 日本电气株式会社 | 一种半导体器件的制造方法 |
US5937288A (en) * | 1997-06-30 | 1999-08-10 | Siemens Aktiengesellschaft | CMOS integrated circuits with reduced substrate defects |
US5937287A (en) | 1997-07-22 | 1999-08-10 | Micron Technology, Inc. | Fabrication of semiconductor structures by ion implantation |
US6245639B1 (en) * | 1999-02-08 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | Method to reduce a reverse narrow channel effect for MOSFET devices |
DE10131707B4 (de) | 2001-06-29 | 2009-12-03 | Atmel Automotive Gmbh | Verfahren zur Herstellung eines DMOS-Transistors und dessen Verwendung zur Herstellung einer integrierten Schaltung |
DE10131705B4 (de) | 2001-06-29 | 2010-03-18 | Atmel Automotive Gmbh | Verfahren zur Herstellung eines DMOS-Transistors |
DE10131704A1 (de) * | 2001-06-29 | 2003-01-16 | Atmel Germany Gmbh | Verfahren zur Dotierung eines Halbleiterkörpers |
DE10131706B4 (de) | 2001-06-29 | 2005-10-06 | Atmel Germany Gmbh | Verfahren zur Herstellung eines DMOS-Transistors |
TW563244B (en) * | 2002-10-25 | 2003-11-21 | Vanguard Int Semiconduct Corp | Deep trench isolation structure of high voltage device and its manufacturing method |
KR100950749B1 (ko) * | 2003-07-09 | 2010-04-05 | 매그나칩 반도체 유한회사 | 반도체소자의 소자분리막 형성방법 |
DE10345347A1 (de) | 2003-09-19 | 2005-04-14 | Atmel Germany Gmbh | Verfahren zur Herstellung eines DMOS-Transistors mit lateralem Driftregionen-Dotierstoffprofil |
US7387942B2 (en) * | 2003-12-09 | 2008-06-17 | Promos Technologies Inc. | Substrate isolation in integrated circuits |
US7045436B2 (en) * | 2004-07-27 | 2006-05-16 | Texas Instruments Incorporated | Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) |
FR2905522B1 (fr) * | 2006-08-31 | 2008-12-19 | St Microelectronics Sa | Resistance integree tridimensionnelle |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4104090A (en) * | 1977-02-24 | 1978-08-01 | International Business Machines Corporation | Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation |
US4140558A (en) * | 1978-03-02 | 1979-02-20 | Bell Telephone Laboratories, Incorporated | Isolation of integrated circuits utilizing selective etching and diffusion |
US4244752A (en) * | 1979-03-06 | 1981-01-13 | Burroughs Corporation | Single mask method of fabricating complementary integrated circuits |
US4406710A (en) * | 1981-10-15 | 1983-09-27 | Davies Roderick D | Mask-saving technique for forming CMOS source/drain regions |
US4380865A (en) * | 1981-11-13 | 1983-04-26 | Bell Telephone Laboratories, Incorporated | Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation |
US4472212A (en) * | 1982-02-26 | 1984-09-18 | At&T Bell Laboratories | Method for fabricating a semiconductor device |
JPS5999758A (ja) * | 1982-11-29 | 1984-06-08 | Toshiba Corp | 相補型mis半導体装置の製造方法 |
US4515371A (en) * | 1983-06-13 | 1985-05-07 | Licinio Basevi | Instructional chess game |
US4569701A (en) * | 1984-04-05 | 1986-02-11 | At&T Bell Laboratories | Technique for doping from a polysilicon transfer layer |
US4534824A (en) * | 1984-04-16 | 1985-08-13 | Advanced Micro Devices, Inc. | Process for forming isolation slots having immunity to surface inversion |
US4597164A (en) * | 1984-08-31 | 1986-07-01 | Texas Instruments Incorporated | Trench isolation process for integrated circuit devices |
US4571819A (en) * | 1984-11-01 | 1986-02-25 | Ncr Corporation | Method for forming trench isolation structures |
US4604150A (en) * | 1985-01-25 | 1986-08-05 | At&T Bell Laboratories | Controlled boron doping of silicon |
-
1985
- 1985-07-25 US US06/758,717 patent/US4653177A/en not_active Expired - Lifetime
-
1986
- 1986-07-09 EP EP86904666A patent/EP0232322B1/en not_active Expired - Lifetime
- 1986-07-09 JP JP61503824A patent/JPS63500482A/ja active Granted
- 1986-07-09 KR KR1019870700264A patent/KR940005719B1/ko not_active IP Right Cessation
- 1986-07-09 DE DE8686904666T patent/DE3669954D1/de not_active Expired - Fee Related
- 1986-07-09 WO PCT/US1986/001463 patent/WO1987000687A1/en active IP Right Grant
- 1986-07-17 CA CA000514068A patent/CA1243420A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
CA1243420A (en) | 1988-10-18 |
JPS63500482A (ja) | 1988-02-18 |
EP0232322B1 (en) | 1990-03-28 |
WO1987000687A1 (en) | 1987-01-29 |
US4653177A (en) | 1987-03-31 |
KR940005719B1 (ko) | 1994-06-23 |
EP0232322A1 (en) | 1987-08-19 |
JPH0551181B2 (ko) | 1993-07-30 |
DE3669954D1 (de) | 1990-05-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19990514 Year of fee payment: 6 |
|
LAPS | Lapse due to unpaid annual fee |