KR880006933A - VTR still picture playback circuit - Google Patents

VTR still picture playback circuit Download PDF

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Publication number
KR880006933A
KR880006933A KR860010162A KR860010162A KR880006933A KR 880006933 A KR880006933 A KR 880006933A KR 860010162 A KR860010162 A KR 860010162A KR 860010162 A KR860010162 A KR 860010162A KR 880006933 A KR880006933 A KR 880006933A
Authority
KR
South Korea
Prior art keywords
resistor
transistor
control pulse
capacitor
control
Prior art date
Application number
KR860010162A
Other languages
Korean (ko)
Inventor
이인호
Original Assignee
임경춘
삼성전자부품 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 임경춘, 삼성전자부품 주식회사 filed Critical 임경춘
Priority to KR860010162A priority Critical patent/KR880006933A/en
Publication of KR880006933A publication Critical patent/KR880006933A/en

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Abstract

내용 없음No content

Description

VTR의 정지화면 재생회로VTR still picture playback circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 회로도,1 is a circuit diagram of the present invention,

제2도는 제1도에 따른 각부파형도이다.2 is an angular waveform diagram according to FIG. 1.

Claims (1)

전체동작을 통제 및 제어하는 원칩마이컴(1)과 제어펄스신호를 발생하는 제어펄스발생기(2)를 구비하여서된 VTR의 정지화면 재생회로에 있어서, 상기 제어펄스 발생기 (2)에는 저항(R1)(R2)과 연산 증폭기(0P1)로 구성된 제1증폭부(3)가 연결됨과 더불어 저항(R16-R18)과 콘덴서 (C4)(C5)및 트랜지스터 (Q7)로 구성된 제어펄스뮤팅부(8)가 연결되고, 상기 제1중폭부(3)에는 앤드 게이트(AD1)를 통해 저항(R4)과 가변저항(VR2), 콘덴서 (C2), 트랜지스터 (Q1)및 모노멀티바이브레이터 (M2)로 구성된 제2멀티 바이브레이터부(5)가 연결됨과 더불어 저항(R3)과 가변저항(VR3), 콘덴서 (C3), 트랜지스터 (Q2)및 모노 멀티바이브레이터(M3)로 구성된 제3밀티바이브레이터부(6)가 연결되며 저항(R3)과 가변저항(VR1), 큰덴서 (C1)및 모노멀티바이브레이터 (M1)로 구성된 제1멀티바이브레이터부(4)에는 상기 앤드 게이트(AD1) (AD2)와 제어펄스뮤팅부(8)가 연결되고, 상기 제2, 제3멀티바이브레이터부(5)(6)에는 저항(R6-R15)과 가변저항(VR4)(VR5) 및 트랜지스터 (Q3-Q6)로 구성된 제어신호 발생부(7)가 연결되며, 상기 제어신호 발생부(7)와 제어펄스뮤팅부(8)에는 제어헤드(CH)가 연결됨과 더불어 정지화면 재생스위치 (SW2)를 통해 저항(R19)(VR20)과 연산중폭기(OP2)(OP3)로 구성되는 제2증폭부(9)가 연결되고, 상기 제2증폭부(10)에는 저항(R21) (R22)과 콘덴서(C6)로 구성된 적분기(10)를 통해 저항(R23) (R42)과 가변저항(VR6), 비교기 (CP) 및 트랜지스터 (Q8)로 구성된 비교부(11)가 연결되며, 상기 비교부(11)에는 앤드게이트(AD3)를 통하여 상기 원칩 마이컴 (1)이 연결되어, 프로그램된 임의의 지점에서 정지화면을 시청할 수 있게 제어트랙에 변형된 제어펄스를 기록 및 재생할 수 있도록 된 VTR의 정지화면재생회로,In the still picture reproducing circuit of a VTR, comprising a one-chip microcomputer (1) for controlling and controlling the whole operation and a control pulse generator (2) for generating a control pulse signal, the control pulse generator (2) has a resistance (R 1). Is connected to a resistor (R 16- R 18 ), a capacitor (C 4 ) (C 5 ) and a transistor (Q 7 ), in addition to the first amplifier (3) consisting of (R 2 ) and an operational amplifier (0P 1 ). The configured control pulse muting unit 8 is connected, and the first medium width unit 3 is connected to the resistor R 4 , the variable resistor VR 2 , the capacitor C 2 , and the transistor through an AND gate AD 1 . Q 1 ) and the second multi-vibrator section 5 composed of a mono-multivibrator (M 2 ) are connected and a resistor (R 3 ), a variable resistor (VR 3 ), a capacitor (C 3 ), a transistor (Q 2 ) and mono multivibrator (M 3) third milti vibrator unit 6 is connected, and the resistance (R 3) and a variable resistor (VR 1), a large condenser (C 1) and the mono multivibrator (M 1) consisting of Generated first multi-vibrator unit 4 is provided with the AND gate (AD 1) (AD 2) and the control pulse muting portion (8) is connected, the second, the third multivibrator section 5 (6), the resistance A control signal generator 7 consisting of (R 6 -R 15 ), a variable resistor (VR 4 ) (VR 5 ) and a transistor (Q 3 -Q 6 ) is connected, and controls with the control signal generator (7). The pulse muting unit 8 is connected to the control head CH and is composed of a resistor R 19 (VR 20 ) and an operational amplifier (OP 2 ) (OP 3 ) through a still picture playback switch (SW 2 ). A second amplifier 9 is connected, and the second amplifier 10 has a resistor R 23 (R 42 ) through an integrator 10 composed of a resistor R 21 (R 22 ) and a capacitor C 6 . ) And a comparator 11 composed of a variable resistor VR6, a comparator CP and a transistor Q 8 , are connected to the comparator 11 through an AND gate AD 3 . Is connected to watch a still image at any point programmed Can allow recording the control pulse to the control strain, and the track of the VTR to play the still image reproducing circuit, ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR860010162A 1986-11-29 1986-11-29 VTR still picture playback circuit KR880006933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR860010162A KR880006933A (en) 1986-11-29 1986-11-29 VTR still picture playback circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR860010162A KR880006933A (en) 1986-11-29 1986-11-29 VTR still picture playback circuit

Publications (1)

Publication Number Publication Date
KR880006933A true KR880006933A (en) 1988-07-25

Family

ID=68469831

Family Applications (1)

Application Number Title Priority Date Filing Date
KR860010162A KR880006933A (en) 1986-11-29 1986-11-29 VTR still picture playback circuit

Country Status (1)

Country Link
KR (1) KR880006933A (en)

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