KR880001348B1 - High speed 1/32 and 1/33 cmos free scaler circuit - Google Patents

Abstract

This circuit can be used for the demultiplexer of an audio digital tunning system. The freescaler is composed of NAND gates, an inverter and a determination circuit of demultiplex. The determination circuit of demultiplex (1) and 1/2 demultiplex circuit are initialized by applying the signal "1" to the preset input terminal (6). If the determination signal of demultiplex ratio is applied to the input terminal of selection signal input (7), the outputs of NAND gates are all "1" states and also the output of the inverter is "1". If the determination signal is applied to (7), 1/ 32 clockpulse is outputed.

Description

High Speed 1/32 and 1/33 Sea Morse Prescaler Circuit

1 is a conventional high speed Sea Morse 1/2 frequency division circuit diagram.

2 is a block diagram of a high speed 1/32 and 1/33 Sea Morse Freescaler circuit in accordance with the present invention.

3 is a high speed Sea Morse 1/2 frequency divider circuit according to the present invention.

4 is a timing diagram of each point in FIG.

5 is a detailed circuit diagram of a frequency division decision circuit.

6 is an overall circuit diagram of the present invention showing a concrete circuit diagram of a frequency division decision circuit.

FIG. 7 is a timing diagram of each point in FIG. 6 when the division ratio determination signal is " 1 ".

* Explanation of symbols for main parts of the drawings

1: Division decision circuit 2, 3, 4: 1/2 division circuit

TECHNICAL FIELD The present invention relates to high speed 1/32 and 1/33 Sea Morse Prescale circuits, and more particularly to high speed prescaler circuits used in Sea Morse Large Scale Integrated Circuits (LIS) composed of dynamic logic.

The present invention can be used as a divider circuit in an audio digital tuning system, and a conventional prescaler is composed of an ECL (Emitter Coupled Logic). In addition, in the case of the conventional C-MOS type 1/2 frequency divider circuit used in the related art, as shown in FIG. 1, the clock pulse input terminal CK is inputted to the clock pulse input terminal CK to output Q as Q. In this case, there was no input of preset or reset. In addition, since the number of MOS transistors used is 12, the use of the high-speed prescaler circuit of the present invention has difficulty in reducing the size of the chip due to the addition of the preset function and the reduction of the number of transistors used.

However, the circuit diagram of FIG. 1, which is a conventional half-dividing circuit, can be used for high speed by minimizing each gate so that it can operate for high speed. However, the addition of a preset function increases the number of MOS transistors used. It has been.

Accordingly, the present invention provides a high-speed Sea Morse-type prescaler circuit capable of combining 1/32 and 1/33 divisions with a minimum number of Morse transistors and minimum logic using the dynamic characteristics of the Sea Morse of the present invention.

It is still another object of the present invention to provide a C-MOS dynamic 1/2 frequency divider circuit using a minimum MOS transistor having a preset function.

Hereinafter, the prescaler circuit of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a prescaler capable of 1/32 and 1/33 division using C. Morse according to the present invention. FIG. 2 shows NAND gate NA ₁ -NA ₃ and inverter INV1-INV17, frequency division decision circuit (1) and FIG. It consists of one-third, half-dividing circuits (2) (3) (4).

After the signal of "1" is input to the preset input terminal 6 to initialize the frequency division decision circuit 1 and the half frequency division circuits 2, 3, and 4, the division ratio determination signal Psc becomes "0". When inputting to the division ratio selection signal input terminal (7), the outputs of the NAND gate NA ₁ -NA ₃ are all "1", and the output of inverter INV5 is also output to the D point with "1", and the division is decided. The clock pulse is divided into 1/4 of the clock pulse inputted to the division ratio selection input terminal SS of the circuit 1 and input to the clock pulse input terminal _5, and the clock pulse is outputted to the output terminal Q ₅ , and the 1/4 divided cool-loop The pulses are divided in order by the first, second, and third half-dividing circuits (2) (3) (4), thereby dividing 1/4 × 1/2 × 1/2 × 1/2 = 1/32 Then, 1/32 divided clock pulses are outputted to the output terminal (8). Therefore, when the division ratio determination signal Psc = "0" is input to the division ratio determination signal input terminal 7, the clock pulses divided by 1/32 are always output to the output terminal 8.

However, when the division ratio determination signal Psc = "1" is inputted to the division ratio determination signal input terminal 7, the state of the point D is changed according to the state of points A, B, and C of FIG. If any one or more of the points becomes "0", the output of point D becomes "1", but if all three points become "1", the output of point D becomes "0" and the quasi-main selection input As described later by inputting to the terminal SS, the clock divided by 1/33 is output to the output terminal 8. That is, when the output of the point D becomes "1" state, the frequency division decision circuit 1 performs 1/4 division, but when the point D becomes "0" state, that is, the points A, B, and C all become "1" state. Since the frequency division decision circuit 1 divides one cycle of the input clock pulse further, 1/33 division clock pulses are output to the output terminal 8. This relationship is explained in detail in the specific circuit diagram of the frequency division decision circuit 1.

3 is a detailed circuit diagram of the high speed 1/2 frequency divider circuit 2, 3, 4 used basically in the 1/32 and 1/33 prescaler circuits of FIG. 2 according to the present invention. In the figure, MP1-MP4 is a PMOS transistor, MNO-MN5 is an NMOS transistor V _DD is a transistor power supply voltage V _SS is a source power supply voltage, and CK is a clock pulse.

4 is a waveform diagram of each part of the 1/2 frequency divider circuit according to the present invention of FIG.

For the initial operation, if a pulse with a preset input of "high" (hereinafter referred to as "1") is applied to the gate of the NMOS transistor MN0 and the clock pulse KC is "1", the NMOS transistor MNO is turned on. Q ₂ = "0" and therefore the PMOS transistor MP4 is on, so Q ₃ is "1" and this level is fed back so that the transistor NM1 is on and Q ₁ is "0". Since the PMOS transistor MP2 and the NMOS transistor MN3 are turned off, the Q ₁ , Q ₂ , and Q ₃ points remain in the "0", "0", "1" state, respectively. "1" state of the point Q ₃ is kept to "1" state is charged to the parasitic capacitance of C ₃ Q ₃ points for a predetermined time. If the clock pulse CK goes from "1" to "0", the PMOS transistor MP2 is turned on, but the MOS transistor MN1 is turned on by the "1" state charged in the parasitic capacitance C ₃ , so that Q ₁ is "0". "maintaining state, and a state of blood Mohs transistor MP3 on Q _2, so that" 1 is filled with a first "state" is a state in the parasitic capacitance C ₂ ". Therefore, the NMOS transistor MN5 is turned on but MN4 is turned off by the clock pulse, so that Q ₃ remains at " 1 ".

Back of clock pulse CK turns to "1" state blood Mohs transistor MP2 is turned off and yen Mohs transistor MN1 is turned on, so being Q ₁ that is so maintained to "0" and a state of blood five MOS transistor MP3 on Q ₂ points It is in the "1" state and charged to the parasitic capacitance C ₂ and remains in the "1" state. Thus yen Mohs transistor MN5 is turned on, and Yen Mohs transistor MN4 also so as to become an ON-state Q ₃ points yen is more than the feedback status is to be the voltage of the parasitic capacitor C ₃ discharges is set to "0" Mohs transistors by the clock pulse MN1 is off and PMOS transistor MP1 is on.

At this time, the clock pulse CK becomes "0" again, the PMOS transistor MP2 is turned on, the Q ₁ point is turned "1", the parasitic capacitance C ₁ is charged, and the enMOS transistor MN3 is turned on. However, the clock pulse yen by CK = "0" Mohs transistor MN2 is turned off blood Mohs transistor MP3 is turned on is because the Q ₂ that is "1" and the state blood Mohs transistor MP4 is state since Q ₃ points before the off It keeps the "0" state.

In the same manner, when the clock pulse CK becomes "1", the Q ₁ , Q ₂ and Q ₃ points are respectively "

1 "" 0 "" 1 "state and when clock pulse CK becomes" 0 "state, Q ₁ , Q ₂ and Q ₃ points are respectively" 0 "" 1 "

In the state of "1", the waveform shown in FIG. 4 is drawn. Thus the output Q ₃ is presented the 1/2 frequency division clock pulses of the clock pulse CK and the frequency division occurs by the pre-set time delay pulse blood Mohs transistors MP1, MP2 and Yen Mohs transistor MN1 and the P transistor MP3 and Mohs yen High-speed 1/2 of CMOS by four gate delays by four gates of Morse transistors MN2 and MN3 and a P-MOS transistor MP4 or by one of the NMOS transistors MN4 and MN5 resulting in a minimum gate count. It will be a division circuit.

Fifth is a specific circuit diagram of the frequency division decision circuit 1 used for the 1/32 and 1/33 prescaler circuits according to the present invention. do.

The pulse is input with the preset input signal "1" at the preset terminal PS, the pulse with the status "1" is input at the division ratio select input terminal SS, and the clock pulse is input at the clock pulse input terminal CK. 1 "if the input was assumed" 1 en by the preset signal, and Mohs transistor MN12 is turned on since the blood Mohs transfected jiseung emitter MP14 is also turned on Q _1, Q ₂ point "is" 0

The parasitic capacitance of Q ₂ is charged to the " 1 " state, and thus the voltage of " 1 " is charged, so that the EnMOS transistor MN16 is turned on and the EnMOS transistor MN is driven by the clock pulse.

15 In addition, since the on-state Q ₃ point is the "0" state, thus avoiding Mohs transistor MP20 is on, and dispensing "1" P by a signal state Mohs transistor MP19 to the input to the non-selected input terminal (SS) also on state Q ₄ is charged to the parasitic capacitance in a state of "1", and the NMOS transistor MN22 is turned on and the NMOS transistor M is turned on by the clock pulse.

Since N21 is also turned on, Q ₅ is in the "0" state.

Therefore, when the preset signal is input as "1" and the signal of "1" is input to the division ratio select input terminal (SS), when the clock pulse becomes "1", Q ₁ = "0" Q ₂ = "1" Q ₃ = "0" Q ₄ = "1" Q ₅ = "0" is output. Therefore, Q ₅ = " 0 " is fed back to the gate of the PMOS transistor MP10 so that the transistor is in the on state.

If the clock pulse is changed to "0" now, the PMOS transistor MP11 is turned on and the Q ₁ point is set to "1", and is charged to the parasitic capacitance. Thus yen Mohs transistor MN14 is termed the on-state the clock pulse because it is "0" yen Mohs transistor MN13 are in the OFF state is also preset signal because the "0" state is blood Mohs transistor MP14 is also off-Q ₂ that is "1" Maintain the state. Hereinafter, the states of Q ₃ , Q ₄ , and Q ₅ are also maintained at the states "0", "1", "0" as in the case where the clock pulse is "1". When the clock pulse becomes "1" again, Q ₁ = '1 ", so that the transistors MN13 and MN14 are turned on so that Q ₂ is changed to" 0 "and the remaining points are the same as before.

Similarly, Q when "1" is input to the division ratio selection input terminal SS and the preset signal is input to the preset input terminal PS as a pulse having a "1" state, and then the clock pulse CK is input. ₁ sheet of -Q ₅ point are given in Table 1.

TABLE 1

Therefore, as can be seen in Table 1, when "1" is inputted to the division ratio selection input terminal (SS), it can be seen that the division becomes 1/4.

Therefore, in FIG. 6, when the division ratio determination signal Psc is "0", the input of the division ratio selection input terminal SS of the division determination circuit 1 always becomes "1" state. The total division ratio by the second and third half dividing circuits (2) (3) (4) is 1/32 divided.

This time considers a case where the division ratio determination signal Psc is input in the " 1 " state. If Psc = " 1 " and a preset pulse of " 1 " state is inputted to the preset input terminal PS of the frequency division decision circuit 1, and the clock pulse CK = " 1 " As can be seen from FIG. 3, the outputs Q _A , Q _B , and Q _C of the 1/2 frequency divider circuit are all "1" and the points A, B and C are in the mode "0". Therefore, the output of NAND gate NA3 becomes "1" and "1" is inputted into the division ratio selection input terminal SS. In this state, the output states of A, B, and C are all "1". When it is maintained until "State" and A, B, and C points are all "1", the output of NAND gate NA3 becomes "0" and when "0" is input to division ratio selection input terminal SS, frequency division decision circuit (1) The state change of each point of Q ₁ -Q ₅ is as shown in Table 2 below.

[Table 2]

Therefore, as can be seen from Table 2, it can be seen that the clock pulses of the arrow marks of Table 2 are further added between the arrow marks of Table 1. That is, in Table 1, Q ₁ Q ₂ Q ₃ Q ₄ Q ₅ = 0

101 "and then" 1011 ", but in Table 2, Q ₁ Q ₂ Q ₃ Q ₄ Q ₅ =" 101 "followed by" 11 "

0 "is added, and then" 01011 'which is the same as Table 1 is output as a ratio. Therefore, the arrowed part in Table 2 is one cycle of the input clock pulses, which is 1/32 divided to 1/33 divided.

In other words, even if the division ratio determination signal Psc becomes 1, "1" is inputted into the division ratio selection input terminal SS until the outputs of the A, B, and C points are all 1, and the division determination circuit 1 is 1 /. It is divided into 4 and the output of A, B, and C points becomes "1", and the frequency is further divided by one period of the input clock pulse. Therefore, 1/33 division clock is output to the prescaler output terminal (8). Done.

Therefore, when the division ratio determination signal Psc = "1", the waveform diagram when "1" is input to the division ratio selection input terminal SS is shown. As shown in FIG. 7, 1/33 division pulses are output, and the division ratio determination signal Psc = In the case of "0", it can be seen that the frequency is divided as much as time T ₁ , which is one period of the input clock pulse.

As described above, the present invention can simplify the entire circuit by simultaneously realizing 1/32 and 1/33 by the division ratio determination signal through a single circuit, and requires high-speed division by configuring the dynamic C-MOS type. In addition to the MOS integrated circuit can be applied to one chip can be made.

Claims (2)

In a dynamic seed dispensing circuit, an inverter for outputting the first, second and third half-dividing circuits (2) (3) (4) composed of a high-speed seed moss and capable of presettings NAND Kate (NA ₁₎ (NA _2), (NA ₃₎ to the input and dispensing determine the output state of the logic gate (NA ₃₎ according to the logic state of the frequency division ratio decision signal (Psc) circuit 1 through a control At the same time, a clock pulse is inputted, and the output of the frequency division decision circuit 1 is input to the frequency division circuit 2 through an inverter INV7 to generate a logic state of a preset signal and the division ratio determination signal Psc. A dynamic C. Morse prescaler circuit characterized in that it performs 1/32 and 1/33 division. The frequency division decision circuit 1 comprises a division ratio select input terminal SS, a preset terminal PS, and a clock pulse input terminal CK, and a PMOS transistor MP10-MP22 and an enMOS transistor. Selecting the division ratio by constructing a SeaMOS frequency division decision circuit composed of (MN10-MN25). Quarter division or one division of the input clock pulse can be added according to the logic state of the input terminal (SS). Circuit characterized in that the presence.

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