KR880000033Y1 - Circuit for controlling motor speed of the cassette - Google Patents

Abstract

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Description

Motor speed control circuit of cassette recorder

1 is a circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

PB, REC, FF: Mode selection switch SEN: Detection switch

M: Motor IV ₁ -IV ₁₀ : Inverter

NR ₁ , NR ₂ : Noah gate EXOR ₁ -EXOR ₄ : Exclusive logic circuit

ND ₁ , ND ₂ : NAND gate MSR: Motor speed stabilization circuit

LT ₁ , LT ₂ : Latch circuit AD ₃ : End gate

The present invention relates to a motor speed control circuit of a cassette recorder, and more particularly, to a cassette recorder capable of appropriately controlling the motor speed of a simple cassette recorder having only functions of playback, recording, and fast-forwarding mode according to each mode. It relates to a motor speed control circuit.

In general, the cassette recorder is configured to control the driving direction and speed of the magnetic cape by various mechanisms including gears in the cassette tech for each mode such as playback and recording, fast forwarding and rewinding. In order to stir a variety of operations, one-chip microcomputers tend to be mounted on cassette recorders. However, in the cassette recorder which has a one-chip micro computer to control the operation according to various modes, the one-chip micro computer not only controls the driving direction and speed of the magnetic tape, but also performs other reservation recording or automatic selection. Since the circuit is configured to perform various functions together, if one-chip microcomputer which performs various functions as described above is installed in the cassette recorder which performs only simple functions such as playback, recording and fast-forwarding mode, If the product price becomes expensive and the driving direction and speed control of the magnetic tape of the cassette recorder are controlled by mechanical operation, it becomes not only complicated mechanically but also reliability of the product due to the ease of failure caused by the complicated mechanism. Done There was a flaw.

Therefore, the present invention was devised to improve the above-mentioned shortcomings, and a simple logic circuit was constructed in the cassette recorder which was designed to perform only a simple function so that the motor speed was controlled according to each mode. It is an object of the present invention to provide a motor speed control circuit of a cassette recorder which can be controlled by the driving direction and the speed of the magnetic tape by allowing it to be controlled.

Hereinafter, the configuration, operation, and effects of the present invention will be described in detail with reference to the illustrated drawings.

The present invention provides a recording mode selector switch (REC) with an inverter (IV ₁ ), a noah gate (NR ₁ ), an inverter (IV ₂ ), a beta logic circuit (EXOR ₁ ), an inverter (IV ₃ ), and a resistor (R ₁ ). The base of the transistor Q ₁ is connected in turn, and the output terminal of the exclusive logic circuit EXOR _{2 in} which the resistor R ₂ and the inverter turn IV ₄ are arranged in series with the regenerative mode selector switch PB. In addition to this connection, the other input terminal of the noble gate NR ₁ is connected, and the fast forwarding mode selection switch FF is connected to the inverter IV ₅ , the exclusive logic circuit EXOR ₃ , the inverter IV ₆ , and the resistor R. ₃ ), in turn, the base of transistor Q ₂ is connected, while a resistor R ₄ and an inverter IV ₇ are connected to one input terminal of the exclusive logic circuit EXOR ₂ , and a magnetic tape end sensing switch ( SEN) is connected to the input terminal of the exclusive logic circuit EXOR ₂ and EXOR ₃ , respectively, and the NAND gate ND _{1 is} connected to the input terminal. The output terminal of the connected exclusive logic circuit (EXOR ₁ ) is exclusively passed through the latch circuit (LT ₁ ), the inverter (IV ₈ ), the NAND gate (ND ₂ ), the inverter (IV ₉ ), and the exclusive logic circuit (EXOR ₄ ). the input terminal of the logic circuit (EXOR ₃₎ is connected, the latch circuit (LT _2), the said NAND gate (ND ₂₎ is associated with the aND gate (AD ₃₎ and NOR gate (NR ₂₎ an inverter (IV ₁₀₎ after addition Together with the fast forward mode select switch (FF), the emitter and collector of the transistor (Q ₁ ) via a motor (M), a motor speed stabilization circuit (MSR) and a transistor (Q ₃ ). It is interconnected, and the collector of the transistor Q ₂ has a structure in which the motor M is connected via a resistor R ₆ and a transistor Q ₄ .

1 is a circuit diagram of the present invention configured as described above, since the mode selection switch (PB) (REC) (FF) is all turned off in the power-only state, the motor (M) does not operate, so (R ₂₎ a power supply (Vcc) through two been converted to a low signal through an inverter (IV ₁₎ is inputted to one input terminal of the NOR gate (NR _1), NOR gate the other input terminal, the resistance of the (NR ₁₎ (R ₄ ) the signal from which the power supply Vcc through the inverter IV ₇ is converted into a low signal and the signal from which the power supply Vcc through the resistor R ₂ are converted into the low signal through the inverter IV ₄ are respectively. The low output signal of the exclusive logic circuit EXOR ₂ and the signal of the play mode selection switch PB in the off state are inputted, respectively.

Therefore, a high signal is output from the output side of the noble gate NR ₁ , converted to a low signal by the inverter IV ₂ , and then input to one input terminal of the beta logic circuit EXOR ₁ , and then the exclusion of the exclusive logic circuit EXOR ₁ . Since the low output signal of the NAND gate ND _{1 to} which the power supply Vcc is input is supplied to the input terminal of the exclusive logic circuit EXOR ₁ (EXPR ₄ ), the low signal is output to the latch circuit LT ₁ . inverter and be fed to (IV _3), is input to the base of the inverter transistor (Q ₁₎ as via a (IV ₃₎ converted to a high signal through the resistance (R ₁₎ accordingly transistor (Q ₁₎ is turned off It becomes On the other hand, since the fast forward mode selection switch (FF) and the sensing switch (SEN) are turned off, the low signal in which the power supply (Vcc) through the resistor (R ₄ ) is inverted through the inverter (IV ₁₀ ) is a noar gate (NR ₂ ). A latch circuit connected to one input of the input terminal of the NOR gate (NR ₂ ) and connected to a resistor (R ₄ ), a fast send mode selection switch (FF), and an inverter (IV ₅ ) (IV ₇ ) (IV ₁₀ ). The output low high signal of LT ₂ ) is applied to the AND gate AD ₃ , and then output as a low signal.

Accordingly, a high signal is output from the output terminal of the noble gate NR ₂ , and a low signal is converted by the inverter IV ₅ , and then input to one input terminal of the exclusive logic circuit EXOR ₃ . On the other hand, at the other input terminal of the logic circuit EXOR ₃ , the output low signal of the exclusive logic circuit EX OR ₁ described above is output as a high signal by the latch circuit LT ₁ , and is converted into a low signal by the inverter IV ₈ . inverted and then inputted to one input terminal of the NAND gate (ND _2), after it is at a low signal from the NAND gate latch circuit (LT ₂₎ in the above-described other input terminal of the (ND ₂₎ is input to the NAND gate (ND _2), the high signal is output inverter (IV ₉₎ with a low signal on the inverted and then an exclusive logic circuit (EXOR ₄₎ which is above the other input end of the bar, wherein an exclusive logic circuit (EXOR ₄₎ is input to one input terminal of NAND gate (ND of ₁₎ since a low signal is input to the output from the the output terminal low signal of the exclusive logic circuit (EXOR ₄₎ output is the output stage, the low signal of the exclusive logic circuit (EXOR ₃₎ the output of the exclusive logic circuit (EXOR ₃₎ It will be input to the other input.

Therefore, since the low signal is output to the output terminal of the exclusive logic circuit EXOR ₃ and is inverted to a high signal by the inverter IV ₆ , and then input to the base of the transistor Q ₂ through the resistor R ₃ , the transistor Q _2. ) Is to be turned off. From this, as the transistors Q ₁ and Q ₂ are turned off, the transistors Q ₃ and Q ₄ are also turned off, so that the motor M is not operated.

On the other hand, when the user presses the recording mode selection switch (REC), the power (Vcc) through the resistor (R ₂ ) is grounded through the switch (REC), so that the high signal is accumulated through the inverter IV ₁ Noah gate there is inputted to the input terminal of the (NR _1), wherein the other input terminal of the NOR gate (NR ₁₎ because there is a high output signal of the exclusive logic circuit (RXOR ₂₎ is input as described above, the output terminal of the NOR gate (NR ₁₎ There will be a low signal output to be input to one input terminal of the following exclusion logic circuit (EXOR ₁₎ inverted to a high signal by the inverter (IC _2), as is described above, the other input terminal of the exclusive logic circuit (EXOR ₁₎ accordingly Since the low signal output from the NAND gate ND ₁ is being input, a high signal is output to the output side of the exclusive logic circuit EXOR ₁ , inverted to a low signal by the inverter IV ₃ , and then passed through a resistor R ₁ . Transistor (Q _Since it is input to the base of ₁ ), the transistor Q ₁ is turned on.

Since the fast forwarding mode selection switch FF and the sensing switch SEN are turned off, as described above, a low signal output by the inverter IV ₅ is input to one input terminal of the exclusive logic circuit EXOR _{3 while} the other is input. As described above, since the output low signal of the exclusive logic circuit EXOR ₄ is input to the input terminal, a low signal is output to the output side of the exclusive logic circuit EXOR ₃ , and accordingly, a low state signal is output to the inverter IV ₆ . The transistor Q ₂ is turned off because it is inverted by and then supplied to the base of the transistor Q ₂ through the resistor R ₃ .

Therefore, as described above, the transistor Q ₃ is turned on by the turn-on of the transistor Q ₁ so that a current flows through the motor M and the motor speed stabilization circuit MSR. The cassette recorder by the recording mode selection switch (REC) operation is performed therefrom.

On the other hand, since the user inputs to the other input terminal of the NOA gate NR ₁ via the playback mode select switch PB to reproduce the recorded contents recorded on the magnetic tape, the output terminal of the NOA gate NR ₁ outputs a low signal. Since the subsequent operation operates in the same manner as when the recording mode is selected, the transistors Q ₁ and Q ₃ are turned on so that current flows through the motor M and the motor speed stabilization circuit MSR. The rotor M performs the constant speed operation, from which the cassette recorder by the playback mode selection switch PB operation performs the playback operation.

On the other hand, when the user quickly presses the send mode selection switch FF, the power supply Vcc is grounded through the resistor R ₄ and the switch FF while the recording and playback mode selection switch REC (PB) is turned off. Since the high signal through the inverter IV ₁₀ and the output of the latch circuit LT ₂ and the end gate ND ₃ are input to the input terminal of the noble gate NR ₂ as described above, A low signal is sent to the output shaft of the gate NR ₂ , and a high signal is applied to the input terminal of the exclusive logic circuit EXOR ₃ through the inverter IV _{5. In} this case, a high signal is applied to the other input terminal of the exclusive logic circuit EXOR ₃ . As described above, the exclusive logic circuit EXOR receives the output signal from the latch circuit LTI, the inverter IV ₈ , the NAND gate ND ₂ , and the inverter IV ₉ and the output signal of the NAND gate ND ₁ . with a low signal of _four) of different exclusive logic circuit (EXO E ₃₎ Since applied to ryeokdan, an output shaft of an exclusive logic circuit (EXOR ₃₎ is therefore input to the base of the are is at a high signal is inverted to a low signal by the inverter (IV _6), and then the resistance (R ₃₎ a through the transistor (Q ₂₎ transistors ( Q ₂ ) is turned on. Accordingly, the transistor Q ₄ is turned on by the collector voltage of the transistor Q ₂ , and the mode select switch RED RR is turned off, so that the transistors Q ₁ and Q ₃ are turned off as described above. Will be in a state. Therefore, since the current flowing in the motor M is grounded by the transistor Q ₄ and not through the motor stable speed circuit MSR, the power supply Vcc is applied to the motor M, so that the motor M is fast. This will cause the cassette recorder to perform the send mode quickly.

In addition, when the running of the magnetic tape is completed in the state of performing the quick sending mode as described above, the uneven portion at the end of the magnetic tape is detected by the sensing switch SEN, and the sensing switch SEN is turned on. Accordingly, since the signal is grounded through the sense switch SEN at the high output of the inverter IV ₅ , the transistor Q ₂ is turned off by outputting the low signal as the output of the exclusive logic circuit EXOR ₃ as described above. It is in a state. At this time, although the fast forwarding mode selection switch FF is turned on, the transistor Q ₁ is also turned off as the output terminal of the inverter IV ₇ is changed from a high signal to a low signal by the sensing switch SEN. . Therefore, the motor M stops without operating, and the fast forwarding mode selection switch FF is turned off, so that the cassette recorder stops operating.

As described above, the present invention has the advantage that the motor speed of the cassette recorder can be controlled with a simple logic circuit, so that various functions such as the playback and recording of the cassette recorder, which performs only a simple function, and the fast sending mode can be sufficiently performed. There is this.

Claims (1)

The recording mode selector switch (REC) passes through an inverter (IV ₁ ), a noah gate (NR ₁ ), an inverter (IV ₂ ), an exclusive logic circuit (EXOR ₁ ), an inverter (IV ₃ ), and a resistor (R ₁ ). The base of (Q ₁ ) is connected, and the output terminal of the exclusive logic circuit (EXOR ₂ ), in which a series resistor (R ₂ ) and an inverter (IV ₄ ) are connected to an input terminal thereof, is connected to the regeneration mode selection switch (PB). The other input terminal of the noble gate (NR ₁ ) is connected, and the fast-forwarding mode selection switch (FF) passes through the inverter (IV ₅ ), the exclusive logic circuit (EXOR ₃ ), the inverter (IV ₆ ), and the resistor (R ₃ ). A base of the transistor Q ₂ is connected, and a resistor R ₄ is connected to an input terminal of the exclusive logic circuit EX OR ₂ via an inverter IV ₇ , and to the magnetic tape end detection switch SEN. an exclusive logic circuit (EXOR ₂₎ EXOR ₃₎ and the input terminal are connected, respectively, the NAND gate (ND ₁₎ are you are being connected to the input terminal The output terminal of the exclusive logic circuit (EXOR _1), the latch circuit (LT ₁₎ and the inverter (IV _8), a NAND gate (ND _2), an inverter (IV _9), and an exclusive logic circuit exclusive logic through (EXOR ₄₎ in turn circuit ( EX OR ₃ ) is connected, and the latch circuit LT ₂ is connected to the NAND gate ND ₂ , and is connected to the inverter IV ₁₀ through the AND gate AD ₃ and the NOA gate NR ₂ . The fast forward mode select switch FF is connected, and the emitter and collector of the transistor Q ₁ are interposed between the motor M, the motor speed stabilization circuit MSR and the transistor Q ₃ . to interconnect and said transistor (Q ₂₎ the collector of a transistor (Q ₄₎ the Motor (M) is connected to a cassette recorder constructed Motor speed control circuit of the via.