KR870004255U - Parallel conversion circuit of serial data - Google Patents

Parallel conversion circuit of serial data

Info

Publication number
KR870004255U
KR870004255U KR2019850010813U KR850010813U KR870004255U KR 870004255 U KR870004255 U KR 870004255U KR 2019850010813 U KR2019850010813 U KR 2019850010813U KR 850010813 U KR850010813 U KR 850010813U KR 870004255 U KR870004255 U KR 870004255U
Authority
KR
South Korea
Prior art keywords
conversion circuit
serial data
parallel conversion
parallel
serial
Prior art date
Application number
KR2019850010813U
Other languages
Korean (ko)
Other versions
KR880003598Y1 (en
Inventor
이인옥
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019850010813U priority Critical patent/KR880003598Y1/en
Publication of KR870004255U publication Critical patent/KR870004255U/en
Application granted granted Critical
Publication of KR880003598Y1 publication Critical patent/KR880003598Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Communication Control (AREA)
KR2019850010813U 1985-08-24 1985-08-24 Pararell modulating circuit of a direct data KR880003598Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019850010813U KR880003598Y1 (en) 1985-08-24 1985-08-24 Pararell modulating circuit of a direct data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019850010813U KR880003598Y1 (en) 1985-08-24 1985-08-24 Pararell modulating circuit of a direct data

Publications (2)

Publication Number Publication Date
KR870004255U true KR870004255U (en) 1987-03-31
KR880003598Y1 KR880003598Y1 (en) 1988-10-12

Family

ID=19244909

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019850010813U KR880003598Y1 (en) 1985-08-24 1985-08-24 Pararell modulating circuit of a direct data

Country Status (1)

Country Link
KR (1) KR880003598Y1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411231B1 (en) * 1995-12-28 2004-03-18 주식회사 하이닉스반도체 Method for converting data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411231B1 (en) * 1995-12-28 2004-03-18 주식회사 하이닉스반도체 Method for converting data

Also Published As

Publication number Publication date
KR880003598Y1 (en) 1988-10-12

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19970829

Year of fee payment: 12

EXPY Expiration of term