KR870003581A - Low resistance contact semiconductor device and its manufacturing method - Google Patents

Low resistance contact semiconductor device and its manufacturing method Download PDF

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Publication number
KR870003581A
KR870003581A KR1019860008003A KR860008003A KR870003581A KR 870003581 A KR870003581 A KR 870003581A KR 1019860008003 A KR1019860008003 A KR 1019860008003A KR 860008003 A KR860008003 A KR 860008003A KR 870003581 A KR870003581 A KR 870003581A
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KR
South Korea
Prior art keywords
metal layer
semiconductor device
region
refractory metal
substrate
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Application number
KR1019860008003A
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Korean (ko)
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KR940009584B1 (en
Inventor
뎅 수 쉥
Original Assignee
글렌 에이취. 브루스틀
알. 씨. 에이 코오포 레이숀
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Publication of KR870003581A publication Critical patent/KR870003581A/en
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Publication of KR940009584B1 publication Critical patent/KR940009584B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides

Abstract

내용 없음No content

Description

저저항 접촉의 반도체 장치와 그 제조방법Low resistance contact semiconductor device and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명에 따른 반도체 장치의 일부 횡단면도.1 is a partial cross-sectional view of a semiconductor device according to the present invention.

제 2 도는 부분 공정이 완료된 반도체 장치의 일부 횡단면도.2 is a partial cross-sectional view of a semiconductor device in which a partial process is completed.

제 3 도는 제 1 도에 도시된 점선영역의 확대도.3 is an enlarged view of the dotted line region shown in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : MOSFET 12 : 기판10: MOSFET 12: substrate

16 : 소오스 영역 18 : 드레인 영역16: source region 18: drain region

Claims (7)

기판, 상기 기판표면으로부터 아래로 신장된 영역 및 전기적 접촉을 형성하기 위해 상기 영역에 결합된 저저항 접촉수단을 가진 반도체 장치에 있어서, 상기 저저항 접촉수단은 제 1 의 내화 금속층과 상기 제 1의 내화금속층과 상기 영역을 전기적으로 접촉시키도록 그 사이에 놓인 제 2 의 규소화 금속층을 구비하는 것을 특징으로 하는 반도체 장치.A semiconductor device having a substrate, a region extending down from the substrate surface, and low resistance contact means coupled to the region to form electrical contact, wherein the low resistance contact means comprises a first refractory metal layer and the first refractory metal layer. And a second metal silicide layer interposed therebetween to electrically contact the refractory metal layer and the region. 제 1 항에 있어서, 상기 제 2 의 규소화 금속층은 상기 기판표면 아래로 부분적으로 신장하는 것을 특징으로 하는 반도체 장치.2. The semiconductor device according to claim 1, wherein said second silicide metal layer partially extends below said substrate surface. 제 2 항에 있어서, 제 1 의 내화 금속층은 제 2규소화 금속층보다 두꺼운 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 2, wherein the first refractory metal layer is thicker than the second silicon nitride metal layer. 제 1 도전형 물질의 반도체 기판, 높게 도우프된 제 2 도전형 물질로 상기 기판에 형성되고, 상기 기판 표면으로부터 아래로 신장하고, 서로 이격배치되어 그 사이에 채널 영역을 형성하는 제 1 영역과 제 2 영역 및 상기 채널 영역위에 배치된 게이트를 구비하고, 상기 제 1 및 제 2 영역은 상기 기판표면으로부터 신장된 제 1 의 규소화 금속층과 상기 제 1의 규소화 금속층 위에 배치되는 제 2의 내화 금속층을 구비하는 것을 특징으로 하는 반도체 장치.A semiconductor substrate of a first conductivity type material, a first region formed on the substrate with a second doped material that is highly doped, extending downward from the substrate surface and spaced apart from each other to form a channel region therebetween; A second refractory having a second region and a gate disposed over said channel region, said first and second regions being disposed over said first siliconized metal layer and said first siliconized metal layer extending from said substrate surface; A semiconductor device comprising a metal layer. 제 4 항에 있어서, 상기 제 2 의 내화 금속층은 상기 제 1 의 규소화 금속층보다 얇은 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 4, wherein the second refractory metal layer is thinner than the first silicon silicide layer. 1) 반도체 장치에 제 1 표면을 갖는 소오스 영역을 형성하는 단계, 2) 채널 영역을 형성하기 위해 제 2 표면을 갖는 드레인 영역을 상기 소오스 영역으로부터 이격 배치해서 상기 반도체 장치에 형성하는 단계, 3) 상기 채널 영역위에 게이트를 형성하는 단계, 4) 상기 제 1 및 제 2 표면 위에 제 1 의 규소화 금속층을 형성하는 단계 및 5) 상기 제 1 의 규소화 금속층위에 제 2 의 내화 금속층을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치 제조방법.1) forming a source region having a first surface in the semiconductor device, 2) forming a drain region having a second surface spaced apart from the source region in the semiconductor device to form a channel region, 3) Forming a gate over the channel region, 4) forming a first metal silicide layer on the first and second surfaces, and 5) forming a second refractory metal layer on the first metal silicide layer. A semiconductor device manufacturing method comprising a. 제 6 항에 있어서, 상기 4)단계와 5)단계는 상기 제 1 및 제 2 표면위에 내화 금속층을 형성하는 단계와 상기 내화 금속층의 일부분과 상기 실리콘 기판의 일부분을 결합시키기 위해 상기 반도체 장치를 가열시키고, 상기 내화성 금속층의 나머지 부분과 상기 기판의 나머지 부분간에 규소화 금속층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조방법.7. The method of claim 6, wherein steps 4) and 5) heat the semiconductor device to form a refractory metal layer on the first and second surfaces and to couple a portion of the refractory metal layer to a portion of the silicon substrate. And forming a silicon nitride layer between the remaining portion of the refractory metal layer and the remaining portion of the substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860008003A 1985-09-27 1986-09-25 Low resistance contact for a semiconductor device and method of making same KR940009584B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US78095685A 1985-09-27 1985-09-27
US780,956 1985-09-27

Publications (2)

Publication Number Publication Date
KR870003581A true KR870003581A (en) 1987-04-18
KR940009584B1 KR940009584B1 (en) 1994-10-15

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JP (1) JPS6278817A (en)
KR (1) KR940009584B1 (en)
DE (1) DE3632217A1 (en)
SE (1) SE8603963L (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2624304B1 (en) * 1987-12-04 1990-05-04 Philips Nv METHOD FOR ESTABLISHING AN ELECTRICAL INTERCONNECTION STRUCTURE ON A SILICON SEMICONDUCTOR DEVICE

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5575256A (en) * 1978-12-01 1980-06-06 Nec Corp Semiconductor device
JPS5780739A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPS60119750A (en) * 1983-12-02 1985-06-27 Hitachi Ltd Manufacture of semiconductor device

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DE3632217A1 (en) 1987-04-02
JPS6278817A (en) 1987-04-11
KR940009584B1 (en) 1994-10-15
SE8603963D0 (en) 1986-09-19
SE8603963L (en) 1987-03-28

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