KR870002709U - Delay signal generation circuit of central processing unit - Google Patents

Delay signal generation circuit of central processing unit

Info

Publication number
KR870002709U
KR870002709U KR2019850009633U KR850009633U KR870002709U KR 870002709 U KR870002709 U KR 870002709U KR 2019850009633 U KR2019850009633 U KR 2019850009633U KR 850009633 U KR850009633 U KR 850009633U KR 870002709 U KR870002709 U KR 870002709U
Authority
KR
South Korea
Prior art keywords
processing unit
central processing
generation circuit
signal generation
delay signal
Prior art date
Application number
KR2019850009633U
Other languages
Korean (ko)
Other versions
KR880003591Y1 (en
Inventor
임종걸
Original Assignee
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 금성사 filed Critical 주식회사 금성사
Priority to KR2019850009633U priority Critical patent/KR880003591Y1/en
Publication of KR870002709U publication Critical patent/KR870002709U/en
Application granted granted Critical
Publication of KR880003591Y1 publication Critical patent/KR880003591Y1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
KR2019850009633U 1985-07-26 1985-07-26 Delay signal generating circuit of cpu KR880003591Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019850009633U KR880003591Y1 (en) 1985-07-26 1985-07-26 Delay signal generating circuit of cpu

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019850009633U KR880003591Y1 (en) 1985-07-26 1985-07-26 Delay signal generating circuit of cpu

Publications (2)

Publication Number Publication Date
KR870002709U true KR870002709U (en) 1987-03-18
KR880003591Y1 KR880003591Y1 (en) 1988-10-12

Family

ID=19244278

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019850009633U KR880003591Y1 (en) 1985-07-26 1985-07-26 Delay signal generating circuit of cpu

Country Status (1)

Country Link
KR (1) KR880003591Y1 (en)

Also Published As

Publication number Publication date
KR880003591Y1 (en) 1988-10-12

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