KR860008613A - Semiconductor Memory and Manufacturing Method - Google Patents

Abstract

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Description

Semiconductor memory device and manufacturing method thereof.

Since this is an open matter, no full text was included.

1 is a plan view of a ROM according to the present invention.

2 is a cross sectional view taken along the line II-II of FIG. 1;

Claims (24)

A semiconductor memory device having the following functions as a memory dedicated to memory. Each of the MISFETs, which are memory cells of the memory dedicated memory, and each of the MISFETs have a first or second threshold voltage. A word line formed integrally with the gate electrode of the MISFET, a data line connected to the drain region of the MISFET and extending in a direction crossing the word line, and an insulating film formed between the word line and the data line, and the first insulating film; And a second insulating film thereon. On the MISFET of the first threshold voltage, the first and second insulating films are present, and on the MISFET of the second threshold voltage, the first insulating film exposed by removing the second insulating film is present. do. By ion implantation through the first insulating film, the threshold voltage of the MISFET becomes from the first value to the second value. In the semiconductor memory device according to claim 1, the first insulating film is a silicon nitride film. In the semiconductor memory device according to claim 2, the second insulating film is a silicon oxide film containing or not containing impurities. In the semiconductor memory device according to claim 2, the insulating film further comprises a third insulating film formed under the first insulating film. This is a membrane that does not contain nitrogen. In the semiconductor memory device according to claim 1, the first insulating film is a polycrystalline silicon film containing no impurities. In the semiconductor memory device according to claim 1, the first and second insulating films are silica glass films having a low impurity concentration and a high impurity concentration, respectively. In the semiconductor memory device according to claim 1, the first insulating film is thinner than the second insulating film. In the semiconductor memory device according to claim 1, the first insulating film is a film that is difficult to be etched in etching for removing the second insulating film. In the semiconductor memory device according to claim 1, the word line is a layer containing a polycrystalline silicon layer and a high fused metal thereon. In the semiconductor memory device according to claim 1, a plurality of the MISFETs are connected in parallel between the data line and the ground potential. In the semiconductor memory device according to claim 1, a plurality of the MISFETs are connected in series between the data line and the ground potential. In the semiconductor memory device according to claim 11, the MISFET is of n channel type, and a single charged boron is implanted to make it a depression type. The following semiconductor memory device having a memory dedicated memory function, a plurality of MISFETs each used as memory cells of the memory dedicated memory, and each MISFET has a first or second threshold voltage. An insulating film covering the memory cell, which is a first insulating film and a second insulating film thereon. The first and second insulating layers are on the MISFET of the first threshold voltage, and the first insulating layer is on the MISFET of the second threshold voltage. The threshold voltage of the MISFET becomes a second value from the first value by ion implantation through the first insulating film. The following semiconductor memories, a plurality of MISFETs each of which is used as a memory cell, and each memory cell are in a first or second state. An insulating film covering the memory cell, which is a first insulating film and a second insulating film thereon, is formed. The first and second insulating layers exist on the memory cell in the first state, and the first insulating layer exists on the memory cells in the second state. The memory cell is brought into the second state from the first state by ion implantation through the first insulating layer. In the semiconductor memory device according to claim 14, a part of the memory cells that are brought into the second state from the first state by the ion implantation becomes the first conductive type to the second conductive type. A method of manufacturing a semiconductor memory device, a step of forming a MISFET which is a memory cell, and the MISFET have a first threshold voltage. A step of forming an insulating film covering the memory cell, and the insulating film is a first insulating film and a second insulating film thereon. The second insulating film has a quality that is different from that of the first insulating film. The etching rate of the second insulating film is faster than that of the first insulating film due to the step of removing the second insulating film on the selected cell among the memory cells by etching and the difference in the quality of the film between the first and second insulating films. An etching method such as this is used. And implanting impurities into the channel region of the MISFET of the selected memory cell through the first insulating film, whereby the MISFET of the selected memory cell has a second threshold voltage. As a method of manufacturing a semiconductor memory device according to claim 16, the following matters are further provided. A step of forming a connection hole in the insulating film, and a step of forming a wiring layer on the insulating film, which are connected to the MISFET through the connection hole. In the method of manufacturing a semiconductor memory device according to claim 17, the etching step of the second insulating film is performed after the connection hole forming step and the wiring layer forming step. In the method of manufacturing a semiconductor memory device according to claim 17, the connection hole forming step is performed after the ion implantation step. As a method for manufacturing a semiconductor device according to claim 17, the following items are also provided. The annealing step for activating the implanted impurities and the annealing step are performed at least before the wiring layer forming step after the ion implantation step. The wiring layer is made of aluminum. In the method of manufacturing a semiconductor memory device according to claim 17, the etching step of the second insulating film is performed using a part of the connection hole forming step. The wiring layer forming step is performed after the ion implantation step. In the method of manufacturing a semiconductor memory device according to claim 16, the etching is dry etching. In the method of manufacturing a semiconductor memory device according to claim 16, the etching is wet etching. In the method of manufacturing a semiconductor memory device according to claim 16, the impurity is a single charged ion. ※ Note: The disclosure is based on the initial application.