KR850000119B1 - Control method of electronic engine - Google Patents

Abstract

A process for electronically controlling an internal combustion engine employs a plurality of engine controlling programs to be executed by a central processing unit classified into a number of task programs in accordance with processing functions of the CPU. The periods at which the task programs are to be activated are determined in consideration of the influential significance of the tasks in controlling the engine, whereby the task programs are executed in accordance with the activation periods thereof under supervision of a program for monitoring the plurality of the engine control programs.

Description

Electronic engine control method

1 to 23 show a first embodiment when the control method of the present invention is applied to an internal combustion engine equipped with a vaporizer.

1 is a cross-sectional view of a throttle chamber of an engine.

2 is a schematic view of an ignition device.

3 is a system diagram of a white gas reflux apparatus.

4 is an overall block diagram of a control system.

5 is a program system diagram of the control circuit of FIG.

6 is a configuration diagram of a memory showing program contents stored in a ROM.

7 is a detailed flowchart of the initial program.

8 is a detailed flowchart of the monitoring program.

9 is a characteristic diagram which shows the ignition timing at engine start.

10 is a characteristic diagram showing fuel supply amount at engine start-up.

11 is a characteristic diagram showing an air supply amount at engine start-up.

12 is a detailed view of the EGRCAL and FISC programs.

13 is a detailed flowchart art of the program 224 of FIG.

14 is a detailed flowchart of the task scheduler (TASK SCHEDULER).

15 is an explanatory diagram for explaining the operation of generating a start request for a task level program;

16 is a detailed flowchart of the EXIT program.

17 is an explanatory diagram of a processing procedure of a program.

18 is a view showing a state change of a level program.

19 is a view for explaining a state change of the background job (BACKGROUND JOB).

20 is a detailed flowchart of the program of the level zero task.

21 is a detailed flowchart of the program of the level 1 task.

22 is an IRQ generation circuit diagram.

23 to 28 show a first embodiment in which the control method of the present invention is applied to a fuel injection type internal combustion engine.

Fig. 23 is a sectional view showing a schematic configuration of an engine control device.

24 is a block diagram of the overall configuration of the control device.

25 is a detailed flowchart of the initial program.

Fig. 26 is a characteristic diagram showing a fuel supply amount at engine start-up.

27 is a detailed flowchart of EGRCAL and FISC programs.

28 is a detailed flowchart of the program of the level 1 task.

FIG. 29 is a detailed block circuit diagram relating to the CABC 162, FSC 176 and FIG. 24 IFSC registers and EGRC registers of FIG.

30 is a detailed block diagram of the IGNCs 168 and 1138 of FIGS. 4 and 24;

FIG. 31 is a detailed circuit diagram relating to the discrete input / output circuitry (DIO) 128 of FIGS. 4 and 24. FIG.

32 is a detailed block circuit diagram related to the INJD register of FIG.

FIG. 33 is a waveform diagram for explaining the circuit operation in FIG.

The present invention relates to an electronic control method for an internal combustion engine, and more particularly, to a control method for controlling an internal combustion engine by digital arithmetic processing by a central processing unit (hereinafter referred to as a CPU).

Methods and apparatus for controlling an engine in accordance with a predetermined program using a CPU are disclosed in US Pat. Nos. 3,969,614 and 4,163,282. According to this conventional technique, a series of programs are executed in accordance with the state of the engine for each control object from information extraction from the sensor to setting of the control amount for all functions to control the engine. Such control programs include, for example, a fuel amount control program, an ignition timing control program and an engine start program. The fuel amount control program, the ignition timing control program, and the like are executed in synchronization with, for example, a constant crank angle of the engine rotation, and the task processing of the program is executed by outputting the fuel supply amount or the ignition timing advance amount, which is the result of the calculation, to the pulse output circuit. Was shutting down.

When the program is executed in any state of the engine as described above, the load state of the CPU, which is the control system, varies greatly depending on the operation state of the engine.

Therefore, in a state in which the engine state is suddenly changed, the CPU load is significantly increased in accordance with the state in which the CPU load is suddenly changed, thereby degrading the serviceability of the CPU (easiness of error detection, diagnosis and repair of hardware or software). For example, when the engine speed changes from low speed to medium speed and high speed, in the conventional system, the number of times of operation request, which is the number of executions of task processing to the CPU, increases with the engine speed, and the CPU may not be able to meet this request. Can be.

On the other hand, at low speeds, the load factor of the CPU decreases, and the capability of the CPU becomes useless. As described above, in the conventional apparatus and method, it is inconvenient to obtain a service corresponding to the capability of the CPU as a whole of the control system.

In addition, in the above patent, when it is necessary to change the contents of one of a plurality of control programs or when a new program is added, only a partial change is necessary, and eventually, the entire control programs must be rewritten. There was inconvenience.

It is an object of the present invention to provide a control method of an engine which can always obtain a high control performance without being affected by a change in the state of an engine.

The present invention divides a plurality of engine control contents performed by a CPU into several tasks according to the processing functions of the CPU, and determines the start cycle according to the influence of each processing function on the engine controllability, that is, the importance. The program of the task is executed in accordance with the start cycle. In this way, the ratio of the task service which requires high serviceability in engine controllability can be raised significantly, and the load state of a CPU hardly changes even if the state of an engine, ie, engine speed, etc. changes.

Therefore, it is possible to control with excellent control performance that fully exhibits the capabilities of the CPU.

In addition, the present invention has a management program for managing the execution of a plurality of engine control contents (control program), and when a program content of one of the plurality of control programs is changed or a new program is added to another control program. The contents of the program can be changed or added without any influence, and thus the contents of the program can be easily changed.

Other objects and advantages of the present invention will become apparent from the following description of the drawings.

First, the present invention will be described with reference to FIGS. 1 to 22 with reference to the first embodiment when applied to an internal combustion engine equipped with a vaporizer.

1 is a cross sectional view of a throttle chamber of an engine. First, the control of the amount of fuel and the bypass air supplied to the throttle chamber by the operation of each solenoid installed around the throttle chamber will be described. The opening degree of the low-speed side throttle valve 12 is controlled by an accelerator pedal (not shown), thereby controlling the amount of air supplied to each cylinder of the engine from the air cleaner (not shown). If the passage air volume of the low speed side venturi 34 increases as the opening of the low speed throttle valve is enlarged, the high speed side throttle valve 14 is caused by a diaphragm (not shown) depending on the negative pressure of the low speed side venturi 34. ) Is opened. As a result, the increase in resistance due to the increase in the amount of intake air is reduced. In this way, the flow rate of the air supplied to the engine under the control of the throttle valves 12 and 14 is converted into an analog amount by a negative pressure sensor (not shown). The opening degree of each solenoid valve 16,18,20,22 of FIG. 1 is controlled based on this analog quantity and the signal from the sensor mentioned later.

Next, control of the fuel supply amount will be described. Fuel supplied from the fuel tank flows from the conduit 24 to the conduit 28 via the main jet pipe 26. Fuel in conduit 24 also enters conduit 28 via main solenoid valve 18. Therefore, the fuel introduced into the conduit 28 increases as the opening of the main solenoid valve 18 increases, and these fuels are mixed with air in the engine emulsion tube 30 again and pass through the main nozzle 32 to venturi. 34 is supplied. When the high speed throttle valve 14 is opened, fuel is supplied to the venturi 38 even through the nozzle 36 communicating with the main nozzle 32. On the other hand, when the slow solenoid valve 16 is controlled at the same time as the main solenoid valve 18 and the slow solenoid valve 16 is opened, the air passing through the air purifier is discharged from the opening 40 to the conduit 42. Supplied. Meanwhile, fuel from conduit 28 is supplied to conduit 42 via slow emulsion tube 44. Therefore, the amount of fuel in the conduit 42 becomes smaller as the amount of air from the slow solenoid valve 16 increases. The mixture of fuel and air in this conduit 42 is supplied to the throttle chamber from the aperture 46.

The fuel solenoid valve 20 is a valve for increasing the amount of fuel, and is used to increase the amount of fuel for starting the engine or to increase the fuel for warming the engine. Fuel introduced from the hole 42 in communication with the conduit 24 flows into the conduit 50 leading to the throttle chamber, depending on the opening degree of the fuel solenoid valve 20.

The air solenoid valve 32 is a valve for controlling the amount of air supplied to the engine. The air from the air cleaner is supplied from the opening 52 to the air solenoid valve 22, and passes through the throttle chamber according to the degree of the opening. Flows into conduit 54.

The air fuel ratio is controlled by the slow solenoid valve 16 and the main solenoid valve 18 of FIG. 1, and the fuel amount is increased by the fuel solenoid valve 20. FIG. Moreover, the engine speed at no load is controlled by the slow solenoid valve 16, the main solenoid valve 18, and the air solenoid valve 22. FIG.

2 shows an ignition device, in which a pulse current is supplied to the power transistor 64 via the amplifier 62, and the transistor 64 is turned on by this current. As a result, the primary coil current flows from the storage battery 66 to the ignition coil 68. As the input pulse current falls, the transistor 64 is turned off and generates a high voltage at the secondary coil of the ignition coil 68. This high voltage is supplied to each of the ignition plugs 72 in each cylinder of the engine via the distributor 70 in synchronization with engine rotation.

3 is for explaining the exhaust gas complete (hereinafter referred to as EGR) system, in which a constant negative pressure of the negative pressure source 80 is applied to the control valve 86 via the pressure control valve 84. The pressure control valve 84 controls the ratio of opening the constant negative pressure of the negative pressure source 80 to the atmosphere 88 and applies it to the control valve 86 according to the on-duty cycle of the repetitive pulse applied to the transistor 90. To control the negative pressure. Therefore, the negative pressure applied to the control valve 86 is determined based on the duty cycle of the transistor 90. The amount of EGR from the exhaust pipe 92 to the intake pipe 82 is controlled by the control pressure of the pressure control valve 84.

4 is an overall configuration diagram of the control system. This control system is composed of 102, read-only memory 104 (hereinafter referred to as ROM), random access memory 106 (hereinafter referred to as RAM), and input / output circuits 108. As shown in FIG.

The CPU 102 calculates input data from the input / output circuit 108 in accordance with various programs stored in the ROM 104, and returns the operation result back to the input / output circuit 108. The temporary data storage required for this operation uses the RAM 106. The transfer of various data between the CPU 102, the ROM 104, the RAM 106, and the input / output circuit 108 is performed by the bus line 110 composed of a data bus, a control bus, an address bus, and the like. The input / output circuit 108 includes a first analog-digital converter 122 (hereinafter referred to as ADC1), a second analog-digital converter 124 (hereinafter referred to as ADC2), and an angle signal processing circuit 126. And input means of a discrete input / output circuit 128 (hereinafter referred to as DIO) for inputting and outputting 1-bit information.

The ADC1 includes a battery voltage detection sensor 132 (hereinafter referred to as VBS), a coolant temperature sensor 134 (hereinafter referred to as TWS), an atmospheric temperature sensor 136 (hereinafter referred to as TAS), and a regulated voltage generator 138 (hereinafter referred to as "a"). VRS), the throttle angle sensor 140 (hereinafter referred to as θ _THS ), and the λ sensor 142 (hereinafter referred to as λS) are applied to the multiplexer 162 (hereinafter referred to as MPX), One of them is selected by the MPX 162 and input to the analog-to-digital converter 164 (hereinafter referred to as an ADC). The digital value that is the output of the ADC 164 is stored in the register 166 (hereinafter referred to as REG).

The negative pressure sensor 144 (hereinafter referred to as VCS) is input to ADC2 124 and digitally converted via an analog-to-digital converter 172 (hereinafter referred to as ADC) to register 124 (hereinafter referred to as REG). I remember. From the angle sensor 146 (hereinafter referred to as ANGS), a signal indicating a reference crank angle, for example, 180 degrees crank angle (hereinafter referred to as RES), and a signal indicating a small angle, for example, 1 degree crank angle (hereinafter referred to as POS) is output and applied to the angle signal processing circuit 126, where the waveform is shaped. The output of the no-load switch 148 (hereinafter referred to as IDLE-SW), the top gear switch 150 (hereinafter referred to as TOP-SW) and the start switch 152 (hereinafter referred to as START-SW) is provided in the DIO 128. It is being input.

Next, the pulse output circuit and the control target based on the calculation result of the CPU 102 will be described. The air-fuel ratio control device 165 (hereinafter referred to as CABC) controls the slow solenoid valve 16 and the main solenoid valve 18 by changing the duty cycle of the pulse signal in this embodiment.

The output signal from CABC 165 is applied to main solenoid valve 18 via inverter 163 because the duty cycle of CABC 165 is increased, thereby reducing the fuel supply by main solenoid valve 18. . On the other hand, the slow solenoid valve 16 increases the fuel supply amount as the duty cycle of the pulse signal from the CABC 165 increases. The CABC 165 is provided with a register for storing the repetitive pulse period (hereinafter referred to as CABP) and a register for storing the duty cycle of the same pulse signal (hereinafter referred to as CABD), and these data are separately stored in the CPU 102. I remember.

The ignition pulse generation circuit 168 (hereinafter referred to as IGNC) includes a register for storing ignition timing data (hereinafter referred to as ADV) and a register for controlling the ignition coil primary current energization time (hereinafter referred to as DWL). These data are stored in the CPU 102. The output pulse of this IGNC 168 is applied to the ignition device 170. The details of this ignition device 170 are as shown in FIG. 2, and the output pulse is applied to the amplifier 62 of FIG.

The fuel amount increase pulse generation circuit 176 (hereinafter referred to as FSC) controls the duty cycle of the pulse to control the fuel solenoid valve of FIG. 1, and the duty cycle of the same pulse as the register (hereinafter referred to as FSCP) that stores the repetition period. It has a register (hereafter referred to as FSCD) to store. The EGR amount control pulse generation circuit 178 (hereinafter referred to as EGRC) includes a register for storing data of pulse repetition period (hereinafter referred to as EGRP) and a register for storing data of duty cycle of the pulse signal (hereinafter referred to as EGRD). ), And a repetitive pulse is applied to the air solenoid valve 22 via the AND gate 184, and the signal of the output DIO1 of the DIO 128 is applied to the AND gate 184, which is a DIO1 signal. Is at a low level, the AND gate 184 is in an operating state, and the air solenoid valve 22 is controlled.

On the other hand, when the DIO1 is at a high level, the AND gate 186 is brought into an operating state to control the EGR device 188. The basic configuration of the EGR device 188 is as already described in FIG. As described above, the DIO 128 is an input / output circuit of a 1-bit signal, and includes a register 192 (hereinafter referred to as DDR) 192 for storing data for determining input or output, and a register 194 for storing output data. (Hereinafter referred to as DOUT).

The DIO 128 outputs a signal DIOO for controlling the fuel pump 190.

5 is a program system of the control circuit of FIG. When the power is turned on by the key switch (not shown), the CPU 102 enters the star art mode to execute the INITIALIZ 204 of the early program. Next, the MONIT 106 of the monitoring program is executed to execute the BACKGROUND JOB 208.

As this background jog, for example, an EGR calculation task (hereinafter referred to as "EGRCAL TASK") or a fuel solenoid valve and an air solenoid valve ("FISC") are executed. If an interruption interruption request (hereinafter referred to as IRQ) occurs during the execution of this task, the IRQ request analysis program 224 (hereinafter referred to as IRQ ANAL) is executed at the start step 222 of the IRQ. The program of IRQ ANAL is again executed by the termination intervention processing of ADC1 (hereinafter referred to as ADC1 END IRQ) program 226, the termination intervention processing of ADC2 (hereinafter referred to as ADC2 END IRQ) program 228, and a predetermined time elapses. It is composed of an interruption interruption processing program (hereinafter referred to as INTV IRQ) program 230 and an engine interruption interruption interruption processing (hereinafter referred to as ENST IRQ) program 232, and the like. QUEUE). The tasks in which the QUEUE is output by the respective programs ADC1 END IRQ 226, ADC2 END IRQ 228, and the INTV IRQ 230 programs in the IRQ ANAL program 224 are the level "0" task group 252. ). It is a task which comprises the level "1" task group 254, the level 2 task group 256, the level 3 task group 258, or each task group. The task in which the QUEUE is generated by the ENST IRQ program 232 is the processing task 262 (hereinafter referred to as ENST TASK) at the engine stop. When this ENST TASK 262 is executed, the control system again becomes a star art mode and returns to the start step 202.

The task scheduler 242 determines the execution order of the task group to execute in the task group in which the QUEUE occurs or in the task group having a high level among the suspended task group (here, level "0" is the highest). When the execution of the task group ends, the end report is reported by the end report program 260 (hereinafter referred to as EXIT). By the end report, the task group with the highest level of task groups waiting to be executed is executed next. When the task group where the interrupt task group or the QUEUE is generated disappears, the background job 208 is executed again from the task scheduler 242. If an IRQ occurs while executing any of the level "3" task groups from the level "0" task group, the process returns to the start step 222 of the IRQ processing program.

The first table shows the start of each task and its function.

[Table 1]

Table 1 is a program for managing the system of FIG. 5, which includes IRQ ANAL, TASK SCHEDULER, and EXIT. These programs (hereinafter referred to as OS) are held at addresses A000 to A300 of the ROM 104 as shown in FIG. In addition, there are programs of AD1 IN, AD1 ST, AD2 IN, and AD2 ST RPM IN as level "0" programs, which are activated by INTV IRQs generated every 10 (msec). As the level "1" program, there are CARBC, IGNCAL, and DWLCAL programs, which are activated by INTV IRQs that occur every 20 (m sec). As a level "2" program, there is a LAMBDA program, which is started by an INTV IRQ that occurs every 40 (m sec). As a level "3" program, there is a HOSEI program, which is activated by an INTV IRQ that occurs every 100 (m sec). There are also EGRCAL and FISC programs as backgroundzob. The level "0" program is PROG1 and is stored in addresses A700 to AAAA of the ROM 104 in FIG. 6, respectively.

The level "1" program is PROG2 and is stored in the ABFF at the address AB00 of the ROM 104. The level "2" program is stored from the addresses AE00 to AEFF of the ROM 104 as PROG3. The level "2" program is stored in the AFFF from the address AF00 of the ROM 104 as PROG4.

The background job program is stored in B000 to B1FF. Also, a list of star art addresses (hereinafter referred to as SFTMR) of each program from the programs PROG1 to PROG4 is stored in the address (B200 to B2FF), and from PROG1 to PROG4. A value indicating each program start cycle (hereinafter, referred to as TTM or less) is stored in address B300 at B3FF.

Other data are stored in address B400 to B4FF in the ROM of FIG. 6 as necessary. Subsequently, data ADV MAP, AF MAP, and EGR MAP for calculation are stored respectively.

The initial program 204 in FIG. 5 will be described in detail using FIG. In the step 282, a waiting area at the time of IRQ generation is set. Next, all of the RAM 106 is cleared by the staff 284. The staff 286 sets initial values in the registers of the input / output circuit 108. As the setting of the initial value, for example, the number of cylinders of the engine, the initial value of the angle sensor 146 or the DDR of the DIO 128, the setting of the timer for generating the INTV IRQ, the setting between the detectors for generating the ENST IRQ, and the engine speed There is a measurement time setting for detection.

Step 288 causes ADC1 to be triggered and releases the prohibition for ADC1 END IRQ. In this case, it jumps to the address A700 of FIG. 6 which is the star art and address of the AD1ST program. Thereby, the output of the battery voltage detection sensor VBS 132 which is one of the inputs of the MPX 162 of the ADC1 122 of FIG. 4 is selected and input to the ADC 164.

Returning to step 290, where we wait for the ADC1 END IRQ. When the operation of the ADC 164 is completed and the digital value is input to the REG 166, the operation completion of the ADC 164 is reported to the status register STATUS 198, and the ADC1 END IRQ is input to the CPU 102. As a result, the program AD1 IN is executed to take in the output of the battery voltage sensor 132.

In step 292, it is checked whether all values of λ S 142 are extracted from the VBS 132. Since the withdrawal of the input of the VBS 132 in this case is finished, the process returns to the staff 288. At this step 288, the AD1 ST program is started again, and the MPX 162 selects the output of the TWS 134 as the next input. After the analog-digital conversion of the output of the TWS 134 is finished, in step 292, the program AD1 IN withdrawal is executed, and the digital value of the output of the TWS 134 stored in the register REG 166 is retrieved and the ROM is retrieved. It is stored in the DATA area of 104. At the staff 292, the process returns to the staff 288 again. In this manner, the loop values from the staff 288 to the staff 292 are repeatedly executed, and the digital values of the outputs from the VBS 132 to the? S 142 are fetched sequentially, and when the extraction of the output values of the? S 142 is completed, the staff ( Proceed to 294). The ignition timing of the start is calculated by the staff 294.

This ignition timing Q _ADV (START) is calculated as a function of the temperature TW of the engine coolant. This function is shown in FIG. Q _ADV (START) is calculated in accordance with the characteristic of FIG. 9, and this calculation result is input to the register ADV 166 of the ADC of FIG.

In step 296, the opening degree of the air solenoid valve 22 at the time of lighting is calculated. This operation is performed based on the characteristics shown in FIG. 11 and the operation output is set in the register EGRD. In addition, a fixed value for the degree of opening of the air solenoid valve is set in the EGRP. The valve opening degree of the air solenoid valve 22 for starting the engine in FIG. 11 is stored in EGRP and is the ratio of the set value to the stop.

In step 298, the initial value of the fuel solenoid duty coefficient is calculated. This calculation value is performed by FIG. 10, and the ratio of the set value of the register FSCD to the set value of the register FSCP is shown as a characteristic diagram of FIG.

As data is set in the registers FSCP and FSCD, execution of the program INITIALIZ 204 in FIG. 5 ends, and the MONIT program 206 shown in FIG. 8 is executed. The program 206 starts from the step 302 and determines in step 302 whether the start switch 152 of FIG. 4 is on by monitoring the DIO5 input of the DIO 128. If the start switch 152 is in the ON state, the fifth bit DIO5 of the DIO 128 becomes high logic " H ". On the contrary, when turned off, the low logic "L" is obtained. If the engine is now before starting, the start switch is turned off, and the process proceeds from the step 302 to the step 312, where it is determined whether the program is after starting. This determination determines, for example, whether a start flag has been made. This start up marker is set in the staff 308. This start-up marker is set at a predetermined position in the RAM of FIG. Before startup, since the startup marker is not set, it is negative (NO) at the staff 312 and returns to the staff 302 again.

The routine routine is repeated between the step 302 and the step 312 until the start switch 152 is turned on. The start switch is monitored while following this path.

When the start switch is turned on and the judgment at the step 302 is affirmative (YES), the process proceeds to the step 304. At this point, it is determined whether the start switch is already on. In the case where the operation proceeds to the step 304, it is immediately after the start switch is detected to be turned on, so that the determination of the step 304 becomes negative (NO). The judgment of the staff 304 is also determined by whether or not the start mark is made. When the start mark is not shown, the judgment is made negative (NO), and the process proceeds to the step 306 to be ready for start-up.

For example, in the present embodiment, high logic "H" is set in the "0" bit of the DOUT register 194 of the DIO 128 to start the fuel pump 190.

Thereby the fuel pump is operated.

Next, in the step 306, the first bit of the DOUT register 194 is set to low logic "L". Thereby, the air solenoid valve 22 is controlled by the output of the EGRC circuit 178. In practice, the set of the "0" bit and the first bit of the DOUT register 194 are performed at the same time.

In step 308, the prohibition of the INTV IRQ is released, and the ignition output prohibition is released. The prohibition of this INTV IRQ is performed by, for example, setting the fourth bit (the flip-flop 739 in FIG. 22) of the MASK register 200 in FIG. The start mark is issued again by the staff 308. The start mark already indicates that the start switch is on, and the step 304 and the step 312 use this mark for judgment.

Since the step 310 starts the CABC 165, the IGNC 168, the FSC 176, the EGRC 178, etc., which are the outputs of the input / output circuit 108, a high logic " H " . This sends a pulse output to each control device.

Returning from the step 310 to the step 302, it is determined whether or not the start switch 152 is turned on in the step 302. During start-up, if the switch is on and is affirmative (YES), the process proceeds to the step 304. The start mark is checked at this step 304, and if it is marked, the start mark is regarded as being already started and the process returns to the step 302.

As described above, while the starting motor is being driven, the loop made by the positive YES of the staff 302 and the positive YES of the staff 304 is repeatedly performed.

Since the start switch 152 is turned off when the engine is started, determination of the step 302 proceeds to the step 312 when it is negative (NO). Since the start mark is checked at the staff 312 and the start marker is made, the process proceeds to the step 314. This step 314 releases the prohibition of ENST IRQ, and the engine stop after this step 316 can be detected by this ENST IRQ.

The program then proceeds to background job program 208. This program is shown in detail in FIG.

In FIG. 12, it is determined whether the no-load switch 148 is on in the step 410. If on, no exhaust gas reflux is performed.

Therefore, the process proceeds to the step 3412, where the air solenoid valve 22 is designated by setting the first bit of the register DOUT 194 of the DIO to low logic " L ". For this reason, the air solenoid valve 22 of FIG. 1 is controlled according to the value set in the register EGRD. The air solenoid valve 22 for controlling the air flow rate in the bypass passage is controlled according to a specific operating state. That is, in the case of winter operation at low temperature, start-up operation when the engine is cooled, and load on the engine, that is, when driving while using the car air conditioner, the air flow rate in the bypass passage is increased. At the step 414, the duty of the air solenoid valve 22 is set in the resistor EGRD according to the coolant temperature. Further, the fuel supply amount from the fuel solenoid valve according to the water temperature TW is set in the register FSCD. In accordance with these values, the fuel solenoid valve 20 and the air solenoid valve 22 are controlled to control the engine at no load. When the step 416 ends, the process proceeds to the step 410 and repeats this flow.

On the other hand, in the state where the no-load switch 148 is not on, the air solenoid valve 22 is not used, and exhaust gas reflux is performed instead. For this reason, the EGR apparatus 188 which controls the EGR amount is driven, and the first bit of the DOUT register 194 of the DIO is set to high logic " H " The EGR device 188 is driven to the set value. Next, at step 420, " 0 " is set in the register FSCD to stop the driving of the fuel solenoid 15. In the staff 422, it is determined whether or not a certain value of the cooling water temperature is higher than TA ° C, for example, and if it is high, the EGR operation is not performed. For this reason, the value for performing EGR CUT in the step 426 is set. If the cooling water temperature in the staff 422 is lower than a predetermined value (TA ° C), the process proceeds to the staff 424. In step 424, it is determined whether the cooling water temperature is lower than TB 占 폚. If it is low, the EGR CUT is set by the staff 426 by disabling the EGR operation as well. These values are set in the EGRD register at step 430.

On the other hand, when cooling water temperature TW is higher than TB degreeC and lower than TA degreeC, EGR is performed. The EGR amount at this time is determined according to the output VC of the negative pressure sensor 144 and the engine rotation speed (N).

The map MAP of the amount of EGR by the outputs VC and N is set at addresses B700 to B7FF of the ROM of FIG. 6, and is searched from this map to determine the amount of EGR. A search is made at step 428 and this value is set at register EGRD at step 430. The apparatus 188 shown in FIG. 4 is driven in accordance with the set value of this register EGRD.

In the flowchart illustrated in FIG. 12, the flow returns to the staff 410 as the staff 430 or the staff 416 ends. By doing so, the calculator always executes the flowchart art of the staff 410 through 416 for controlling the air solenoid valve 22 or the flowchart art of the staff from the staff 418 to the staff 430. There is a number. Therefore, if no occurrence of IRQ or the like occurs, the program starting from the start step 202 always continues to execute FISC or EGRCAL of the background job 208 via the INITIALIZ 204 and the MONIT 206. The MONIT 206 and the background job 208 generate an interruption request (IRQ) and can abort the processing. When the processing by the IRQ is finished, the execution of the program is resumed.

Next, the processing based on the generation of the IRQ will be described in FIG. The program 224 of factor analysis of IRQ is comprised of the process of ADC1 END IRQ 226, the process of ADC2 END IRQ 228, the process of INTV IRQ 230, the process of ENST IRQ 232, etc. have. In order to execute each of the programs 226, 228, 230, and 232, first, what is the content of the IRQ is examined. For this purpose, the contents of the STATUS register 198 of FIG. By looking at the contents of this STATUS register, it can be found that the IRQ is allowed. According to this occurrence factor, the respective programs 226, 228, 230, and 232 are executed, thereby executing in the TASKs 252, 254, 256, 258, and 256. A QUEUE is issued to this required TASK.

However, if the occurrence of the IRQ increases, the execution time of the management program (hereinafter referred to as OS) increases, and thus, there is a drawback that it is impossible to take a calculation time for actual engine control. Therefore, in this embodiment, ADC2 END IRQ 228 is generated only during the execution of INITIALIZ 204 or MONIT 206, but not otherwise. That is, the step 314 shown in FIG. 8 of the MONIT 206 sets the prohibition command low logic " L " of the ADC2 END IRQ in the MASK register 200 of FIG. 4 (flip-flop 766 in FIG. 22). . In addition, the ADC1 END IRQ 226 sets the MASK register so that it does not generate from the beginning, i.e., the IRQ generation prohibition state is set as the general reset signal of the input / output circuit so that all interruption is prevented at the start step 202. After that, the ADC1 END IRQ is set to the prohibited state by not issuing a command to release the inhibition.

A specific example of the program of the STATUS register 224 is shown in FIG. If it is determined that the ADC1 END IRQ has not occurred in the step 500 from the inlet start step 222 of the IRQ, the process proceeds to the step 502. Here, it is determined whether the generation request of the IRQ is the ADC2 END IRQ, and if it is YES, the staff 516 makes a pillar request to the program of the task level "0" task.

This sets a mark of " 1 " to b6 of the task control word TCWO in the RAM 106 shown in FIG. Thus, the process proceeds to TASK SCHEDULE 242. The reason why the ADC2 END IRQ occurs is that the program of the INITIALIZ 204 in FIG. 5 is running in this embodiment. Otherwise, ADC2 END IRQ is prohibited. If the judgment of the staff 502 is "Negative", the process proceeds to the staff 504.

In step 504, it is determined whether the factor of the IRQ is an INTV IRQ that occurs at a predetermined period.

If YES, go to staff 506. The step 506 to the step 514 have a function of judging whether or not the start timing of the program from the task level "0" to the task level "3" is started. First examine task level "0". The task control word of task level " 0 ", i.e., the counters b0 to b5 of TCWO in FIG. 15 increments 0 by +1. As described above, although the addition method is employed in this embodiment, the subtraction method may be employed. The staff 508 compares the value of the counter 0 of the TCWO with the task start timer TTMO of FIG. Here, "1" is applied to the TTMO. Here, the INTV IRQ is generated every 10 msec, so that "1" is applied to the TTMO indicates that the task level "0" program (252 in FIG. 5) is activated every 10 msec. The counter CNTRO and TTMO of FIG. 15 are compared at the staff 508 and are positive if they match. In this case, the process proceeds to the staff 510 and sets a marker " 1 " to b6 of the task control wared TCWO.

In this embodiment, b6 of each TCWO is set with the mark " 1 " of the start request of the task. The staff 510 sets the mark " 1 " to b6 of the TCWO, so that the counter CNTRO set to b0 to b5 of the TCWO is cleared.

In the step 512, the start timing search of the task level "1" is performed from the task level "0". In step 514, it is determined whether task level "3" is finished. In other words, it is determined whether n = 4. In this case, since n = 1, the process returns to the staff 506. In step 506, the content of counter CNTR1 of TCW1 in RAM 106 of FIG. 15, which is the task control word of the program at task level "1", is increased by +1. The staff 508 compares the TTM1 of the ROM 104 of FIG. 15. In this embodiment, the content of TTM1 is "2". That is, the lamp timing of the task level "1" is 20 msec. If it is assumed that the content of the counter CNTR1 is "1" at this time, the judgment of the staff 508 is "negative", that is, the task level 1 task 254 is judged that it is not the timing to proceed to the staff 512. Here, the task level retrieved again is updated, and then the task level becomes "2".

Similarly, if task level "3" is reached, n = 4 in step 512 and n = MAX in step 514 is satisfied. The process proceeds to task schedule 242. If the INTV IRQ is negated at the staff 504, the process proceeds to the staff 518. In this case, it is determined whether the ENST IRQ indicating the engine stops. If it is "negative" in the staff 504, it will necessarily be ENST IRQ, so the staff 518 may be omitted and the process proceeds to the staff 520. The staff 520 stops the fuel pump with a special program based on the engine stop, resets the signals of the ignition system and all the output systems of the fuel system, and returns to the start step 202 of FIG.

14 is a detailed flowchart art of the task schedule 242. It is determined whether the task level "n" needs to be executed by the staff 530. In the beginning, since n = 0, it is determined according to the necessity of executing the program of the task level "0". In other words, the existence of the request for registration is examined in order of the highest priority tasks. It can be determined by searching for b6 and b7 of the task control word TCWO. b6 indicates that the start request is "present" when "1" is set as the start request marker. In addition, b7 is a marker indicating execution, and if "1" is set here, it indicates that it is stopped at the present execution. Therefore, if " 1 " is set in at least one of b6 and b7, execution is required to proceed to the step 538.

The staff 538 determines the mark of b7. If b7 is " 1 ", the execution that has been interrupted by the staff 540 is resumed since the execution is interrupted. Even if the marks are set in both b6 and b7, if the judgment of the staff 538 is affirmed, the suspended program is restarted. When only b6 is " 1 ", the level start request marker, i.e., b6 is cleared by the staff 542, and the staff 544 sets a marker of b7 (hereinafter referred to as RUN marker). Steps 542 and 544 indicate that the process proceeds from the task level start request state to the execution state. The step 546 searches for the star art address of the task level program. This is obtained by the star art address table TSA set in correspondence with the TCW of each task level in the ROM 104 shown in Fig. 15, and the task is executed by jumping to this star art address.

Returning to Fig. 14, when it is judged as "negative" by the staff 530, this case indicates that the start request is not indicated in the search task level program and the execution is not interrupted. In this case, move on to the next task level search.

In other words, n of the task level becomes n + 1, and the level moves by one. Here, it is determined whether n is MAX, that is, 4 here, and if not 4, the process proceeds to the step 530 again. This is repeated, and when n = 4, it returns from the staff 536 to the background interruption interruption program.

In other words, the staff 536 turns out that it is not necessary to execute all programs up to task levels 0 to 3, and returns to the interruption interruption program of the background job before generating the IRQ.

FIG. 15 shows the relationship between the above-described task control word TCW and TTM indicating the task start cycle in the ROM and the task star art address table. There is a task start cycle TTM in the ROM corresponding to 0 to 3 of the task control word, and the counter CNTR of the TCW is continuously updated for each INTV IRQ, and the mark is set in b6 of the TCW by coinciding with the TTM of each task. By this marker, the star art addresses of two tasks are retrieved from the next task star art address TSA and jumped to the star art address to execute the selected programs of programs 1 to 4.

During execution of the task program, a mark is set at b7 of the TCW corresponding to the program in the RAM 106. While this marker is set, it can be determined that it is running. In this way, the program of the task scheduler 242 of FIG. 5 is executed. For example, any one of the programs 252 to 258 for 0 to 3 is executed.

If an IRQ occurs during the execution of this task, the task is stopped again to process the IRQ. If no IRQ occurs at this time, processing of the running task is finally terminated. This proceeds to EXIT 260 to report termination. The details of this EXIT program are shown in FIG. The program consists of staffs 562 and 564 for finding end tasks. In the steps 562 and 564, the task level is first found by searching from "0" of the task level to find the finished task level.

By this, the staff 568 advances, and the RUN marker of b7 of the control word of the task finished here is reset. This completes the execution of the program. The program then returns to the task scheduler to determine the next executable. The execution and interruption of the program is explained again in FIG. 17. If the background zov 208 having the lowest priority is being executed at this time, if INTV IRQ occurs at time t ₁ , execution is transferred to the management program (hereinafter referred to as OS program). In this case, the execution of the STATUS register 224 and the task scheduler 242 of FIG. 5 indicates that the level “0” task 252 is required to be executed. And " 1 " is set in b7 at time t ₂ and b6 is cleared and level " 0 " task 252 is executed. At the same time, if a program having a level "1" also has a start request, the marker "1" is also set in b6 of TCW1.

However, first, a high priority level 0 task 252 is executed. Time (t ₂₎ at the level Exiting the execution of zero task is the detection and execution preparation of reprogrammed to doedul agar TCWO b7 marker cleared by execution of a level "1", the next level of a task to the needs of the t ₄ Execution begins. If it takes time to process the task of level "1", the next INTV IRQ is issued again, and the program of level 1 is interrupted at t ₅ and returned to the OS program. The OS program is executed to make a start request to a program to be started with this INTV IRQ, for example, the level "0" task 252. And it executes the priority level, the highest level "0" task (252) to the time (t _6).

That is, the marker " 1 " is set in b7 of the TCWO and the marker in b6 is cleared to retrieve the star art address of the level " 0 " task 252 from TSAO and execute the level " 0 " task 252. At time t ₇ the execution of level “0” task 252 is finished and the program returns to clearing b7 of the TCWO at EXIT.

The task schedule 242 of the OS program searches for a start request or a stop program. The task scheduler 242 detects the interruption of the level "1" task 254 and executes the execution again. Level "1" of the restart task is carried out by CPU dulrim back to back in time (t ₈₎ that had been waiting, the contents of the CPU (102) in the time (t _5). When the level " 1 " task 254 is restarted and the execution is terminated at time t ₉ , the program returns to the OS program and executes the EXIT program, resulting in the end report of the program 254.

That is, it is clear the mark of the TCW b _{7 1.} Subsequently, by executing the task scheduler 242, it is searched whether or not there is a program whose start request is issued or a program which is stopped. For example, it is checked whether the mark "1" is set on b2 of TCW2 of the program 256. do. As a result, the TSA ₂ which is the star art address of the level "2" task 256 is searched for and jumped to the star art address of the program 256, and the level "2" task 256 of the program is executed. The clear mark of the TCW b _{6 2} as described above, and sets the mark of b7. When the execution of the level " 2 " task 256 of the program at the time t ₁₁ is completed, the program returns to the OS program to clear the TCW b7 mark by the program and reports the completion.

Then, the start request and the execution stop are searched again. If there is no start request or execution stop program by this search, each data is supplied to the CPU from the standby area of the background job 208 to be processed. When the INTV IRQ is entered at t 13, the contents of the CPU are transferred back to the waiting area, returned to the OS program, the IRQ request analysis is performed, and the program is requested to start again.

As can be seen from the above description, if an interruption of interruption occurs during the execution of each program, the program is stopped, and the program is returned to the program and executed from the highest level program. In this way, processing time is preferentially allocated to more important programs.

In addition, since each program is divided into levels according to the priority, each processing program included in each level is continuously executed, and the end of the overall processing is reported to the program of each level. It is minimal and the processing efficiency is improved. In this way, no interruption of intervention occurs for the programs in the same level, so that the standby area for interruption can be executed by setting each level to correspond to the program, so that the standby area is greatly reduced.

The execution status of the program of each level described in FIGS. 5 and 17, that is, the level "0" task 252, the level "1" task 254, the level "2" task 256, and the level 3 task 258 are shown. It is shown in FIG. The IDLE state is a waiting state for starting and no pillar request for a program is issued. The next time the start request is issued, it is set in the b6 of the TCW to indicate that start is required. The time to move from IDLE state to QUEUE state is determined by each program level. Even if the status is QUEUE, the order of execution depends on the priority.

The reason why the program enters the execution state is because the b6 mark of the TCW is cleared in the OS program and the b7 is set. This starts the execution of the program. This state is the RUN state. When the execution ends, the b7 marker of the TCW is cleared and the completion report is completed. This completes the RUN state and returns to the IDLE state, waiting for the next start request. However, if an IRQ occurs during program execution, that is, during RUN, the program must stop execution. As a result, the contents of the CPU are waited and execution is interrupted.

This state is READY state. The next time the interrupted program is run again, the contents of the waiting area are sent back to the CPU to resume execution. That is, it returns from the READY state to the RUN state again. In this way, each level program repeats four states of FIG. 18 is a representative flowchart, but it is possible that the marker " 1 " is set in b6 of the TCW in the READY state. This is the case, for example, when the next start request timing of a program comes to a stop during the stop. In this case, the b7 marker takes precedence and the task program that is suspended is executed first. As a result, the b7 marker is reset and the QUEUE state is not passed through the IDLE state by the b6 marker.

In this manner, each level program, that is, the level tasks 252, 254, 256, and 258, respectively, is in any one state of FIG. In addition, it is not possible for each level program to be in the READY state for each program, but for each level program. That is, for example, the level "1" task program is composed of the CARCB program shown in the first table, the IGNCAL program, or the DWLCAL program. Therefore, the READY state exists for the level "1" task program, but the READY state does not exist for each of the CARBC, IGNCAL, DWLCAL, and programs. Therefore, it is sufficient to have a standby area corresponding to each level program. The standby area 602 of the RAM 106 of Fig. 15 is set by the size corresponding to each level. FIG. 19 is a diagram showing a change in the state of a background jog. The state of the background job is in the RUN state while the IRQ is generated. When the interruption interruption processing ends, the waited contents are sent back to the CPU, and the execution resume state, that is, RUN. When waiting for the contents of the CPU due to the occurrence of the IRQ, the waiting area 602 shown in the RAM of FIG. 15 is waited.

20 is a program of level "0" tasks. This program has a maneuver requirement every 10m sec as shown in the first table. The step 650 pulls out the data of ADC1 and the step 654 makes a start request for pulling out the data of the next ADC1. In addition, the staff of 652 is to execute the ADC END IRQ before the light-up, and if the pre-starting mark is displayed, it is before start-up, so it returns to RT1, that is, the interrupt program. This program is INITIALIZ 204 in FIG. At step 656 the data of ADC2 is fetched and again at step 658 a start for the next data entry of ADC2 is set. The engine speed is extracted from the staff 660. When these staff are finished, the EXIT program of the OS is executed to clear the b7 mark of the TCW.

21 is a program of the level 1 task, and it is determined whether or not the step 672 is being started. If it is on, it does not need to be calculated by supplying starting fuel and determining the igniter time, and jumps to staff 678. The staff 674 executes the CARBCAL program for calculating the fuel, and the staff 676 then executes the IGNCAL program. These are each done by table lookup. The step 678 executes the DWALCAL program, and calculates the energization time using this. The LAMBDA program at level "2" is a correction program of?, And the HOSEI program at level "3" is a program of each correction coefficient. As the correction coefficient, for example, a program for obtaining correction coefficients such as air temperature and water temperature, and these parameters have a large specific time constant, so that the parameters may be counted at long time intervals.

As described above, the present invention issues an INTV IRQ so that all computational control is performed regardless of the engine speed. 22 shows a configuration of such an IRQ generation circuit. In the figure, data (for example, 10 msec) for setting the timer interruption stop period from the CPU is set via the data bus 752, and at the same time, the clock pulse CLOCK is input to the counter 736. The number of counts and the contents set in the register are compared in the comparator 737. When the contents of the register 735 and the contents of the counter 736 are the same, an output is generated in the comparator 737, and the flip-flop is generated. 738 and 740 are set.

At the same time, the counter 736 and the flip-flop 738 are reset to the output of the AND circuit 747. On the other hand, when the flip-flop 739 is set, the timer interruption stop signal IRQ is output via the AND circuit 748 and the OR circuit 751. The flip-flop 739 is a flip-flop for masking the IRQ when the IRQ signal is unnecessary (for example, during engine light). At this time, the reset instruction is sent to the flip-flop 739 from the CPU.

In addition, the engine failure (ENST) interruption interruption request when the engine is stopped, such as when the rotation of the engine stops due to a failure or an operation error during operation, is generated by the following configuration. This configuration is the same as in the case of timer interruption and is applied to registers 741, counters 742, comparators 743, AND circuits 749, 750, flip-flops 744, 745, 746. It is configured and the operation is the same as that described above. However, the signal input to the counter 742 is a signal generated when the engine is rotating, and is a reference angle signal REF of the crank generated from the sensor 146 shown in FIG. In the case of an engine, this signal is generated every time the crank turns 180 °. Since the counter 742 is reset while the RES signal is being applied, the engine failure intervention stop signal is not generated. When the engine stops, the engine failure intervention stop signal is generated because the REF signal is stopped and the reset is released. do.

The timer interruption interrupt IRQ as described above triggers the start of the task, as shown in the flowchart art of FIG. 5 described above, and the task priority processing is performed. That is, the CPU receives an interruption request and makes a determination of the interruption request. If this is the interruption of the timer, the task group 252, 254, 256, and 258 whose levels are sorted in order of high priority are triggered to execute the task selected by the task scheduler 242. Is done. When task execution ends, it is reported to exit from EXIT, and the next task is selected by the next timer interruption and task schedule again. On the other hand, when the interruption is an interruption of engine failure, the fuel pump is turned off and the ignition device is reset to disable all of the input / output control circuits.

The ADC1 END IRQ and the ADC2 END IRQ are also the same, and "1" is set in the flip-flop 764 when the ADC's sequencing operation ends. When " 1 " is set in the flip-flop 762 via the bus line 752 from the CPU, the AND gate 770 is enabled and requests the service of the ADC1 END IRQ to the CPU via the OR gate IRQ. However, if "1" is not set in the flip-flop 762, the ADC1 END IRQ is prohibited. The same applies to ADC2, and "1" is set in the flip-flop 768 at the end of the psychon of ADC2.

At this time, if "1" is set in the flip-flop 766, the ADC2 END IRQ is generated by the AND gate 772 and the OR gate 751, but if "1" is not set in the flip-flop 766, AND Since gate 772 is disabled, ADC2 END IRQ does not occur. Therefore, IRQ only for setting "1" to flip-flops 739, 745, 762, and 766 is generated. If "0" is set, the IRQ is prohibited.

As described above, according to the present invention, the priority is determined according to the processing function of the program shown in the first table. Then, a request for output is output at a time interval of a predetermined parameter according to the priority. In this way, the main task of engine control is started at a fixed time interval regardless of the engine rotation speed, so that the load of the CPU hardly changes even when the engine state changes, and high-performance control is possible at all times.

Further, according to the embodiment of Fig. 5, since the start cycle is changed for each level program, the control efficiency is further improved. In addition, since the EXIT is reported at the end of the program at the same level, the execution of the OS program is not required to proceed to the next program within the same level. Therefore, the processing time is faster. As a result, the interruption of the intervention of the programs in the same level is not mutually interrupted. Therefore, the waiting area may be set according to each task level, so the area may be small.

After the engine is started, the interruption of the ADC1END interruption or the interruption of the ADC2END interruption is masked, thereby reducing the execution time of the OS program and improving the processing efficiency. According to the embodiment shown in FIG. 15, the TCW may be set for each level, and the TCW area may be small because it is not necessary to set for each program of the first table. In the TCW, a mark b6 indicating a start request and a mark b7 indicating execution are set. As shown in FIG. 17 and FIG. 18, execution, interruption, and resumption of a program can be performed smoothly and the priority can be increased. Control efficiency is improved.

Next, a second embodiment in which the present invention is applied to a fuel injection type internal combustion engine will be described with reference to FIGS. 23 to 33. FIG. Since the type of the internal combustion engine is different from the first embodiment and the second embodiment, it is the same except for the differences described below.

In particular, the essential control method of the present invention is almost the same. FIG. 23 shows the control of the entire engine system. In the drawing, intake air is supplied to the cylinder 1008 via the air cleaner 1002, the throttle chamber 1004, and the intake pipe 1006. The gas burned in the cylinder 1008 is discharged from the cylinder 1008 to the atmosphere through the exhaust pipe 1010.

The throttle chamber 1004 is provided with an injector 1012 for injecting fuel, and the fuel ejected from the injector 1012 is mixed with the intake air while being sprayed in the air passage of the throttle chamber 1004 to mix the mixer. This mixer is supplied to the combustion chamber of cylinder 1008 by opening the valve of intake valve 1020 through intake pipe 1006.

Throttle valves 1014 and 1016 are provided near the outlet of the injector 1012. The throttle valve 1014 is configured to mechanically interlock with the accelerator pedal and is driven by the driver. On the other hand, the throttle valve 1016 is arranged to be driven by the diaphragm 1018 and is fully closed in a region where the air flow rate is small, so that the negative pressure in the diaphragm 1018 increases as the air flow rate increases, thereby the throttle valve 1016 ) Starts to open and suppresses the increase in suction resistance. An air passage 1022 is provided upstream of the throttle valves 1014 and 1016 of the throttle chamber 4, and an electric heating element 1024 composed of a thermocouple air flow device is disposed in the air passage 1022. From the relationship between the air flow rate and the heat transfer amount of the heating element, an electric signal which changes according to the predetermined air flow rate is drawn out. Since the heating element 1024 is provided in the bypass air passage 1022, the heating element 1024 is protected from the hot gas generated at the time of the back fire of the cylinder 1008, and is also protected from being contaminated by dust or the like in the intake air. The exit of the bypass air passage 1022 is formed near the maximum narrow portion of the venturi, and the inlet thereof is formed upstream of the venturi. The fuel supplied to the injector 1012 is supplied from the fuel tank 1030 to the fuel pressure regulator 1038 via the fuel pump 1032, the fuel damper 1034, and the filter 1036. On the other hand, from the fuel pressure regulator 1038, pressurized fuel is supplied to the injector 1012 via a pipe 1040, and the pressure of the intake pipe 1006 to which urine fuel is injected from the injector 1012 and the injector ( The fuel is returned from the fuel pressure regulator 1038 to the fuel tank 1030 via the feedback pipe 1042 so that the difference in fuel pressure at 1012 is always constant. The mixer sucked from the intake valve 1020 is compressed by the piston 1050 and burned by the spark that is generated in the ignition plaque 1052, which is converted into cloud energy. The cylinder 1008 is cooled by the cooling water 1054, and the temperature of this cooling water is measured by the water temperature sensor 1056, and this measured value is used as the engine temperature. The ignition flag 1052 is supplied with a high voltage from the ignition coil 1058 in accordance with the ignition timing.

The crankshaft (not shown) is provided with a crank angle sensor for generating a reference angle signal and a position signal at every reference crank angle or at a predetermined angle (for example, 0.5 degrees) according to the rotation of the engine. The output of this crank angle sensor, the output 1056A of the water temperature sensor 1056, and the electric signal from the heating element 1024 are input to a control circuit 1064 composed of a microcomputer or the like, and the control circuit 1064 The injector 1012 and the ignition coil 1058 are bulbated by the output of the control circuit 1064.

In the engine apparatus controlled by the above configuration, the throttle chamber 1004 is provided with a bypass passage 1026 which communicates with the intake pipe 1006 via the throttle valve 1016 of the throttle, and the bypass passage 1026. ) Is provided with a bypass valve 1062 which is controlled to open and close. A control input of the control circuit 1064 is supplied to drive the bypass valve 1062 to open and close the valve.

The bypass valve 1062 is provided in the bypass passage 1026 provided by bypassing the throttle valve 1016 and is controlled to open and close by a pulse current. This bypass valve 1062 changes the cross-sectional area of the bypass passage 1026 by the bias amount of the valve, which causes the drive to be driven controlled by the output of the control circuit 1064.

That is, the control circuit 1064 generates an open / close cycle signal for controlling the drive device, and the drive device transmits a control signal for adjusting the bias amount of the bypass valve 1064 by the open / close cycle signal. 1062).

24 is an overall configuration diagram of the control device. In Fig. 24, the same or identical components as those in Fig. 4 have the same reference numerals as in Fig. 4. 4 and other components will be described only.

The output of the heating element 1024 (hereinafter referred to as AFS) constituted by the flow sensor is input to the ADC 2, and is digitally converted through the analog-digital conversion circuit 172 (hereinafter referred to as ADC) to register 174 (hereinafter referred to as REG). Set).

Next, the pulse output circuit and the control target based on the CPU calculation result will be described. The injector control circuit (called INJC) is a circuit for converting the digital value of the calculation result into a pulse output. Therefore, a pulse having a pulse width corresponding to the fuel injection amount is produced at the INJC 1134 and applied to the injector 1012 via the AND gate 1136.

The ignition pulse generation circuit 1138 (hereinafter referred to as IGNC) has a register for setting the ignition timing (ADV) and a register for setting the ignition coil primary current start time (called DWL). The data is set. The pulse is generated based on the set data and is applied to the amplifier 62 described above with reference to the amplifier 62 via the AND gate 1140.

The valve opening degree of the bypass valve 1062 is controlled by a pulse supplied from the control circuit (hereinafter referred to as ISCC) 1142 via the AND gate 1144. The ISCC 1142 has a register ISCD for setting a pulse lock and a register ISCP for setting a repetitive pulse period.

A register for setting a value representing the duty cycle of the pulse in the EGR amount control pulse generating circuit 178 (hereinafter referred to as EGRC) to control the transistor 90 that alternately controls the EGR control valve 86 shown in FIG. It has a register EGRP that sets the sitter EGRD and a value representing the repetition period of the pulse. The output pulse of this EGRC is applied to the transistor 90 via the AND gate 1156.

In addition, the 1-bit input / output signal is controlled by the circuit DIO 128. The input signals include IDLE-SW signals, TOP-SW signals, and START-SW signals. As an output signal, there is a pulse output signal for driving the fuel pump. This DIO is provided with a register DDR 192 for deciding whether to use a terminal as an input terminal or an output terminal, and a register DOUT 194 for latching output data.

The mode register 1160 is an instruction memory register (hereinafter referred to as MOD) for instructing various states inside the input / output circuit 108. For example, the AND registers 1136 and 1140 are set by setting an instruction in the mode register 1160. , 1144 and 1156 are all in this cable state or are in a disabled state. In this way, by setting an instruction in the mode register 1160, generation and termination of output signals of INJC, IGNC, and ISCC can be controlled.

The level "1" task program CARBC in the above-mentioned first table showing the start of each task and its function is unnecessary in this embodiment without using a carburetor, and the program INJC must be replaced instead. This program INJC uses the calculation of fuel injection amount as its function, and the pillar of the program is performed by INTV IRQ which is an interruption factor that occurs every 20 msec. Other programs are the same as those in the first embodiment.

In terms of differences from the INITIALIZ program shown in FIG. 7 of the first embodiment, in step 290 of FIG. 25, when the analog-digital conversion of the output of the sensor 1056 is completed, the program AD1IN is executed again to register REG. The digital value of the output of the water temperature sensor TWS 134 set in 166 is taken out and stored in the DATA area of the ROM 104 as in the first embodiment. The step 296 'calculates the degree of opening of the air bypass valve 1062 at startup. This calculation is performed based on the characteristics shown in FIG. 11 as in the first embodiment, and this phosphoric acid output is set in the register ISCD.

In the step 298 ', the initial value of the fuel injection time is calculated. This calculated value is traversed by FIG. 26 and set in the register INJD1. FIG. 26 shows a preset value of the fuel injection amount with respect to the water temperature. This figure corresponds to FIG. 10 of the first embodiment.

The background job program is executed in accordance with the flucha art shown in FIG. In FIG. 27, the staff 410 determines whether the IDLE-SW 148 is on. If it is on, exhaust gas reflux cannot be performed.

Therefore, the process proceeds to step 412, where "0" is set in the EGRD register. The duty cycle of the air bypass valve 1062 is determined by the step 414 according to the cooling water temperature, and the step 416 sets the duty cycle in the ISCD register. This set value determines the amount of air bypass to the engine. As the staff 416 ends, the process proceeds to the staff 410 again, and the staff is repeated in this Peruup unless a request of the IRQ service is issued to the CPU.

On the other hand, ISC cannot be executed when IDLE-SW is turned off. Therefore, the staff 420 sets "0" in the ISCD register. In this state, the EGR amount is calculated. For this reason, it is judged whether cooling water temperature TW is higher than fixed temperature TA degreeC. If high, go to step 426 to set the EGR to the CUT state and set "0" to the EGRD register.

If the TW is lower than the TA, the process proceeds to the step 424 to determine whether the temperature is lower than the predetermined temperature TB and to cut the EGR even when the TW is lower. Therefore, the process proceeds to the step 426, where "0" is set in the EGRD. The temperature level TA of the staff 422 represents the upper limit temperature, while the TB of the staff 424 represents the lower limit temperature, and the EGR operation is performed only in the temperature range therebetween. Therefore, in the range between these steps, the process proceeds to the step 428, where the amount of EGR is calculated by the map search from the intake air amount and the engine rotation speed N.

The map for this is described in addresses B700-B7FF of the ROM of FIG. This search value is set in the EGRD register at step 430. As a result, the EGR valve is opened at the value due to the duty cycle of the EGRD register and the EGRP register set in advance, and EGR is performed.

In the flowchart shown in FIG. 27, as the step 430 or the step 416 ends, the flow returns to the step 410 again. By doing so, the calculator is a step 410 for controlling the air bypass valve 1062, the flow chart art from the step 416, or the step 420 to the step 430 for controlling the EGR amount. Always execute the step flow chart art.

Therefore, if the occurrence of IRQ or the like does not occur as in the first embodiment, the program starting from the start step 202 (FIG. 5) passes through the INITIALIZ 204 and the MONIT 206, and the background job 208 is ISCCO. The program or the EGRCON program is always executed.

28 is a flowchart art for executing a task program of level " 1 ". It is determined whether or not the step 672 is being started. In case of starting, it is not necessary to calculate in this program group because fuel or ignition timing is started by other program. Therefore, when the prohibition of INTV IRQ is released in step 308 and 310 of the MONIT program of FIG. 8 and the SFTMRI program group is started, the start mark is set. ), The step 678 calculates the primary current energization time of the ignition coil to complete the calculation of this program group. If it is not starting, the process proceeds from the step 672 to the step 674. In this step 674, an INJC program is executed. Here, the fuel injection amount is calculated by the AF map shown in FIG. 6 from the intake air amount and engine rotation speed N obtained by SFTMR. The injection amount is corrected as other factors by the LAMBDA program, other corrections are made by the HOSEI program, and the value is set in the INJD register. Upon completion of the program of INJD, the staff 676 executes the IGNCAL program. Since the IGNCAL program is executed, the ignition timing is obtained based on the coefficients QA and N retrieved from the map shown in FIG. 6, and the operation result is set in the ADV register. Upon completion of the IGNCAL program, the process proceeds to the step 678 to execute the DWLCAL program, to obtain the starting point of the primary coil current energization of the ignition coil, and to store the value in the DWL register.

The execution of each of the programs of INJC, IGNCAL, and DWLCAL is terminated, and the end report is jumped to the exit program for the end report.

FIG. 29 is a detailed view of CABC 165, FSC 176, EGRC 178, and ISCC 1142 and EGRC 178 of FIG. In this figure, each register of CABD, FSCD, ISCD, and EGRD represents a pulse width, which corresponds to the register 802. There is also a register 806 corresponding to CABP, FSCP, IFSCP and EGRP.

It is assumed that high logic "H" is set in bit bo of the mode register 1160 at this time. For this reason, AND gate 1144 (Fig. 24) and 816 are in an operating state together. The timer 804 composed of the counter circuit counts the clock from the AND gate 816. The count value B is compared with the value of the register 806 in the comparator 810 so that the timer 804 is cleared when the value of the count value B becomes equal to or greater than the value of the register 806. Therefore, the timer 804 repeats the counting at a period determined by the value C of the register 806.

In addition, the count value of the timer 804 is compared in the comparator 808 with the value of the register 802. At this time, the flip-flop 812 is set under the condition that the value A of the register 802 is larger than the count value B of the timer 804, and is reset under the condition that the value B becomes A or more. For this reason, the set time of the flip-flop 812 is determined according to the value A of the register 802. By increasing this value A, the set time of the flip-flop 812 becomes long.

As described above, since the count of the timer 804 is repeated at a frequency corresponding to the set value of the register 806, the set output of the flip-flop 812 is repeatedly repeated according to the period by the set value of the register 806. Is output. Since the bo bit of the mode register 1160 (FIG. 24) is a high logic " H " level, it is output via the AND gate 1144. When bo of the mode register 1160 is set to a low logic "L", the gates 1144 and 816 are disabled, the output of the flip-flop 812 is stopped, and the input to the timer 804 is also stopped.

Therefore, the start or stop of the circuit operation of FIG. 29 can be controlled by setting the control data from the CPU in the mode register shown in FIG. FIG. 29 shows an example in which the AND gates 1144 and 816 are controlled by bo in the mode register, but bo is a bit for controlling the ISCD of the ISCC 1142 of FIG. The EGRC 178 of FIG. 24 is the same as that of FIG. 29, but the start and stop of operation of 1142 are controlled by the bo bit of the mode register and the EGRC 178 is controlled by the b2 bit.

30 is a detailed view of the IGNC 168 of FIG. 4 or the IGNC 1138 of FIG. Data for controlling the primary current energization start time of the ignition coil from the CPU is set in the DWL register, and data indicating the ignition timing is set in the ADV register. Now, the set value of the DWL register 1168 is called A. The set value of the ADV register 1169 is C.

If the b1 bit of the mode register 1160 is now high logic " H ", the AND gates 1156 and 860 are in a state of transmitting a signal and the POS pulse is passed to the counter 850 via the AND gate 860. Is entered. For this reason, the count value of this counter 850 is increased by the engine crank angle and cleared by the REF pulse indicating the reference angle. This count is referred to as B. When the count value is small, the output of A> B of the comparator 852 is supplied to the flip flop 856 via the OR gate, and the flip flop 856 is reset.

B출력에 의하여 플립플롭(856)은 다시 리세트된다. 이로 인하여 AND게이트(858)으로부터 펄스출력은 개입중단되고 점화를 위한 스파이크가 발생된다.Therefore, no pulse output comes from the AND gate 1156. If the count value of the counter 850 increases, the flip-flop 856 is set by the output from the AND gate 864 when the count value of the count 850 becomes larger than the set value of the DWL register 1168. This set output is applied to the ignition device via the gate 1156, and a primary current flows through the ignition coil. If the count is higher, C in comparator 854

Flip-flop 856 is reset again by the B output. This interrupts the pulse output from the AND gate 858 and generates spikes for ignition.

DIO 128 in FIG. 4 and DIO 128 in FIG. 24 are shown in detail in FIG. In this figure, DDR determines whether the input / output ports DIOO to DEO7 of the DIO are placed in an input state or an output state.

The signal from the bit in which the high logic " H " of the DDR is set is applied to the corresponding tri-state drivers 872 to 886 so that the tri-state driver is in a conductive state. As a result, the bits of DOUT corresponding to the bits of the high logic " H " of DDR are output through the corresponding question state.

On the other hand, the signals of the lines DIOO to DIO7 can be freely read from the CPU via the buffer amplifiers 892 to 904. Since the signal of the line corresponding to the ternary state driver which is in a negative conduction among the ternary state drivers 872 to 856 depends on the external state, the external state can be read out for this line.

FIG. 32 is a detailed view of the INJC 1134 of FIG. 24, wherein the REF pulse from the crank angle sensor occurs at a constant angle immediately before the top dead center of the crank angle (for example, 80 degrees or 90 degrees). A relationship between the top dead center (TDC) of the crank angle and REF is shown in FIGS.

The gates 910, 912, 1136 (FIG. 24) are put into a conductive state since it is now assumed that the b4 bit of the mode register 1160 has a high logic " H ". For this reason, the count value of the counter 904 is cleared every REF pulse as shown in FIG. The register 902 is a register for receiving and storing a value A for determining the fuel injection start point from the CPU.

D인 조건에서 플 립플롭(920)이 세트되고 AND게이트(1136)로부터의 분사용 펄스는 정지한다.The value A of the register 902 is compared by the comparator 906 with the count B and set to the flip-flop 908. When the flip-flop 908 is set, a pulse is sent from the gate 1136 and supplied to the injection valve 1012. In addition, the timer 916 which is triggered by the gate 912 and counts a clock pulse. The INJD register 914 is the INJD register of FIG. 24, and the valve is opened for a time corresponding to the set value C of this register. That is, the flip-flop 920 is set while the count value D of the timer 916 is smaller than C, but C

In the condition D, the flip-flop 920 is set and the injection pulse from the AND gate 1136 stops.

In this way, the starting point of the fuel injection and the opening time of the valve are controlled. Further, by setting the low logic " 0 " (L) of the mode register 1160, the output of the gate 1136 and all the operations can be stopped. As described above, according to the present invention, since the CPU can freely control the start and stop of the operation of the output system, no malfunction occurs. First, an initial value for operating the input circuit of the input / output circuit, for example, a set of set values for measuring the engine rotation speed, designation of the input / output of each bit of the DIO, and the like, and the input / output circuit 108 provides a service to the CPU 102. Set the conditions of the IRQ for requesting or release the IRQ of the input circuit. Next, withdrawal of input required for start-up and calculation of the set value for start-up based on that are performed. After setting these set values in each register of the input / output circuit 108, the starter is monitored. The start of the starter is confirmed and the output side device of the input / output circuit 108 is started. In this way, the preparation for starting the engine is made in advance, so that the output side device can be started regardless of the start, and the output device is stopped until the start. Therefore, the engine control device is not malfunctioned. In addition, power consumption is low, and heat generation of the input / output circuit 108 and the amplifier for amplifying the output is also suppressed.

In addition, since the prohibition of INTV IRQ is canceled by the staff 308 of the MONIT program of FIG. 8, the INTV IRQ is received during startup, i.e., during the execution of the Perupu produced by the processes of the staff 302 and the staff 304. Based on the INTV IRQ, the CPU 102 performs a more important task. As a result, calculation results can be set based on new inputs from the registers IDJD, ADV, DWL, ISCD, and EGRD of the input / output system. Since the battery voltage is changed by the start of the starter motor, it is very important to quickly change the setting value of the register of the output meter according to the change, and this becomes possible.

According to the present invention, calculation of fuel injection is performed by interrupting the timer, so that the load of the computing device is stable regardless of the engine state.

Claims (1)

As the processor performs a number of tasks, it generates an output signal and the function of these tasks affects processor-controlled engine operation. Through the execution of the tasks, these tasks have a number of task programs. In an electronic engine control method, the method comprises: (a) generating a continuous interruption signal to which a processor responds during execution of a task program; and in response to each interruption signal, requesting to execute a current task program in memory. (B) storing the execution request signal, and searching for the memory as soon as the memory of the execution request signal is finished in step (b) to confirm the existence of the execution request signal, and in step (b) (C) starting the execution of the selected task program stored therein. Electronic engine control method.

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