KR840005255A - Error pulse train detector - Google Patents

Error pulse train detector Download PDF

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Publication number
KR840005255A
KR840005255A KR1019830002467A KR830002467A KR840005255A KR 840005255 A KR840005255 A KR 840005255A KR 1019830002467 A KR1019830002467 A KR 1019830002467A KR 830002467 A KR830002467 A KR 830002467A KR 840005255 A KR840005255 A KR 840005255A
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South Korea
Prior art keywords
stage
output
pulse
error signal
detecting
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KR1019830002467A
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Korean (ko)
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KR870001117B1 (en
Inventor
로페즈 드 로마나 에두아르도
Original Assignee
로늘드 제이클라크
디스커비젼 어소시에이츠
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Publication of KR840005255A publication Critical patent/KR840005255A/en
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Publication of KR870001117B1 publication Critical patent/KR870001117B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
    • G11B19/20—Driving; Starting; Stopping; Control thereof
    • G11B19/28—Speed controlling, regulating, or indicating
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
    • G05D13/00—Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover
    • G05D13/62—Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover characterised by the use of electric means, e.g. use of a tachometric dynamo, use of a transducer converting an electric value into a displacement
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
    • H02P23/18—Controlling the angular speed together with angular position or phase
    • H02P23/186—Controlling the angular speed together with angular position or phase of one shaft by controlling the prime mover
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence

Abstract

내용 없음No content

Description

오차 펄스 열 검지기Error Pulse Thermal Detector

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 위상 검파기술을 이용하여 스핀들 모우터의 속도를 제어하기 위한 종래의 스핀들 서어보시스템을 나타내는 블록 다이어그램.1 is a block diagram showing a conventional spindle servo system for controlling the speed of a spindle motor using a phase detection technique.

제2도는 제1도에 도시된 종래의 스핀들 서어보 제어회로를 본 발명의 원리에 따라 변형시킨 것으로서, 스핀들모우터의 속도를 본 발명에 따른 펄스폭 변조 검파 계획내에 정확하게 유지시키기 위한 3단 쉬프트 레지스터와 기준펄스 및 회전속도계 펄스가 사용되고 있음을 나타내는 블록 다이어그램.2 is a variation of the conventional spindle servo control circuit shown in FIG. 1 in accordance with the principles of the present invention, wherein a three-stage shift for accurately maintaining the speed of the spindle motor within the pulse width modulation detection plan according to the present invention; Block diagram showing register and reference pulses and tachometer pulses being used.

제3도는 본 발명에 따른 펄스 드롭아우트 검지기를 구체적으로 나타내는 블록 다이어그램.3 is a block diagram specifically showing a pulse dropout detector according to the present invention.

제4도는 기준펄스 및 회전속도계 펄스, 그리고 스핀들 모우터의 속도를 제어하기 위해 펄스폭 변조된 출력을 발생시키는 상기 펄스들 사이의 관계를 나타내는 파형도.4 is a waveform diagram showing a relationship between a reference pulse and a tachometer pulse and the pulses generating a pulse width modulated output to control the speed of the spindle motor.

제5도는 제3도에 도시된 3단 쉬프트 레지스터에 가해지는 기준펄스와 회전속도계 펄스가 적절하게 배향된 경우 및 부적절하게 배향된 경우에 이 3단 쉬프트 레지스터의 각단의 논리적 상태 및 NAND 출력상태를 나타내는 진리표.5 shows the logical and NAND output states of each stage of the three-stage shift register when the reference and tachometer pulses applied to the three-stage shift register shown in FIG. 3 are properly oriented and improperly oriented. Truth table representing.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

9 : 스핀들 모우터 서어보 11 : 비디오 디스크9: spindle motor servo 11: video disc

29 : 3단 쉬프트 레지스터 A : 3단 쉬프트 레지스터의 제1단29: 3-stage shift register A: First stage of 3-stage shift register

B : 3단 쉬프트 레지스터의 제2단 C : 3단 쉬프트 레지스터의 제3단B: 2nd stage of 3rd stage shift register C: 3rd stage of 3rd stage shift register

31 : 회전속도계 펄스 발생장치 33,35 : 펄스발생장치31: tachometer pulse generator 33,35: pulse generator

37 : 등각속도 기준 오실레이터 38 : 등선속도/등각속도 선택장치37: Isometric velocity reference oscillator 38: Isometric speed / isometric speed selection device

39 : 전압제어식 오실레이터 83 : 원쇼트 멀티바이브레이터39: voltage controlled oscillator 83: one-shot multivibrator

Claims (8)

2개 방향으로의 이동이 가능한 3단 프쉬트 레지스터를 설치하고, 이 쉬프트 레지스터의 제1단에 0을 부하하고 이 쉬프트 레지스터의 제3단에 1을 부하하고, 제1단에 부하된 0을 제1펄스열과 함께 제3단쪽으로 이동시키고, 제3단에 부하된 1을 제2펄스열과 함께 제1단쪽으로 이동시키고, 상기 제1단과 제3단으로부터 동일한 출력이 발생되는가을 검지하여서 이들 제1단과 제3단으로부터 동일한 출력이 검지될 경우에 출력 오차신호를 발생시키는 단계로 구성되는, 제1펄스열의 펄스들과 제2펄스열의 펄스들이 시간적으로 교대로 발생하도록 되어있는 제1 및 제2펄스열중의 어느 하나의 펄스열내에 펄스가 존재하지 않거나 혹은 부가된 것을 검지하는 방법.A 3-stage shift register capable of moving in two directions is provided, 0 is loaded in the first stage of the shift register, 1 is loaded in the third stage of the shift register, and 0 loaded in the first stage is loaded. The first pulse train is moved toward the third end, the first load is moved to the first end together with the second pulse train, and the first output and the third stage are detected to detect whether the same output is generated. First and second pulses of the first pulse string and pulses of the second pulse string, which are configured to generate an output error signal when the same output from the first stage and the third stage is detected. A method for detecting the absence or addition of a pulse in one of the pulse trains. 제1항에 있어서, 상기 제1단과 제3단으로부터의 출력을 검지하여 출력 오차신호를 발생시키는 단계에 제1단의 출력상태를 역전시키고 이와 같이 역전된 출력을 제3단의 출력과 함계 논리적으로 NAND시킴이 포함되는 방법The method of claim 1, wherein the output state of the first stage is reversed in the step of detecting the outputs from the first stage and the third stage and generating an output error signal. How NAND is Included 제1항에 있어서 상기 제1단과 제3단으로부터의 출력을 검지하여 출력 오차신호를 발생시키는 단계에, 고정된 폭을 갖는 펄스를 상기 출력 오차신호의 선단(leading edge)과 일치하게 발생시킴이 포함되는 방법.The method of claim 1, wherein detecting the output from the first and third stages to generate an output error signal, generating a pulse having a fixed width coinciding with a leading edge of the output error signal. Method included. 제1항에 있어서 상기 제1단과 제3단으로부터의 출력을 검지하여 출력 오차신호를 발생시키는 단계에, 제3단의 출력상태를 역전시키고 이와 같이 역전된 출력을 제1단의 출력과 함께 논리적으로 OR시킴이 포함되는 방법The method of claim 1, wherein the step of detecting the outputs from the first and third stages to generate an output error signal includes: inverting the output state of the third stage and logically converting the inverted output together with the output of the first stage. How ORing Is Included 2개 방향으로의 이동이 가능한 3단 쉬프트 레지스터와 , 이 쉬프트 레지스터의 제1단에 0을 부하시키기 위한 수단과, 이 쉬프트 레지스터의 제3단에 1을 부하시키기 위한 수단과, 제1단에 부하된 0을 제1펄스열과 함계 제3단쪽으로 이동시키기 위한 수단과, 제3단에 부하된 1을 제2펄스열과 함께 제1단쪽으로 이동시키기 위한 수단과, 상기제1단과 제3단으로부터 동일한 출력이 발생되는가를 검지하여서 이들 제 1 단과 제 3 단으로부터 동일할 출력이 검지될 경우에 출력 오차신호를 발생시키기 위한 수단으로 구성되는, 제1펄스열의 펄스들과 제2펄스열의 펄스들이 시간적으로 교대로 발생하도록 되어있는 제1및 제2펄스열중의 어느 하나의 펄스열내에 펄스가 존재하지 않거나 혹은 부가된 것을 검지하기 위한 펄스 드롭아우트 검지기.A three-stage shift register capable of moving in two directions, means for loading zeros into the first stage of the shift register, means for loading one into the third stage of the shift register, and a first stage Means for moving the loaded zero toward the first stage with the first pulse train and the third stage; means for moving the one loaded at the third stage with the second pulse train toward the first end; and from the first and third stages, The pulses of the first pulse train and the pulses of the second pulse train, which are configured to generate an output error signal when the same output is detected from these first and third stages by detecting whether the same output is generated, A pulse dropout detector for detecting that a pulse does not exist or has been added to any one of the first and second pulse trains, which are to be generated alternately. 제5항에 있어서, 상기 제1단과 제3단으로부터의 출력을 검지하여 출력 오차신호를 발생시키기 위한 수단에, 제1단의 출력상태를 역전시키기 위한 인버어터와, 이와같이 역전된 출력을 제3단의 출력과 함께 논리적으로 NAND시키기 위한 NAND게이트가 포함되는 장치.6. The apparatus of claim 5, further comprising: an inverter for reversing the output state of the first stage and means for detecting the output from the first and third stages to generate an output error signal; Device that includes a NAND gate for logically NAND with the output of the stage. 제5항에 있어서, 상기 제1단과 제3단으로 부터의 출력을 검지하여 출력 오차신호를 발생시키기 위한 수단에, 고정된 폭을 갖는 펄스를 상기 출력 오차신호의 선단과 일치하게 발생시키기 위한 펄스 발생수단이 포함되는 장치.6. The apparatus according to claim 5, wherein the means for detecting the outputs from the first and third stages to generate an output error signal, wherein the pulses for generating a pulse having a fixed width coincident with the leading end of the output error signal. Apparatus comprising a generating means. 제5항에 있어서, 상기 제1단과 제3단으로부터의 출력을 검지하여 출력 오차신호를 발생시키기 위한 수단에, 제3단의 출력상태를 역전시키기 위한 인버어터와, 이와 같이 역전된 출력을 제1단의 출력과 함께 논리적으로 OR시키기 위한 OR 게이트가 포함되는 장치.6. The apparatus of claim 5, further comprising: an inverter for reversing the output state of the third stage and means for detecting the output from the first and third stages to generate an output error signal. Device with OR gate to logically OR with one stage of output. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019830002467A 1982-06-04 1983-06-02 Erroneous pulse sequence detector KR870001117B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US06/385,171 US4465977A (en) 1982-06-04 1982-06-04 Erroneous pulse sequence detector
US385,171 1982-06-04
US385171 1982-06-04

Publications (2)

Publication Number Publication Date
KR840005255A true KR840005255A (en) 1984-11-05
KR870001117B1 KR870001117B1 (en) 1987-06-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830002467A KR870001117B1 (en) 1982-06-04 1983-06-02 Erroneous pulse sequence detector

Country Status (7)

Country Link
US (1) US4465977A (en)
EP (2) EP0240678B1 (en)
JP (2) JPS58222463A (en)
KR (1) KR870001117B1 (en)
AT (1) ATE60156T1 (en)
DE (1) DE3382129D1 (en)
HK (1) HK34492A (en)

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Also Published As

Publication number Publication date
DE3382129D1 (en) 1991-02-21
EP0240678A2 (en) 1987-10-14
EP0096295A3 (en) 1985-05-15
JPS58222463A (en) 1983-12-24
JPH06111467A (en) 1994-04-22
JPH0778959B2 (en) 1995-08-23
US4465977A (en) 1984-08-14
ATE60156T1 (en) 1991-02-15
KR870001117B1 (en) 1987-06-08
EP0096295A2 (en) 1983-12-21
EP0240678A3 (en) 1987-12-16
EP0240678B1 (en) 1991-01-16
JPH059867B2 (en) 1993-02-08
HK34492A (en) 1992-05-22

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