KR830002527B1 - Video signal processing circuit - Google Patents

Abstract

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Description

Video signal processing circuit

1 is a graph showing a state when the cathode ray tube is driven.

2 is a block diagram showing an embodiment of the present invention.

3 is a waveform used to describe the operation of the embodiment of FIG.

4 is a circuit diagram showing an embodiment of the present invention.

5 is a circuit diagram showing an embodiment that is partially different from the fourth embodiment.

6 is a circuit diagram showing another embodiment of the present invention.

7 is a waveform used to describe the operation of the embodiment of FIG.

8 is a circuit diagram showing yet another embodiment of the present invention.

9 is a waveform used to describe the operation of the embodiment of FIG.

10 is a circuit diagram showing the embodiment of FIG.

11 is a waveform used to describe the operation of the embodiment shown in FIG.

TECHNICAL FIELD The present invention relates to video signal processing, and more particularly, to a video signal processing circuit for use in a television receiver.

Technically, when a video signal is applied to the cathode of the cathode ray tube to drive the cathode ray tube, as shown in FIG. 1, the screen of the cathode ray tube is darkest at the pedestal level V ₁ of the video signal, and the At the back level V ₂ , it is driven to be the brightest.

As described above, when the cutoff level (black level) of the cathode ray tube is selected as the pedestal label of the video signal in order to completely restore the component, a fluctuation occurs in the setting level between the stations (channels). In other words, when the broadcast wave from any station having a high setting level is received due to the fluctuation of the black level, the black color appears somewhat gray. In order to prevent this drawback, in the conventional television receiver, the D.C key ratio is lowered to 0.5 to 0.9 in order to reduce the fluctuation of the black level as the fluctuation of the set level is relatively small.

However, the black level fluctuations were not completely removed by this method.

Accordingly, an object of the present invention is to provide a novel video signal processing circuit for solving the disadvantages of the prior art, wherein the level closest to the black side in the video interval is black in the cathode ray tube in order to avoid the black level fluctuation by the set level fluctuation. Provides a video signal processing circuit that is detected by setting the level and the cutoff level, and the selected level closest to the black side in the video interval is set to the cathode ray tube in order to avoid the fluctuation of the hog level due to the fluctuation of the set level without losing the characteristics of the screen. It is to provide a video signal processing circuit which is detected by being set to the black level and the blocking level.

According to an aspect of the present invention, a video signal processing circuit is configured to set a level of an input video signal to a predetermined first D. C level higher than a pedestal level of the input video signal while the video input signal is erased to generate a waveform signal. A waveform forming circuit to be set, a peak holding circuit for generating a peak holding signal to maintain the black peak level of the formed waveform signal, and matching the selected second D.C level with the darkest level of the video input signal. In order to control the D. C level of the video input signal, a black level control means controlled by the peak holding signal is provided.

Other objects, features and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings. 2, the basic configuration of the present invention will be described. In Fig. 2, reference numeral 1 denotes an input terminal through which the video input signal S ₀ shown in Fig. 3 is input from the video detection circuit (not shown in Fig. 2). The input video signal S ₀ is applied to the blanking circuit 2 to be blanked for an interval slightly longer than the horizontal blanking interval of the blanking pulse P _{1 of} FIG. 3b input from the terminal 3. . The blanking circuit 2 generates an output signal S ₂ having a voltage (+ Vcc) corresponding to the voltage erasing or the blanking interval of the input video signal shown in FIG. 3C. The output signal S ₂ is applied to the peak holding circuit (lower peak holding) circuit 4, which is a peak holding output signal S ₃ corresponding to the peak level at the completely black side as shown in FIG. 3d. Occurs in turn. The input video signal S ₀ from the input terminal 1 and the peak holding signal S ₃ from the peak holding circuit 4 are applied to the comparator 5. The comparator 5 has two signal (S _0), (S ₃₎ the output signal shown in FIG. 3 of the (S ₄₎ and transmitting a signal having a closer level to the black level than the other signal, and therefore the comparator (5 ) Is an analog OR circuit. The output signal S ₄ from the comparator 5 is applied to the clamp circuit 6 to which the clamp pulse P ₂ of FIG. 3f is supplied via the terminal 7. The clamp circuit 6 outputs the video signal S ₅ to the output terminal 8, and the blanking interval of the output signal is made equal to the selection level shown in FIG.

4 is an embodiment of an actual circuit for realizing the basic configuration shown in FIG. In Fig. 4, 9a and 9b are a pair of transistors whose emitters are connected together to a constant current source consisting of a transistor 10, a diode 11 and a resistor 12. The retrace pulse P ₁ described above is supplied to the terminal 3 connected to the base of the transistor 10 through the resistor 12 so that the transistor 10 is turned off during this pulse period, so that the collector of the transistor 9b In fact, the voltage is + Vcc. The collector output of transistor 9b is led through a current mirror circuit consisting of diode 13 and PNP transistor 14. Between the collector of the transistor 14 and the ground point, a series connected resistor 15, 16 is inserted, and a connection point between the resistor 15, 16 is connected to the base of the NPN transistor 17. Has a collector connected to the grounded emitter and the base of transistor 9b and to a ground point between resistor 18 and capacitor 17. The transistor 17 and the series connection of the resistor 18 and the capacitor 17 connected between the voltage source terminal (+ Vcc) and the ground point form a freck holding circuit shown in FIG. When the base voltage of the transistor 9a is higher than the base voltage of the transistor 9b, no current flows in the transistors 13 and 17 of the diode 13 and the capacitor 17 is charged to the power supply voltage through the resistor 18. do.

In such a case, the time constant becomes very large. When the terminal voltage across the capacitor 19 (base voltage of the transistor 9b) becomes higher than the base voltage of the transistor 9a, current flows through the diodes 13, 14, and 17, and the capacitor 19 is discharged below the terminal voltage. Thus, this feedback ensures that the base voltages of the transistors 9a and 9b coincide so that a level close to the black side in the video interval is maintained and the sustain output signal S ₃ is applied to the base of the transistor 20a.

A transistor 20b is provided having a collector and an emitter connected to the collector and emitter of the transistor 20a, respectively. The connection point between the collectors of the transistors 20a and 20b is connected to the power supply terminal (+ Vcc), and the connection point between the emitters is connected to the ground point through the resistor 21 and to the output terminal 5a.

The two transistors 20a and 20b form the comparator 5 shown in FIG. 2, and the input video signal S ₀ is applied to the base of the transistor 20b. A signal having a higher level among the signals S ₀ and S ₃ outputs an output signal S ₄ from the signal. As explained in connection with the second diagram, the clamp circuit 6 is connected to the output terminal 5a of the comparator 5. In practice, a clamp circuit 6 or a similar known circuit can be used as the clamp circuit 6 so that the clamp circuit 6 is not shown in FIG.

As shown in FIG. 5, two diodes 22a and 22b are used in the comparator, and the cathodes of the diodes 22a and 22b are grounded together through the resistor 21 and the output terminal 5a. You are connected to

As can be easily understood from the above-described embodiment of the present invention, the level closest to the black side in the video interval is detected and maintained in accordance with the present invention and automatically set as the blocking and black level of the cathode ray tube. Therefore, the fluctuation of the black level by the set level fluctuation between the conventional stations can be effectively prevented by the present invention. It may be considered that the video signal S ₂ subjected to the blanking process is used to clamp the level closest to the black side corresponding to the cutoff level to the predetermined level. However, in such a case, the blanking interval is chosen to be wider than the horizontal blanking interval, and the former level is high level on the white side, and therefore, even if the blanking process is performed at a stage preceding the cathode ray tube, the pulsation signal is high at the white side. Will be maintained. Such defects are eliminated by the present invention.

6 shows another embodiment of the present invention. In this embodiment, the input video signal S ₀ shown in FIG. 7 is supplied to the clamp circuit 23, and the pedestal level of this circuit is input to the clamp circuit 23 through the terminal 24. Is clamped to the reference voltage V ₀ , which is the voltage of the clamp voltage source 29. The output signal S ₁ from the clamp circuit 23 is input to the blanking circuit 2 and the subtractor 25. The output signal S ₃ and the reference voltage V ₀ from the peak holding circuit 4 shown in FIG. 7C are input to the comparator 26.

Comparator 26 compares the two signals and detects a level difference between the two signals. The output from the comparator 26 is input to the subtractor 25 through the gate circuit 27. The gate circuit 27 is controlled by applying the same control pulse as the blanking pulse P ₁ through the terminal 28. The subtractor 25 is supplied with a signal S ₆ , the level of which is selected in response to the output from the comparator 26 at the video interval rather than the control pulse interval shown in FIG. 7d within the control pulse interval. Level. The output signal of the gate circuit 27 is subtracted from the video signal S ₁ in the subtractor 25 and the subtractor 25 has a level closest to the black side in the video interval that matches the black level shown in FIG. The output signal S ₅ is transmitted to the output terminal 8.

The embodiment of the present invention shown in FIG. 6 can make the black level fluctuate according to the fluctuation of the set level as in the first embodiment of the present invention.

In the novel embodiment of the present invention shown in FIGS. 2 and 6, undesirable phenomena will occur depending on the type of video input signal. For example, when the contrast ratio of a video signal is bright and small, when this video signal is processed by the present invention, the vicinity of the video signal to be brightened essentially becomes too dark and thus the reproduced image becomes unnatural.

Another embodiment of the present invention, which can avoid the above undesirable phenomenon, will be described with reference to FIG. In the embodiment of FIG. 8, the clamp power supply 29 and the clamp circuit 23 of the embodiment shown in FIG. 6 are added to the embodiment shown in FIG. 2. In addition, the threshold power supply 30 and the diode 31 are It is further formed.

In the embodiment of the present invention shown in FIG. 8, the input video signal S ₀ from the video detection circuit passes through the input terminal 1 and the clamp circuit 23 through which the clamp pulse is applied. ) Is entered. Accordingly, the clamp circuit 23 generates the video signal S ₁ having a pedestal level clamped to the predetermined level V ₀ as shown in FIG. 9A. Horizontal blanking of the video signal (S ₁₎ is standing retrace through is applied to blanking circuit 2, terminal 3, a blanking pulse (P ₁₎ shown in Fig claim 9 ^B is applied to the circuit (2) It will be cleared over a slightly larger interval. The retrace clear circuit 2 generates an output signal S ₂ having a portion corresponding to the retrace clear interval made at the power supply voltage shown in FIG. ^9C . The output signal (S ₂₎ it is supplied to claim 9 ^D also the peak holding an output signal (S ₃₎ a peak holding circuit 4 is generated in the order that corresponds to the closest peak level in the video interval within the black, as shown in .

The output side of the peak holding circuit 4 is connected to the voltage point of (V ₀ + V _t ) which is the forward direction of the diode 31. If the forward voltage drop of the diode 31 is ignored, when the sustain output S ₃ is lower than the voltage (V ₀ + V _t ) level, the diode 31 is cut off and the sustain output S ₃ is applied to the video signal. Corresponding. On the other hand, when the sustain output S ₃ is higher than the (V ₀ + V _t ) level, the diode 31 is turned on and the sustain output S ₃ is at the level of (V ₀ + V _t ).

The video signal S ₁ from the clamp circuit 23 and the holding output S ₃ from the peak holding circuit 4 are transmitted to the comparator 5. The comparator 5 generates a signal having a level closer to the black side of the signals S ₁ and S ₃ and outputs the output signal S ₄ shown in FIG. 9. The output signal S ₄ from the comparator 5 is transmitted to the clamp circuit 6 through which the clamp pulse P ₂ shown in FIG. 9f is also transmitted via the terminal 7. Therefore, the video signal S ₅ having the blanking interval equally adjusted to the predetermined level as shown in FIG. 9G is output from the clamp circuit 6 to the output terminal 8.

FIG. 10 is an embodiment according to the present invention for realizing the circuit structure shown in FIG. Parts and elements corresponding to FIGS. 4 and 6 in FIG. 10 are denoted by the same numerals and description thereof will be omitted.

Now, the difference between the embodiment of FIG. 10 and the embodiment of FIGS. 4 and 6 will be mentioned. In the embodiment of the present invention shown in FIG. 10, the connection point between the resistor 18 and the capacitor 17 is connected through the diode 31 to the emitter of the transistor 24t. In this manner, the emitter of the transistor 24t is grounded through the constant current resistor 25r having a large resistance value, and the collector of the transistor 24t is connected to a power supply terminal of + Vcc. The base of the transistor 24 is connected to the clamp power supply 29 via a resistor 26r and to the power supply terminal of + Vcc via a resistor 27r. In such a case, by selecting the resistance values of the resistors 26r and 27r, the connection contact between the resistors, i.e., the base voltage of the transistor 24t becomes (V ₀ + V _t ), and the base-emit of the transistor 24 ^t is obtained. The voltage drop has a polarity to eliminate the forward voltage drop of the diode 31. Therefore, the holding output S ₃ is prevented from being exceeded above the voltage V ₀ + V _t .

According to the embodiment of the present invention shown in FIG. 8, the video signal S ₁ corresponds to a bright image and has a level higher than the predetermined voltage V ₀ + V _t as shown in FIG. 11A. when the input to maintain the output (S ₃₎ is the (V ₀ + V _t), the output (S ₄₎ from the comparator (5) is a thick line ^B of claim 11 degrees. On the other hand, in the embodiments of Figs. 2 and 6, if the level closest to the black side in the video interval is maintained and detected in accordance with the cutoff level of the cathode ray tube, the video signal corresponding to the bright image and the small contrast ratio is generated. It is converted into the video signal of the dark image shown by the dotted line of 11b degree.

On the other hand, in the embodiment of the present invention shown in FIG. 8, when the video signal has a higher level than the predetermined level (V ₀ + V _t ), no peak holding operation is performed, so the above-described problem does not occur. Do not.

According to the present invention, the output signal level of the television camera as well as the television receiver as well as the television receiver is processed, or the output signal level of the television camera closer to the black level and closer to the black side than the predetermined level is maintained in accordance with the set level and detected It can be adapted to such processing.

It is apparent that many modifications and variations can be made by those skilled in the art without departing from the scope of the novel concept of the invention and therefore the scope of the invention should be determined only by the appended claims.

Claims (1)

A waveform shaping circuit which sets the input video signal to a predetermined first DC level larger than the pedestal level of the video input signal while blanking the interval of the video input signal to generate the waveform signal, and maintains the black peak level of the formed waveform signal. A peak holding circuit for generating a peak holding signal for controlling the signal; and a DC level of the input video signal to control the selected second DC level to the darkest level of the input video signal, and controlled by the peak holding signal. In a video signal processing circuit having black level control means or the like, the level of the peak holding signal S ₃ limited to the maximum level and the second signal V ₀ supplied to the comparator are set to the input signal S ₀ . Compared to the level of the video signal (S ₁ ) output by controlling the output DC bell and driving the control signal (S ₄ ) to the darkest of the input video signal A video signal processing circuit provided with said black level control means with a comparator (5) for matching a level with a selected second DC level.

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