CA1154151A - Video signal processing circuit - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A video signal processing circuit is disclosed which has a wave-forming circuit for setting a level of an input video signal to a first predetermined D.C. level, which is higher than pedestal level of the input video signal, during at least a blanking period of the input video signal and producing a wave-formed signal, a peak-hold circuit for holding a level of the black-side peak of the wave-formed signal and producing a peak-held signal, and a black level control circuit controlled by the peak-held signal for controlling a D.C. level of the input video signal so as to coincide the darkest level of the input video signal with second predetermined D.C.
level.

Description

BACKGROUND OF THE XNVENTION
Field of the Invention The present inventiorl relates generally to a video signal processing circuit, and is directed more particularly to a video signal processing circuit for use in a television receiver.
Description of the Prior Art _ . _ In the art, when a video signal is applied to the cathode of a cathode ray tube to drive the same, it is selected such that, as shown in Fig. 1, the screen of the cathode ray tube becomes darkest at a pedestal level Vl of the video signal and becomes brightest at a white level V2 of the video signal. When the cut off level (black level3 of the cathode ray tube is selected equal to the pedestal level of the video signal to completely restore the D.C. component as set forth above, the fluc-tuation of a set up leve.. between stations (channels3 ~ .

$~

.

.
- ~ , ' ,~, : . ~ ' . .
:

~ 5~
appears, as it is~ as the fluctuation o-f the black level with the result that when a broadcast wave of a certain station with a high set up level is received, the black appears with somewhat greay. To avoid this defect, in a prior art television receiver, the D.C.transferring ratio is lowered to about 0.5 t:o 0.9 to reduce the fluc-tuation of the black level due to the above fluctuation of the set up level as to be relatively small. However, the fluctuation of the black level can not be sufficiently removed by the above manner.
OBJECT~ AND SU~ ~RY OF THE INVENTION
.
Accordingly, an object of the present invention is to provide a novel video signal processing circuit free from the defect inherent to the prior art.
Another object of the invention is to provide a video signal processing circuit in which the level nearest to the black side in the video period is detected, taken as the black level and set as the cut-off level of a cathode ray tube to avoid the fluctuation of the black level due to the above fluctuation of the set up level.
A further object of the invention is to provide a video signal processing circuit in which .the level nearest to the black side and with a predetermined level in a video period`is detected, taken as the black level-and set as the cut-off level of a cathode ray tube to avoid the fluctuation of the black level due to the above fluctuation of the set up level without losing the naturality of a pickure screen.
Accordinq to an aspect of the present 1~5'~51 invention, a video signal processing circuit is provided which comprises:
a) a wave-forming circuit for setting a level of an input video signal to a first predetermined D.C. level, which is higher than a pedestal level of said input video signal, during at least a blanking period of said input video signal and producing a wave-formed signal;
b) a peak-hold circuit for holding a level of a black -side peak of the wave-formed signal and producing a peak-held signal; and c) black level control means controlled by said peak -held signal for controlling a D.C. level of said input video signal so as to coincide the darkest level of said input video signal with a second predetermined D.C. level.
The other objects~ features and advantages of the present invention will become apparent fromthe following description taken in conjunction with the accom-panying drawings through which the like references designate the like elements and parts.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. l is a graph used to explain such a case where a cathode ray tube is driven;
Fig. 2 is a block diagram showing an example of the present invention;
Fig. 3 is a waveform diagram used to explain the operation of the example shown in Fig. 2;
Fig~ 4 is a connection diagram showing a practiacl example of the invention;

~ 5~

Fig. 5 is a connection diagram showing another example of a part of Fig. ~;
Fig. 6 is a block diagram showing another example of the invention;
Fig. 7 is a waveform diagram used to explain the example of the invention shown in Fig. 6;
Fig. 8 is a block diagram showing a further example of the invention;
Fig. 9 is a waveform diagram used to explain the operation of the example shown in Fig. 8;
Fig. 10 is a connection diagram showing a practical example of that shown in Fig. 8; and Fig. Il is a waveform diagram used to explain the operation of the example shown in Fig. 10.
DESCRIPTION OF THE PREFERRED EMBODI~ENTS
The present invention will be hereinafter described with reference to the attached drawings.
Turning to Fig. 2, the fundamental con-structuion of the present invention will be now described.
In Fig. 2, 1 designates an input terminal to which an input video signal So shown in Fig. 3A is fed from a video detecting circuit (not shown in Fig. 2).
The input video signal So is then supplied to a blanking circuit 2 where the video signal is blanlced over a period somewhtat longer than the horizontal blanking period by a blanking pulse Pl shown in Fig. 3B and fed thereto through a terminal 3. Then, the blanking circuit 2 generates an output signal S2 which has, for example, a voltage source potential or voltage, for example, +Vcc corresponding to the blanking period of the input video ~S~5~
signal as shown in Fig. 3C. The output signal S2 is then fed -to a peak hold (bottom hold ) circuit 4 which in turn produces a peak-hold output signal S3 which cor-responds to the peak level at the most black-side as shown in Fig. 3D. The input: video signal S0 Erom the input terminal 1 and the peak-held signal S3 from the peak hold circuit 4 are both supplied to a comparator 5. This comparator 5 delivers therefrom one o~ both signals S0 and S3 which has a level nearer to the white level than the other or output signal S4 shown in Fig. 3E, so that this comparator 5 is an analog OR circuit.
The output signal S4 from the comparator 5 is supplied to a clamp circuit 6 which is also supplied with a clamp pulse P2, shown in Fig. 3F, through a terminal 7, so that the clamp circuit 6 produces at its output terminal 8 a video signal S5 whose blanking periods are made equal with one another to a predetermined level as shown in Fig~ 3G.
Fig. 4 shows an example of the practical circuit which will realize the fundamental construction shown in Fig. 2. In Fig. 4, 9a and 9b designate a pair of transistors whose emitters are connected together to a constant current source consisting of a transistor 10, a diode 11 and a resistor 12. The terminal 3; con-nected through the resistor 12 to the base of the transistor 10, is supplied with the blanking pulse Pl as set forth above so that, during the period in which the transistor 10 is made OFF bv the blanking pulse Pl, the collector of the transistor 9b becomes the power source voltage ~Vcc substantially. The collector output of this transistor 9b is derived through a current mirror circuit ' ~15~5~
eonsisting of a diode 13 and a PNP transistor 14, A series connection of resistors 15 and 16 is inserted between the collector of the transistor 14 and the ground, and.the connection point between resistors 15 and 16 is eonneeted to the base o an NPN transistor 17 which has the emitter grounded and the eollector eon-neeted to the base of the transistor 9b and also to the eonnection point between a resistor 18 and a capacitor 19, The series conneetion of the resistor 18 and eapacitor 19 . eonneeted between the voltage source terminal ~~ec and the ground and the transistor 17 form the peak hold ei.r-euit 4 shown in Fig. 2. When the voltage at the base of the transistor 9a is higher than that at the base of the transistor 9b, no eurrent flows through the diode 13 and the transistors 14 and 17 and the eapaeitor 19 is charged up by the power souree voltage through the resijstor -18. In this ease, the time eonstant is made very large.
When the terminal voltage acxoss the eapaeitor 19 (the ~oltage at the base of the transistor 9b) tends to beeome higher than the base voltage of the transistor 9a, current flows through the diode 13 and the transistors 1~ and 17 :.
and the eapacitor l9 is diseharged to lower its terminal voltage. Thus, such a ~eedback is applied that the base voltages of the transistors 9a and 9b become equal each other, so that the level nearest to the black side in the video period is held and the held-output signal S3 is applied to the base of a transistor 20a.
A transistor 20b is provided which has the eolleetor and emitter respectively connected to those of the transistor 20a. The connection point between 5~

the collectors of bo-th transistors 20a and 20b is conneeted to the power source terminal +Vcc, and the connection point between the emitters thereof is connected through a resistor 21 to the ground and also to an output terminal 5a. Both transistors 20a and 20b form the comparator 5 shown in Fig.

2, and the input video signal S0 is applied to the base of the transistor 20b. One of the signals S0 and S3 which is higher than the other in level is derived as the output signal S4 therefrom.
To the output terminal 5a of the comparator 5 connected is the clamp circuit 6 as described in connection with Fig. 2. In practice, as the clamp circuit 6, a well-known clamp cireuit sueh as a feedbaek elamp eireuit or the like ean be used so that the elamp circuit 6 is not shown in Fig. 4.
As shown in Fig. 5, such a comparator may be used in which two diodes 22a and 22b are connected in sueh a manner that their cathodes are connected together to the ground through the resistor 21 and also to the output terminal 5a.
As will be easily understood from the above deseribed example of the invention, aecording to the present invention, the level nearest to the black side in the video period is deteeted, held, is taken as the blaek and set as the eut-off level (blac]c level? of the cathode ray tube automatically. so that the fluctuation of the black level by the fluetuation of the set up level between the stations as in the prior art can be effectively avoided by the invention.
It may be considered that the video signaI S2, ~15~51 which is subjected to the blan]cing process, is used to clamp the level nearest to the black side to a predetermind level which corresponds to the cut-off level. However, in this case the blanking periocl is selected wider than the horizontal blanking period and the level of the former is khe high level at the white side/ so that even if the blank-ing process is performed at the stage prior to the cathode ray tube, a pulsative signal in the high level at the white side will remain. Such the defect is removed by the present invention.
Fig. 6 shows another example of the invention.
In this example, an input video signal S0 shown in Fig. 7A
is supplied to a clamp circuit 23 and its pedestal level is clamped therein to a reference voltage V0, which is the voltage of a clamp voltage source 29, by a clamp pulse fed to the clamp circuit 23 through a terminal 24. An output signal Sl from the clamp circuit 23 is fed to a subtracter 25 and to a blanking circuit 2. This blanking circuit 2 is similar to that shown in Fig. 2 and produces an output signal S2 shown in Fig. 7s which is fed to a peak hold cir-cuit 4. An output signal S3 from the peak hold circuit 4 and the reference voltage V0 both shown in Fig. 7C are fed to a comparator 26.
The comparator 26 compares both the signals 2~ and detects the level difference therebetween. The output~from the comparator 26 is fed through a gate cir-cuit 27 to the subtracter 25. The gate circuit 27 is also supplied with a control pulse similar to the blanking pulse Pl through a terminal 28 to be controlled, so that the subtracter 25 is supplied with a signal S6 which is :
.

-~15~'151 in a predetermined level in the period oE the control pulse and in the level in response to the output from the com-parator 26 in the video period other than the control pulse period as shown in Fig. 7D. The output signal of the gate circuit 27 is subtracted from the video signal Sl in the subtracter 25 so that the subtracter 25 delivers to the output terminal 8 an output signal S5 whose level nearest to the black s,ide in the video period coincides with the black level as shown in Fig. 7E.
The example of the invention shown in Fig.6 can avoid the fluctuation of the black level owing to the fluctuation of the set up level similar to the first example of the present invention.
In the above examples of the invention shown in Figs. 2 and 6, an undesired phenomenon will appear in accordance with the kind o~ the input video signals.
For example, in case of a video signal which is generally bright and small in the contrast ratio, when this video signal is processed by this invention, a part of the video signal to be inherently bright becomes dark excessively and hence a reproduced picture becomes unnatural.
A further example of the inventlon, which can avoid the above undesired phenomenon, will be now described with reference to Fig. 8. In brief, the example of Fig. 8 is formed by such a manner that the ,clamp circuit 23 and the clamp voltage source 29 of the example shown in Fig. 6 are added to the example shown in Fig. 2, and further a threshold voltage source 30 and a diode 31 are added -thereto.
In the example of the invention shown in 1~54~5~
Fig. ~, the input video signal S0 from the video detecting circuit i 9 fed through the input terminal 1 to the clamp circuit 23 to which the clamp pulse is applied through the terminal 24. Thus, the clamp circuit 23 produces a video signal Sl whose pedestal level is clamped to a pre-det~ermined level V0 as shown in Fig. 9~. This video signal Sl is applied to the blanking circuit 2 and blanked over a period somewhat wider than the horizontal blanking period by a blanking pulse Pl shown in Fig. 9B and applied to be blanking circuit 2 through a terminal 3. Then, the blanking circuit 2 produces an output signal S2 whose part corresponding to the blanked period is made at, for example, the power source voltage as shown in Fig. 9C. This output signal S2 is supplied to a peak hold circuit 4 which in turn produce a peak-held output signal S3 which corresponds to the peak level nearest to the black side in the video period as shown in Fig. 9D.
The output side of the peak hold circuit ~ is connected to the voltage point of (V0 -~ Vt) through the diode 31 in the forward direction thereof, so that if the forward voltage drop of the diode 31 is neglected, when the held output S3 is lower than the voltage tVo + Vt) in level, the diode 31 is cut off and the held output S3 corresponds to the video signal. While, when the held output S3 is higher than (Vo -~ Vt) in level, the diode 31 is made conductive and the held output S3 becomes the level of (V0 + Vt).
The video signal Sl from the clamp circuit 23 and the held output S3 from the peak hold circuit ~
are fed to a comparator ~. This comparator 5 produces A,~

-` 1154~S~

one of both the signals S1 and S3 which is in level much near to the white side than the other and hence delivers an output signal S4 shown in Fig. 9E. The output signal S4 from the comparator 5 is fed to a clamp circuit 6 to which a clamp pulse P2 shown in Fig. 9F is fed through a terminal 7. Thus, at an output terminal 8 led out from the clamp circuit 6 delivered is a video signal S5 whose blanking periods are arranged equal to a predetermined level as shown in Fig. 9G.
Fig. 10 shows an example of a practical connection according to the present invention which will realize the circuit construction shown in Fig. 8. In Fig. 10, the parts and elements corresponding to those of Figs. 4 and 6 are marked with the same references and their description will be omitted.
Now, the difference between the examples of Fig. 10 and those of Figs. 4 and 6 will be described.
In the example of the invention shown in Fig. 10, the connection point between the resistor 18 and capacitor 19 is connected through a diode 31 to the emitter of a transistor 2~t. This emitter of the transistor 24t is grounded through a constant current resistor 25r whose resistance value is selected large, and the collector of the transistor 24t is connected to the power source terminal of +Vcc The base of the transistor 24t is connected through a resistor 26r to the clamp voltage source 29 and also through a resistor 27r to the power source terminal of +Vcc. In this case, by selecting the resistance values of the resistors 26r and 27r, the -~oltage at the connection point therebetween i.e. the base '~

.

voltage o~ the transis~or 24t can be made as (V0 -~ Vt), and the base-emitter voltage drop o-f the transistor 24t has such a polarity to cancel the forward voltage drop of the diode 31. Thus, the held output S3 is prevented from exceeding over the voltage (Vo + Vt).
According to the example of the invention shown in Fig. 8, when a video signal Sl, which corresponds to a bright picture and whose level is higher than the predetermined voltage (V0 -~ Vt) as shown in Fig. llA, is fed to the circuit, the held output S3 becomes (V0 + Vt) per se, and accordingly the output S4 from the comparator 5 becomes as shown in Fig. l]B by the solid line.
While, as in the examples of Figs. 2 and 6, if the level nearest to the black side in the video period is merely detected, held and made coincident with the cut off level of the cathode ray tube, there may be such a fear that the video signal corresponding to a bright picture and small in contrast ratio is converted to a video signal of a dark picture as shown in Fig. llB by the broken line.
According to the example of the invention shown in Fig. 8, on the contrary, such the ear does not occur because when the video signal has a level higher than the predetermined level (V0 ~ Vt), no peak hold operation is carried out.
The present invention can be applied not only to a television receiver as in the above examples, but also to such a case where the output from a tele-vision camera is processed or such a process is carried out that a level of the output signal from the television camera, which is nearest to the black side and nearer :llS4:~L5~L
than the predetermined level to the black level, is detected, held and then made co:Lncident with the set up level.
It will be apparen-t that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope oE the novel concepts of the present invention so that the spirits or scope of the invention should be determined by the appended claims only.

Claims (5)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A video signal processing circuit for an input video signal representing a video picture and having a D.C. level, a pedestal level, and a blanking period, said processing circuit comprising: a wave-forming means operative during at least said blanking period for establishing the amplitude level of said input video signal during the operating period thereof to be equal to a predetermined first D.C. level, which is higher than said pedestal level of said input video signal, and producing a wave formed signal; peak-hold circuit means for detecting and holding that level of the wave-formed signal representing the darkest level of the video picture, and producing a peak-hold output signal; and black level control means responsive to said peak-hold output signal for setting the D.C. level of said input video signal at such a level that the level of said input video signal repre-senting said darkest level of the video picture coincides with a predetermined second D.C. level.

2. A video signal processing circuit according to claim 1, wherein said second predetermined D.C. level corresponds to a cut off level of a cathode ray tube which is the output sig-nal of said black level control means to be supplied.

3. A video signal processing circuit according to claim 1, wherein said black level control means has:
d) a comparator for comparing a level of said input video signal with said peak-held signal, and producing an output signal corresponding to a higher level signal of said both signals; and e) a first clamp circuit for clamping the output of said comparater to said second predetermined D.C. level at the blanking period of said input video signal.

4. A video signal processing circuit according to claim 1, wherein said black level control means has:
f) a clamp voltage source for supplying said second predetermined D.C. level;
g) a second clamp circuit for clamping the pedestal of said input video signal to said second predeter-mined D.C. level;
h) a first subtracter for subtracting said second predetermined D.C. level from said peak-held signal;
and i) a second subtracter for subtracting the output of sid first subtracter from the output of said second clamp circuit, and producing an output signal.

5. A video signal processing circuit according to claim 1, wherein said black level control means has:
j) a clamp voltage source for supplying said second predetermined D.C. level;
k) a second clamp circuit for clamping the pedestal of said input video signal to said second predeter-mined D.C. level; and 1) a series circuit of a threshold voltage source and a diode connected between said peak-hold circuit and said clamp voltage source.