KR830002287A - Binary coded compressor circuit - Google Patents
Binary coded compressor circuit Download PDFInfo
- Publication number
- KR830002287A KR830002287A KR1019800000726A KR800000726A KR830002287A KR 830002287 A KR830002287 A KR 830002287A KR 1019800000726 A KR1019800000726 A KR 1019800000726A KR 800000726 A KR800000726 A KR 800000726A KR 830002287 A KR830002287 A KR 830002287A
- Authority
- KR
- South Korea
- Prior art keywords
- group
- input
- bits
- programmable storage
- significant
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Programmable Controllers (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this content is publicly disclosed, the full text is not included.
제1 및 2도는 이전기술의 광학적 판독 시스템에 채택되는 종래의 기계적 애퍼튜어 마스크의 종래기술의 도해.1 and 2 are illustrations of the prior art of a conventional mechanical aperture mask employed in prior art optical reading systems.
제3도는 광학적 판독 시스템의 서류 포오맷을 결정하기 위한 선택적 프로그래머블 티드-온리-메모리(PROM)을 채택한 본 발명의 실시예의 블록 다이아 그램으로의 도해.3 is an illustration of a block diagram of an embodiment of the present invention employing an optional programmable only-only-memory (PROM) for determining the document format of an optical reading system.
제4도는 제3도의 블록다이아그램으로의 개략적인 도해.Figure 4 is a schematic illustration of the block diagram of Figure 3;
제5도는 서류줄의 주사표시와 표시부분에 관련된 주사간격을 포함하는 서류 포오맷의 도해.Figure 5 is an illustration of the format of a document, including the interval between scans and the markings in the document line.
제6,7 및 8도는 제3도와 4도의 실시예의 상세한 개략적 실시.6, 7, and 8 are detailed schematic implementations of the embodiments of FIGS. 3 and 4.
제9도는 토우를 라이저와 정보 프로쎄서 사이의 데이터 리듀서를 포함하는 제4도의 개략도의 변경.FIG. 9 is a modification of the schematic of FIG. 4, which includes a data reducer between a tow riser and an information processor.
Claims (1)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US45879A | 1979-01-02 | 1979-01-02 | |
US458 | 1979-01-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR830002287A true KR830002287A (en) | 1983-05-23 |
Family
ID=21691604
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019800000726A KR830002287A (en) | 1979-01-02 | 1980-02-22 | Binary coded compressor circuit |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS5592968A (en) |
KR (1) | KR830002287A (en) |
-
1979
- 1979-12-25 JP JP16771679A patent/JPS5592968A/en active Pending
-
1980
- 1980-02-22 KR KR1019800000726A patent/KR830002287A/en unknown
Also Published As
Publication number | Publication date |
---|---|
JPS5592968A (en) | 1980-07-14 |
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