KR830001773B1 - Telecommunication switching device - Google Patents

Abstract

No content.

Description

Telecommunication switching device

1 is a schematic diagram illustrating a remote communication switching system of an exemplary peripheral device of a network according to the present invention.

2 is a schematic diagram showing the overall structure of the network.

3 is a schematic diagram showing the relationship between the network of a switching system, its control unit and related parts.

4A-4C are logic diagrams of a series-to-parallel-to-serial converter.

5 is a schematic diagram of a high level interface circuit.

6A to 6B are logic system diagrams of a CPVA interface circuit.

7a to 7e are logic diagrams of a CPVB interface circuit.

FIELD OF THE INVENTION The present invention relates to telecommunications switching devices, and in particular to a connection between a plurality of ports, to a network part of such a device.

The ultimate purpose of the telephone switching network is to connect two or more terminals. In practice, cross-bar switching, lead switches, etc., which make metal circuits complete, are well known, easily understood, and have nothing in common for troubleshooting.

The present invention provides an " all time " switch, i.e. a one-time slot, for receiving, storing and delaying a sample of information at an appropriate time, and then transmitting it, for effective communication between terminals assigned to the time slot To a switch that switches from one node to another time slot. This circuitry does not use a metal connector, but is a secondary semiconductor memory (connection) to store samples when they are received continuously and to exchange samples between timeslots for communication between terminals assigned to time slots. Semiconductor memory is used to decode the stored information under controlled control. In this type of device, samples from all the arrays of access ports at the input are channeled down to a very small number of buses in the network for switching, and distributed to that port. To be demultiplexed after switching. Because of the density of information in the network, a failure in this network will render all or most of all switching exchanges inoperable.

In order to minimize the possibility of switching devices failing in this form, most switchboard switching devices are equipped with redundant circuitry to immediately return on the line if the primary device fails. Within these devices, all networks are doubled, and if the network is in block form, each block is doubled to return the primary block. In this type of device, each spare block is equal to the main block. For example, the spare block can be operated in parallel with the primary block so that the connections are written on both sides. Another method is to provide a DMA channel between the primary and secondary blocks so that when the secondary block becomes inoperable, its memory contents are moved to extra blocks by operation.

Since a complete dual network involves considerable hardware and is quite expensive to manufacture, in most small switching devices, it is not possible to have a backing network device.

In view of the foregoing, it is a primary object of the present invention to economically provide a switching network in which stability is increased and there is no need to fully double the network. More specifically, it is an object of the present invention to provide a network having a plurality of primary blocks and only one redundant circuit block and the sameness of the redundant blocks is programmed to take the identity of the primary block.

More specifically, another object of the present invention is to define primary and redundant blocks so that they are replaced at a point in the multiplexing / demultiplexing structure where the spare block has the greatest impact on overall device stability. More specifically, another object of the present invention is to define a multiplexing / demultiplexing structure so that redundant blocks are sponsored, including multiplexing in two stages and including zero or higher graded stages in the network.

Hereinafter, other objects and advantages of the present invention will be described in detail with reference to the accompanying drawings.

Referring to the drawings, FIG. 1 shows a schematic diagram of a telephone switching device providing an exemplary peripheral device of a network according to the present invention. This apparatus is adapted to be connected to a plurality of lines indicated by telephones 30 and 31 and a plurality of relay lines indicated by 32. The access point represents a switching device input useful for such an input device. Circuitry is provided for interfacing the access ports to the switching device, which is represented by the line circuits 33 and 34, the analog trunk line circuit 35 and the digital trunk line circuit 36. Since the switching device consists of four wire changes, the line circuits 33,34 and analog relay lines connected to the two wire trunk lines convert the two wire line signals into four wire line signals for use by the switching device. Include hybrids.

In addition to the line and trunk line devices connected to the access ports, the switching devices may serve additional devices to provide the particular form indicated by the element 38. For example, the switching device may be configured to provide paging, code calling, multi-pot portions, and the like. The required additional device, for example an audio device for use in paging form, is indicated by 39.

In the illustrated embodiment, connected to the access port are a dial receiver and register 40 for receiving and interpreting a dial number, and a digital tone generator 41 for generating advancing tones by a switching device.

As already implied, the switching device is formed as a four wire digital time switch, so that the analog information shown in the analog access port must be converted into digital form. For this purpose, a number of code transducers 45 are provided. In a preferred embodiment, the code used is a standard D2 / D 3PCM code using an 8-bit format, 1.544 megabits transmission rate and compression ratio μ = 235. Therefore, the code converter block 45 can be improved to use a plurality of converters capable of processing 24 channels each, rather than the conventional T1 PCM code converter. It is also desirable to modify the switching device by providing two additional bits within each word, the third bit for signal transmission and the tenth bit for parity. One embodiment of the illustrated switching device can accommodate up to 3,088 channels, but 3072 work and 16 lose structures. FIG. 1 shows such a switching device showing a bus structure 46 consisting of 128 buses each carrying 24 channels of digital information to a low level multiplexer 48.

The low level multiplexer continues to collect information generated within a number of separate access points towards the network. This combines four groups of 24 channel buses 46 into a 96 channel serial bus structure 47. In the switching device of the size shown, 32 of the 96 channel buses are provided, which are sent to the network 50 where a number of access ports are taken between.

When the switching device is actually implemented, the input circuit, the code converter and the low level multiplexer are not disassembled into separate blocks as shown in Fig. 1, and function to minimize the wiring between the cards when making 96 channel buses. Blend with each other along the line. For example, in a device frame serving a line circuit, a number of files are provided, each file having four code converters and each file in the frame having one of the 96 channel buses. It contains the line circuits needed to support four code converters along one low-level multiplexer to support them. The buses are in the form of cables that circulate from each file to the device frame covering the network circuitry. In some cases, such as in a trunk line circuit, you must have two files to make 96 information channels, but even in this case, the device visually divides towards each segment serving one bus that acts as input to the network. do. According to the device formed by this method, the failure of a single line or repeater circuit affects only this line or repeater line, the failure of the code converter affects only 24 channels, and the failure of the low level multiplexer is about 3% of the total switching device. Affects specific 96 channels. As a result, the failure of these devices is important, but not so important for the operation of the entire switching device. However, as information continues to gather towards the network, failure of devices above the 96-channel serial level has a significant impact on the operation of the overall switching device. Therefore, a sponsoring device is provided for devices of 96 channels or more as described in detail below.

Before describing this, first, in the illustrated embodiment, the divided multiprocessor control complex 51 described in detail in US Patent Application No. 734,732 (not left) filed by Pirotda et al. Under the name of a microprocessor control complex. Will be described. As shown in FIG. 1, the split processor controller 51 has a circuit connected to these elements so that the above-described elements can perform switching interactions. In general, the control complex keeps track of the current state of each access point in the device, detects service requests, determines the next state of each access post, and one state, such as by a write connection in the network. To change from one state to another.

For the sake of completeness, FIG. 1 shows an additional console 52 coupled to a split processor controller for monitoring device connections, establishing new connections, and the like. The device status and retaining pann 53 provide the ability to assist in repair work and indicate the status of a particular device, as well as the ability to manually reconfigure the device. The data terminal 54 provides information output therefrom as well as a port for inserting information into the processor complex 51. Remote terminal interface 55 provides similar capabilities to stations at remote ends. Finally, the flexible disk 56 can be operated when the software loses its inherent nature to load all the programs for the device and load the program to reposition the device on the track.

Referring to FIG. 2, the general structure of a network 50 consisting of four primary blocks 60-63 and redundant blocks 64 is shown. In this case, as well as the network inputs, its outputs may be 96-channel bus structures 47 that carry information to or from lines, repeaters and service circuits. In the illustrated embodiment, the series-to-parallel-to-serial converter device 66 acts as a network input and output for servicing the bus structure 47. The transducers provide switching elements with a high level multiplexer 67 for gathering fragrance digital information and an information memory 68 operating under the control of the connected memory in such " full time " switch.

In the illustrated embodiment, each network block can process 768 information channels. To efficiently provide this capability, the upright-to-sort-to-serial converter of each block is formed of four cards each capable of handling two of the 96 channel buses. Thus, each block processes eight of the 96 channel buses and provides bus transfer information from the 768 channels as inputs to the information memory.

Referring to the converter card 66a of block 0, this card is divided into four stages 0-3 at the low level end, and the block 0 has 96 channel buses B1 and B2 connected thereto, and the high level multiplexer 67 It can be seen that it has a common end at the high level end that provides two output bus 70 in the). Each remaining card in block 0 is connected in the same way to service 96 channel buses B3-B8. In block 1, one stage of the converter card is used, two stages are used in block 2, and three stages are used in block 3. The redundant network block converter cards have four stages connected to an incoming bus, for example, a card 66b providing buses B1, B2, B9, B10, B17, B18, B25, and B26. Forming a converter card in this way allows a single card form to act as a primary block when inserted at an appropriate location in the card file, or as a spare block converter when inserted into an extra block file.

A serial-to-parallel-to-serial converter accepts serial information from related buses, converts it in parallel, and receives it by the high level multiplexer 67 at a suitable time during the converter's scanning (70). Keep this converted data on the output bus. Operating in the opposite direction, converter 66 accepts demultiplexed parallel information, converts it in series, and drives feedback buses B1-B32 to decompose the information into access ports via a low level multiplexer. Each bus B1-B32 is shown as a single bidirectional bus for simplicity, but is actually implemented as a one-way bus of one phase. As described above, the high level multiplexer 67 periodically receives parallel information from the converter to provide parallel information to the information memory on the 768 channel buses 72. This information is written into the information memory in the dedicated time slot. Under the control of the contact memory, the information memory is decrypted to insert this information on the 768 feedback channel buses into the high level multiplex 67, in which case it is demultiplexed and transferred to the converter card 66. It is serialized for transport back through the D / A stage of the code converter for distribution to low-level, multiplexers, required wires, repeaters, or resistor circuits.

3 is a schematic diagram showing in more detail the relationship between the elements shown in FIG. 2 and the controller thereof. 3 shows only a single series-to-parallel-to-serial converter 66 and two low level multiplexers 48 that serve it. However, the high level multiplexer 67, shown as connected only to a single series-to-parallel-to-serial converter 66, also has circuit connections (not shown) connected to the three additional transducer cards in this block. Have 3 shows a high level multiplexer 67 which supplies signals towards the information memory 68 for storage in the information memory 68 as shown in FIG. In this case, however, demultiplexing takes place in the comparator and comparator interface circuit 74. This device is used when the network is formed of three cavities, accepts samples from two memory elements in the information memory, compares the information during each time slot, and transfers the larger sample of the two samples. The strobe pulses of the serial-to-parallel-to-serial converter 66 cause the within parallel registers to receive the comparison result within an appropriate time slot. Effectively, the comparator and comparator interface circuit 74 completes demultiplexing to compensate for the multiplexing implemented in device 67.

3 also shows the control portion of the network block including a pair of high level interface circuits 75, 75 'that receive data from the control complex 51 (FIG. 1) for distribution to the selected network block. High level interface circuits as well as control complexes are described in detail in the aforementioned U.S. Patent Application No. 734,732 (left). In the split control complex arrangement presented here, the state microprocessor is the control element of the network. As shown here, only one high-level interface circuit is active at a time, and the second unit is provided for complete redundancy, so that if the operating interface circuit fails, its partner will automatically operate. For this purpose, the two input and output bus structures of the interface circuit are connected in parallel. The state microprocessor communicates with the same network interface card as the CPVA interface circuit 76 and the CPVB interface circuit 77 via the high level interface circuit 75 or 75 '. The CPVA interface circuit 76 is used for maintenance and call processing and partially decrypts the address passed through the high level interface circuits 75 and 75 '. CPVB interface circuit 77 receives data words from the control complex to write connections in the network memory. More specifically, data is received indicating the address of a specific position to be written, and other data is received as actual data to be written at this addressed position. Accordingly, the CPVB interface circuit 77 has a circuit connection portion for connecting an address and data to the connection memory 79. As a result, the connection can be written into a connection memory that exchanges information received by the information memory 68 between time slots associated with the connected channels.

High level interface circuits are part of the control complex and effectively provide part of the bus structures that interface the network and the control complex. As such, the active interface circuit among the high level interface circuits 75, 75 'serves all network blocks. By way of contrast, interface circuits 76 and 77, which are CPVs, become part of the network block.

Thus, five pairs are provided for the full size device, one pair for each primary block, and one pair for the spare block. The high level interface circuits 75 and 75 'are connected to all five sets. However, as described in detail below, each pair has a unique address that is decrypted such that only one network block responds to commands from the control complex, so that the control complex selectively addresses each block. can do.

In practicing the present invention, the redundant network block, when enabled, responds to one primary address, so at least in the call processing mode, the control complex should only address the primary block. Thus, when a spare block is placed online, the spare block responds to where the block is replaced, without a call handler program that knows to replace the block. As a result, the call processing software is simple because it does not need to be changed and there is no need to provide a separate program to cover the use of extra blocks at the primary block location. If a spare block is activated and it fails to operate, the primary block will continue to process the call as if the primary block were online, even if it performs extra functions derived from the disabled primary block.

In view of these advantages, a specific circuit of the network element, which shows one embodiment of the network block according to the present invention in detail, will be described. As described below, each circuit card or card or card is universal and can act as a primary block or a spare block, respectively, and optionally, each universal card is specific to a particular device type. Allocate unique features.

4A-4C, there is shown a transducer device 66 inserted between a low level and a high level multiplexer (see FIG. 3). The converter serial-to-parallel converts the data received from the low level multiplex and prepares it on the output line for the high level multiplexer to receive. In the opposite direction, the converter performs parallel-to-serial conversion, accepting parallel data from the comparator and serializing it for the low-level multiplexer to receive. Since each data word in the serial bit sequence contains 8 bits and the eight converters provide a single high level multiplexer, the bit ratio of the low level and high level multiplexers is equally high, although the high level multiplexer handles 8 times the amount of data. maintain. Thus, the bit rate of the low and high level multiplexers is about 6,176 mHz, resulting in about 162 nsec for each data bit and about 1300 nsec for each 8-bit word.

FIG. 4A shows the converter series-to-parallel portion, which includes a set of four triple state drivers 100-103 that are portions of the low-end circuit divided into block C-3 in FIG. Input busses, i.e. cables from lines, repeaters and service circuit frames, are connected to the driver input, one of four groups connected to the particular network block of particular interest. This connection is formed in the connector on the back of the frame, so that when the substrate is inserted into the connector, the appropriate driver receives a signal. Thus, cables carrying 96 serial channels are provided at block 0 with signals to driver 100, at block 1 with driver 101, at block 2 with driver 102, and at block 3. Is connected to the connectors so as to be provided to the driver 103. As described in connection with the description of FIG. 2, the connectors of the redundant network block cards are wired such that all of the drivers 100-103 have input signals provided thereto.

In order to allow only one driver block to operate at a given time, an operable device 105 for selectively operating the block is provided. This operable device, in this embodiment, is in the form of one of four decoders with four outputs, one output driven slightly depending on the state of the input signal. The input signal is denoted by NBI OFF ^* and NBI IFF ^* , which indicates a network block representation (0 or 1) flip-flop circuit, and an asterisk (*) indicates that the low level logic state is true. These input signals can be hardwired for the primary block and programmed for the redundant block to select and operate one of the four driver blocks, thus partially identifying the identity of a particular converter. Divided by For example, if both inverted ID bits are high level, output 106 is driven slightly, and this signal drives the output to high level to operate four triple state drivers 110-113. Provided to the inverter 107. The codes (non-inverting) of the primary channels are as follows.

Since each code can handle two 96-channel serial buses, the conductors 115 and 116 of block 100 provide the input ports of these buses. When the switching device is actually implemented, in addition to eight data bits per channel, there are signaling bits and parity bits. These signaling bits and parity bits are separate buses, in the illustrated embodiment, a bus 117 carrying data signaling and parity on the bus 115, and a data signaling and parity on the bus 116. On bus 118. The other driver blocks are similarly arranged respectively.

For example, bus 115 receives PCM data of group X LMPCM ^* G (X) from a low level multiplexer, bus 116 likewise receives data of group X + 1, and buses 117, 118. Receives LMSIG ^* G (X) and X + 1.

The PCM data passed by drivers 110 and 111, as well as other parts of these other driver blocks, are associated with clocked under the control state of the incoming data 162 nsec clock L 162 I coupled to register via safety device 122. Appears at the input of the 8-bit transition registers 120 and 121. When the entire 8-bit word is received, the output lines of each register represent this 8-bit word in parallel, and this parallel data is controlled by the incoming data 1300 nsec clock L 1300 I ^* coupled to the latch circuit through the inverter 123. Strobes into latch circuits 124 and 125 under this condition. The latch circuits 124 and 125 accept this data under the control state of the above-mentioned clock and hold this day on the output lines 126 and 127 when ready to accept this data by the high level multiplexer.

Referring to the signaling and parity bits, each of these bits is sent twice during each 1300 nsec period, so they are clocked in the 324 nsec period. Therefore, the outputs of drivers 112 and 113 are provided to respective transition registers 130 and 131 and the received data is clocked by 324 nsec clock L 324 I ^* provided to the register by buffer generator 132. This data is therefore available at the next output line received and simultaneously clocked to the buffer latch circuit 134 by the same clock that updated the latch circuits 124 and 125.

Thus, during each 1300? Sec, data words from each of the two serial buses are clocked into registers 120 and 121, and signaling and parity are clocked into registers 130 and 131. At the end of this 1300? Sec period, latch circuits 124, 125, and 134 are clocked to receive the data in parallel, and subsequently clocked to hold this data for reception by the high level multiplexer at appropriate points. The high-level multiplexer receives data from the latch circuits 124, 125 and 134 in operation and from similar latch circuits on three additional cards in the order determined in the appropriate time, so that 10-bit parallel words from each channel are contiguous. While this is taken, the registers 120, 121, 130, and 131 load the next word, so that the cycle is repeated to continue to concentrate information from the low level circuitry towards the switching elements of the network. Able to know.

Before discussing the parallel-to-serial portion of the circuit, let me describe the circuit that terminates the cable that provides the 96-channel serial bus.

These cables carry a series of bits, each with a pulse of about 162 η sec., And cables are typically about 30 feet in length, so it is important to terminate them properly. Also, in order to meet the criteria for providing everything above the 96-channel serial level to the backing device, each cable must be terminated in two locations, which is a significant complication.

Various means are taken to ensure that data sent by the initial frame is received stably in the network. Initially, the termination impedance of the incoming cable is distributed between the primary and redundant blocks, so once the circuit boards of these two blocks are in the proper position, the cable is terminated, one block is moved, and the resulting impedance mismatch occurs. It will be acceptable. To complete this, each input line 115-118 and the corresponding line in driver block 100-103 have a termination impedance connected to ground that is twice the value of the cable characteristic impedance. For example, if a 100Ω cable is used as the serial input bus, the value of each termination impedance 140-143 in the resistor pack 144 is 200Ω. As a result, when the primary and redundant blocks are placed in the proper position, two such termination resistors will be in parallel, providing a termination impedance of 100Ω to match the characteristic impedance of the cable. However, if one substrate is moved, such as in the case of repair, a 200 ohm termination impedance remains, resulting in a terminal that can be tolerated for at least a short period, even if it provides a two-to-one mismatch.

A second form of a suitable terminal part is schematically illustrated in FIG. 2 showing the inlet cable connected to the primary and redundant blocks. Concentrating on the cable 145 for bus B1, in the device frame near primary block 0, where the cable forms a junction 146 which leads the cable 147 to the primary block and the cable 148 to the spare block. You can see that it ends. Since the cable 147 is looped as indicated by the break line 147a, the length from the junction to the back connector is equal to the corresponding length of the cable 148. Thus, different effects are produced by minimizing unequal cable lengths.

Taking these means, it has been found that the incoming data at the reception driver is only valid for about 50% of each period, ie only about 80ηsec of each 162ηsec period. Significant ringing, reflections, etc. are found in the initial portion of each pulse that finally settles around the end of the period when switching occurs again, resulting in incidental noise. An additional problem arises due to uneven propagation delays in the circuit elements that cause data to become unstable near the beginning and end of each pulse. However, the data is stable for almost all states from about 35% of the pulse to about 85% of the pulse. To take advantage of this fact, clocks L162 I ^* and L324I ^* are delayed in phase to occur at about 50% of each 162 nsec period. Thus, even if there is considerable noise, the data generated in the low level circuit is stably received by the network.

Referring to FIG. 4B, the parallel-to-serial portion of the converter circuit is shown converted in series to return to the low level multiplexer so that the parallel data switched through the network is distributed to lines, relay lines and service circuits. As mentioned above, the eight bits of the signaling and parity B8, B9 as well as the parallel data B0-B7 are decoded in the information memory and passed through the comparator to appear as CMPB0 ^* -CMPB ^* at the input of the parallel-to-serial converter. Resistor stages 150-152 provide suitable terminations. Data bits CMPB0 ^* -CMPB7 ^* are coupled to a pair of 8-bit latch circuits 153 and 154, one of which latch circuits providing each 96 channel bus serviced by a particular converter circuit. Data for the associated bus received by the latch circuit 153 appears on the line, which data is passed to the clock input of the latch circuit 153 through the inverter 156 to the low level parallel-to-serial strobe pulse LPSSTR ( Strobe in the latch circuit by x). At the same time, CMPB8 ^* and CMPB9 ^* are strobe in the latch circuit 159. In this manner, the data is sequentially paired at a suitable point by a low-level parallel-to-serial strobe pulse for this channel LPSSTR ^* (× + 1) coupled to the clock input via inverter 157 (a pair of latch circuits). 154, 160) is strobe. It takes about 1300 η sec to load the two pairs of latch circuits described above and six pairs of similar latch circuits for the additional six channel buses provided by the particular network block. Other network blocks perform the same function at the same time. At the end of 1300 η sec, the treatment process starts anew.

Before starting this, the data in the latch circuit is strobe into a set of stabilizing registers. This register, associated with latch circuit 153, consists of a pair of four-bit registers 161, 162 having a Q _D output of register 161 coupled to the J and K inputs of register 162. The registers 163 and 164 associated with the latch circuit 154 are similarly arranged. Register 165 is coupled to latch circuit 159 to receive signaling and parity bits during the first channel, and register 166 provides the same functionality during the second channel. Outside registers 165 and 166, only two bits are clocked out and sent twice each, so the A and B inputs are connected in parallel like the C and D inputs. This data from each latch circuit is loaded into the associated register, like the data on the other translator cards in the block, under the control of the low level load data output pulse LLDO shaped by the inverter 168. At this time, the data is clocked out of the register, in this case 0 to 7 bits, in the 162? Sec period under the control state of the low-level 162 output pulse L162O ^* formed by the inverter 169. Similarly, the signaling and parity bits are clocked out at a rate of 324 [eta] sec by the low level 324 output pulse L324O ^* buffered by the inverter 170. Referring to registers 161 and 162, serial data appears on output lines 172 connected in parallel to the four tri-state drivers in each driver block 100a-103a (FIG. 4C). These blocks are related to the input blocks 100-103 described in connection with the serial-to-parallel conversion and form the output portion of the low level end of the serial-to-parallel-to-serial converter. Serial data from the first 8-bit word is connected to the driver 174 in block 100 as well as similar drivers in other blocks. Serial data from registers 163 and 164 is connected to driver 175 as well as similar drivers in other blocks. The drivers 176 and 177 as well as their partners in the other three blocks receive 324 η sec signaling parity information from registers 165 and 166 respectively. Asterisks in the figures indicate the identity of the data passing through each driver. For example, driver 174 passes through the parallel-to-serial PCM data of group x PSPCM ^* G (x). Corresponding drivers in group 102a, i.e. drivers for block 2, pass through PSPCM ^* G (x + 16), i.e., similar groups for network block 2.

Some drivers are operated to pass a signal that is controlled according to the identity of the network block in question and the state of the NBDIS signal. Instantly ignoring the state of this signal, as in the case of decoder 105, the identity is fixed or programmable depending on whether a particular card acts as a primary block or as an extra block. Thus, the decoder 180 is provided to receive the identity codes NBID 0 FF ^* and NBID 1 FF as inputs to provide one of four outputs addressing one of the four blocks 100a-103a. As described with respect to the decoder 105, when the circuit acts as block 0, the inverted 0-0 is provided with an input, i.e. the two ID bits are high level, so that the output 181 outputs this signal. Because of the low level, the tri-state drivers 174, 177 are actuated when coupled through the buffers 182, 183. All other tri-state drivers on this circuit card become inoperable. Thus, the parallel data received from the comparator is stable and passes through the appropriate driver in drivers 174-177 to return to the cable to be serviced by block 0. We will now describe the circuit's response to the different confirmation codes.

If the circuit is formed by installing one redundant network block at a suitable place at one time, a device is provided to prevent one network block from continuing to operate, so that only the whole complete product is operated at a given time.

For this purpose, a network block disabled function NBDIS is provided and coupled to the disabled input 185 of the decoder 180. When this input is driven to a high level, the decoder 180 will not operate and all outputs will be at a high level, preventing the driver in blocks 100a-103a from passing any signal. Similar action is not related to the decryptor 105. Thus, even if the block does not operate, signals generated in lines, relay lines, etc., pass through the serial input drivers 100-103, are switched through the network, returned as parallel data, and processed through the register 161, and the like. do. Parity and other operational checks may be performed normally. However, if the block becomes inoperative, the decoder 180 acts to prevent all output drivers from working, thus preventing the block from affecting the cable returning data to low-level circuits for distribution to lines, relay lines, and the like. Thus, the network continues to operate for inspection by the maintenance software and does not affect the lines connected to the network block under test.

As shown in FIG. 3, the control signal for the network is produced by a state microprocessor and is coupled to an interface circuit in the network via one of the high level interface circuits 75, 75 '. Since the high level interface circuit is described in detail in the above-mentioned pitot, the application will be described only briefly.

As described in the above-mentioned Fitroda application, the control complex is fully redundant and includes redundant microprocessors and redundant bus structures. As a result, the high level interface circuit shown as a schematic diagram in FIG. 5 includes a number of two-to-one multiplexers that control data flowing into or out of one of the redundant microprocessors. The first two-to-one multiplexer 201 acts as an address selector and has as inputs not only address bits A0-A15 and address parity APs from COPY 0, but also corresponding bits from copy 1. . The data selection multiplexer 203 has as inputs D0-D7 and data parity DP bits from copies 0 and 1. The control selector 205 has a frame enable FE signal 206 generated in the high level interface circuit in response to receiving not only the write and read control signals of the boot at copy 0, but also its characteristic address. The copy 0 and copy 1 enable signals are provided to the copy select circuit 207 to produce control signals for the two-to-one multiplexer as well as other circuits as indicated by the block diagram. These signals act to select one of the two groups of input signals as the microprocessor copy operates.

An address parity checker 213 and a data parity checker 215 are provided to check each received word to detect parity error. If a parity error is detected, an address parity error APE or data parity error DPE signal is generated to set the latch circuit in the status word latch circuit 230, and all good decoders 211 are on all good ASW lines for operational copying. Let's make a pulse.

The address bits received from the working copy of the microprocessor are partially decoded in the high level interface circuitry and passed through to the lower order circuitry to be partially decoded. High rank bits A8-A15 are decoded to produce a joint control frame enable signal 206 in the high level interface address decoder 225.

The high grade bits, i.e. address bits A12-A15, should be in fixed form reserved for addressing high-level interface circuits, and address bits A8-A11 are back strap bits for a particular high-level interface board taken by strapping ST8-ST11. You have to match them. When all states are saturated, a frame enable signal is generated on line 206 and coupled back to control selector 205 to allow the control signal to pass from the working CPV. Mid-grade address bits A5-A7 are coupled to a 1/8 low-level interface decoder 227, which produces a file enable signal FLE0-FLE7 that activates each low-level device block. The 1/8 aberration detector 22P is provided to allow only one file enable signal to operate at a given time. When one or more file enable signals are actuated, a 1/8 error occurs, which is coupled back to the status word latch circuit 230 to set the appropriate latch circuit. Low grade bits A0-A4 pass through a pair of inverters 226 and 228 to pass to the low grade circuit for decryption.

Incidentally, the low level interface address parity generator 235 sends out the appropriate parity bits with each low class address word. The address bits LAC-4, as inverted by the generator 226, are also coupled to the maintenance permit decoding circuit 231, which is decrypted to provide the maintenance allowance signal MAC, and controls the write of the status word latch circuit to the maintenance mode. Is coupled to the status word write circuit 232. In short, when the proper address appears in the high-level interface circuit, the circuit is activated to generate an 1/8 file enable signal, not only to pass five bits of address data but also to address a particular circuit. Pass the file enable signal through a rating circuit.

Considering the addressing in the high level interface circuit, a circuit related to the data word will be described. This data bits D0-D7 from the working copy, such as through the data select multiplexer 203, are coupled to the read / write low level interface data gate 218. The control signal for this gate allows the data bits to pass when the repair does not allow the high level interface circuit MAC, when the failed latch circuit does not set TRBL and when the readout pulse is activated. At this time, data bits D0-D7 and DP pass through gate 218, which appears as low-level data LD0-LD7 and LDP, to a low class circuit, in this case to CPV interface circuit B (FIG. 3). Low level interface control gate 219 is provided to pass read R, write WR and high level operational HLA signals from the high level interface circuit to the low class circuit. As described in more detail below, data is received and processed according to the file enable, low-order address, and control bits that pass through it.

Another data distribution ranges from low level circuits, namely CPV A and B interface circuits, to CPV through high level interface circuits. For this purpose, the data bits LD0-LD7 received from the low grade circuit are coupled to the tri-state data bus 240 to pass back to the working copy of the microprocessor. The tri-state data bus 240 is enabled by the data one-state word select circuit 243 which enables the tri-state data bus when the device is not in the maintenance mode MAC and when the decode pulse R is present. . At this time, the data bits pass through the tri-state bus to form the input towel DIN0-DIN7 to which the data driver 221 is coupled. The data driver 221 combines input signals from the data driver control circuit 217 to receive the copy 0 and copy 1 operation signals. Thus, suitable gates in data driver circuit 221 are enabled to allow data bits to pass through lines D0-D7 of the working copy of the microprocessor. With this technique, low grade circuits can communicate back to the microprocessor.

Another data distribution ranges from high-level interface circuits themselves to microprocessors. In this case, the data in the status word latch circuit 230 is read into the microprocessor. To complete this, the data one-state word select circuit 243 switches its output lead in response to the maintenance operation signal MAC actuating. The tri-state data bus 240 is disabled and the status word selection circuit 222 is enabled. The status word selection circuit selects one word of the two words for transmission back to the CPV according to the state of the address bit A2. If there is a write pulse from the operational copy, the word selected by A2 is decoded from the status word latch circuit 230 and sent to the data driver 221 through the word select circuit 222 for transmission to the operational copy as described above. ) Is combined.

Finally, the CPU can add data into the high level interface circuit, which is coupled to the write pulse coupled via the control selection circuit 205 and directly coupled to the status word data latch circuit 230. Is made by.

In short, the working microprocessor controls all readout writes not only through the high level interface circuit but also through the low level circuit connected to the interface circuit. Call handling is primarily concerned with the possibility of writing data from the CPV into low-level circuits. However, all four data flow types are useful for repairing when the CPV performs a particular function to determine its operability.

In view of these advantages, FIGS. 6A to 6B showing the circuit system passages of the CPVA interface circuit 76 will be described. Address bits generated by the high level interface circuit as described above enter the CPVA interface circuit 76 at the input shown on the left of FIG. 6A. Recalling that there is a redundant high-level interface circuit connected to the network, the address bits from two copies are useful, which include parity LAPs, carry 0s and 1s, as well as the low-grade address bits LA0-LA4. All signals of s serve as inputs for the two-to-one multiplex address selector 301. Only two of the file enable signals generated by the high level interface circuit are needed in the network, and the signals FLE4 ^* and FLE5 ^* for copy 0 and 1 are provided as inputs to the two-to-one multiplexer 302. The control input of each copy is also selected by the multiplexer 302, where a write pulse LWR ^* and a decryption pulse LRPL ^* for each copy are provided as inputs. The passing of the input to the output is determined by the state of HLA ^* / 1 that the output is inverted by the inverter 303 coupled to the selector input of the multiplexers 301, 302. The high level operating signal HLA / 0 for copy 0 is also inverted by the generator 304 in this case, and an exclusive OR gate whose output indicates that only one high level interface circuit is in operation under normal conditions. 305 is coupled with the output of inverter 303 to the input. When two high level interface signals appear to be active, the output of the exclusive OR gate 305 is switched to a low level so that the CPVA interface circuit is unresponsive.

A parity check structure will be described that acts as a device for detecting faults in each network block. The low grade address bits LAC-4 and parity LAP are coupled as inputs to a parity checker 308 whose output is coupled to the D input of the address parity error latch circuit 309. Since the clock input of the latch circuit is controlled by the NOR gate 310 whose output is gated through the other AND gate 311, the clock signal is obtained by the flip-flop circuit 309 deciphering block repair per circuit NBMNTRD, network block repair. Occurs when a write NBMNTWR or network block call processor is in the reset state for the NBCPWR control function. If the appropriate conditions occur at the same time, the flip-flop circuit 30 is set to generate the address parity error signal APEFF.

A data parity error flip-flop circuit 314 is provided for generating a DPEFF signal that indicates detecting parity error in data from the high level interface circuit. The data is operatively coupled to the CPVB interface circuit 77 as described in detail below, which generates a CPOVB data parity error signal CPVBDPE coupled to the D input of the flip-flop circuit 314. This flip-flop circuit is clocked similarly to the flip-flop circuit 309 except that it does not respond to the function NBMNTRD. Another pair of latch circuits 316 and 319 are provided to indicate parity error from the connection memories 1 and 2 which generate output signals CMOPEFF and CMIPEFF. Parity is checked with each word that is decrypted in the access memory. These words are used to address the information memory to decrypt the stored PCM data. Flip-flop circuit stages 316 and 319 are essentially two stages. For example, stage 316 permits first block flip-flop circuit 317 to clock the connection memory 0 parity error signal CMOPE in the flip-flop circuit under the control condition of the connection memory parity error clock CMPECLK ^* , and the network block maintenance. And a second stage for clocking the output of the flip-flop circuit 317 in the flip-flop circuit 318 under the control state of the signal NBMNTACC. Stage 319 is similarly arranged.

Referring back to the incoming address signal, the lower three bits LA0-LA2 are decoded by the circuit denoted 320 for use in the CPVA interface circuit, and the CPVA interface signal CPVAAO ^* for use in the CPVB interface circuit. Buffered by an inverter 321 to form -CPVAA2 ^* . Two upper-order low-order address bits LA3, LA4 are connected as history to a pair of comparators 323, 324 to selectively address each block in the network, and the FLE5 signal coupled to the comparator is used to address other capabilities. It is also used to distinguish between complement and call handling functions.

Referring to a general comparator, comparator 323 responds to a repair command, and comparator 324 responds to a call processing command, even under which circumstances a repair command arrives at this comparator 324. The enable inputs of these two comparators are driven by the output of the exclusive OR gate 325 with FLE4 and FLE5 inputs. Thus, one signal of the signals ELE4 and FLE5 must be at a high level in order for the processor to reach the network. According to the second instruction request, the output of the exclusive OR gate 305 is compared to one in two comparators. Gate inputs are HLA0 and HLA1. Therefore, only one circuit of two high level interface circuit types should be in operation to allow the processor to reach the network.

Referring to complementary comparator 323, three input signals NBIDO-NBID2 are provided to this comparator to compare LA3, LA4 and LA5, respectively. The NBID 0-2 function is hardwired on the back of each network block to assign a complement address. In the case of the primary block, NBID0 and 1 carry the ID code described in the previous table, and NBID2 is zero in all cases. In the case of redundant blocks, NBID2 is strapped to a high level, and both NBID1 and 0 are in a low level state. These three address levels are compared with LA3, LA4 and FLE5. In other words, the two digits above the low-level address signal carry the indication code (or 0-0 of the extra block) of the particular block for maintenance, and FLE5 must be low-level or extra block to address the primary block. It must be at a high level to address. Therefore, when one of the high-level interface circuits shows three bits in the CPV interface circuit, and when FLE4 and 5 are in opposite states, the comparator 323 is saturated, and the repair circuit repairs in the block. Create an output that allows you to decrypt or write the ports.

As in the case of the comparator 323, the comparator 324 receives the LA3, LA4, and FLE5 signals from the high level interface circuit. This compares LA3 and LA4 to PNBID0 and PNBID1, respectively. The two bits PNBID0 and PNBID1 are hardwired to the primary block as allocated to the block, and may be programmed for the extra block to be the same as the primary block. The FLE5 signal is compared with the PNBID2 generated by the CPVA interface circuit itself. The PNBID2 bit is programmed by the repair circuit to 0 for the block going online and to 1 for the offline block. The common control circuit then forms all normal call processing instructions with the FLE5 bit low (FLE4 high) so that the comparator 324 is saturated. This is a steady state causing the common control circuit to reach the network block to write the connection within. However, as will be clearer, it is desirable for the repair circuit to fill in the connections, but this capability is not provided through the repair ports. Thus, the repair circuit has the ability to set the PNBID2 bit on the CPVA interface card to 1 and then generate a call processing instruction with FLE5 set to high level so that the comparator 324 is satisfied. The importance of this capability can be better understood by considering the CPVB interface circuit.

In the case where it is desirable for the common control circuit to reach a particular network block in the maintenance mode, this circuit is suitable for saturating the comparator 323 in this block to produce the output signal used in the decryption circuit 326 to achieve the desired repair function. Export the address to output. For example, the NAND gate 327 gates the repair circuit access code with a low level read pulse LRPL to make the network block repair function NBMNTRD. The NAND gate 328 gates the repair circuit access signal with CPVAA2 and the low-grade write pulse LWR to make the network block repair write function NBMNTWR.

The output of the call processing comparator 324 is decrypted in the gating circuit along with the write function to produce the desired call processing control signal. The NAND gate 330 gates the call processing access signal generated by the comparator 324 with the CPVAA2 ^* signal at the output of the inverter 331 and the low level write signal LWR for making the network block call processor write signal NBCPWR. . Further signals are also generated that are not gated to the particular address decrypted by comparator 324, but affect all network blocks at the same time. These signals are the low level clock write LLCWR ^* at the output of the inverter 333 and the low level clock read LLCRPL ^* at the output of the inverter 334, which is operated by standing or decode pulses that have passed through the high level interface circuit, respectively. .

Referring back to CPAAAO-CPVAA 2 signal gating circuit 320 to decode, AND gate 340 is the output CPVAAI ^* and the inverter in the CPVAAO ^*, the inverter 342 in the output of the inverter 341, Go to gate 340 via 343 and provide to decrypt the network block complement write signal NBMNTWR, which is decrypted by AND gate 328. Thus, the output of the gate 340 is operated with the appropriate type of low-grade address LAO and LA1 bits when the CPV addresses the network high level interface circuitry, particularly when addressing a block in the network in the maintenance mode. The output of AND gate 340 partially enables NAND gate 345 (FIG. 3b) to pass CPV data bit 3 CPVD3 buffered by gate 346 to produce comparator interface parity error cancellation signal CIPECLR ^* . Let's do it.

신호은 데이타흐름을 제어하도록 회로망의 정보 메모리 회로에 사용되는 고레벨 정보메모리 멀티플렉스 석택신호 IMMVXSL을 발생시키도록 반전기(357)로도 통과된다.The output of AND gate 340 also partially enables a pair of AND gates 348 and 349 that receive input CPVDBO and CPVDB1, respectively. The outputs of these gates control the failed flip-flop circuit 351. Therefore, when the AND gate 340 is saturated, the CPV data bit 0 is set controlled through the failed flip-flop circuit 351 and the CPV data bit 1 is reset controlled. When the flip-flop circuit is set, its Q output is at a high level, which acts through a pair of inverters 352 and 353 to produce the working network block failure flip-flop circuit signal NBTBLFF. The high level Q signal also passes through a NOR gate 355 and an inverter 356 to create a high level network block disable function NBDIS. This is a signal in which the series-to-parallel-to-serial interface circuit is coupled to the child so that the tri-state driver that applies data on the feedback bus to the low-level multiplexer does not work. Thus, the failed flip-flop circuit 351, after being set, acts to prevent the network block from working when asked for feedback data to the low-level multiplexer. Resetting the latch circuit puts the block in question back on line. High level

The signal is also passed to inverter 357 to generate a high level information memory multiplexed granular signal IMMVXSL used in the information memory circuitry of the network to control the data flow.

Referring back to the decryption circuit 320, another gate 360 is provided that is saturated when both CPVAAO and AA1 are at high levels in the presence of the network block repair write function NBMNTWR coupled via an inverter 343. . The output of AND gate 360 partially enables a number of AND gates 362-367 to cause the table processor to write into latch circuits 370-372 when addressed this way. Only the latch circuit 370 should be written in the primary block, and all the latch circuits should be written in the spare block. Since the actuating circuit element has the same form as described with respect to the latch circuit 351, the arrangement thereof will not be described in detail. CPV data bit 0 ^* is used to write the latch circuit 372, i.e., to write the low level state that acts to set the latch circuit and the high level state that acts to reset the latch circuit.

When set, the Q output of latch circuit 372 generates a low level NBDOFF ^* corresponding to the high level network block IDO flip-flop circuit signal NBDOFF. When the latch circuit is reset, the opposite state is generated. Likewise, the CPVBD 1 ^* signal controls the latch circuit 371 to generate a high level PNBID2 when set. Finally, the CPV data bit 2CPVDB2 ^* controls writing the latch circuit 370 to generate a high level PNBID 2 signal when set. It will now be appreciated that the CPV controls the latch circuits 370-372 to generate a latch address signal that assigns equality to the redundant block and to control the PNBID 2 state for all blocks.

The allocation of block identity is done in the following way. In the case of the primary block, PNBIDO and 1, the inputs of the serial-to-parallel-to-serial converter (FIG. 4) and the CPVA interface circuit (FIG. 6), are hardwired on the back side. In the case of redundant blocks, the state of these inputs is controlled by programmable latch circuits 372 and 371. In the case of all blocks, ie primary and redundant blocks, PVBID 2 can be programmed by latch circuit 370. The control circuitry can program the ID2 bits of the block to control the response of the ID2 bits of the block to the call processor write command. This bit can be programmed to cause the block to respond in order to repair the call handling write command, ignoring the original call handling write command or vice versa. Finally, the failed latch circuit 351 can be programmed to control the response of one network to which all the information flows through this circuit, i.e. primary and redundant blocks. Once the latch circuit for a particular block is set, the high-level NBDIS signal generated by the latch circuit 351 is serial-to-parallel-as described above to simply disable the block output so that the PCM information flow is offline as long as it is relevant. To control the serial-to-serial converter (FIG. 4).

This arrangement provides considerable flexibility.

Considering the PCM information flowing through the network, the network type is controlled by the respective failed latch circuits. These latch circuits are programmed so that one block is always off-line to hold the entire refill of the block on line at one time.

Reaching each network block by the control circuit is not limited by the failed latch circuit. The control circuitry can selectively reach blocks in the maintenance mode by hardwired addresses and comparators 323. A control circuit with a suitable modification of the PNBID 2 bits can write connections in on-line blocks, in off-line blocks, or in parallel to these two blocks. These connections can be entered in either the maintenance mode or the initial call processing mode.

As an example, if the repair circuit sets the latch circuit 370 for a particular block to provide a high level PNBID 2 signal, and FLE5 is always at a low level during the initial call processing write period, this block may not respond to this command. none. Therefore, if it is desired that the repair circuit allocates the identity of the primary block to the spare block and writes the connection into the spare block rather than in the primary block, it is simply PNBID 2 to prevent the primary block from responding to the call processing write command. Can be washed to a high level for the primary block and to a low level for the extra block. . This can be done even if the primary block acts when repairing the connection. If it is desirable for the primary block to respond back to the call processing write period, then PNBID 2 is returned to the low level by the complement circuit for the comparator 324 to respond again. Optionally, the repair circuit can set PNBID 2 to a high level in the case of redundant blocks and to a low level in the case of the primary block, and use a maintenance call processing instruction to write the connection into the spare block rather than the primary block. do. Since the control circuit simply addresses the network during call processing, such as a memory area, the repair circuit can form a network such that the area addresses the primary block, redundant block, or these two block responses. Therefore, even if the call processing addresses different pieces of hardware after switching blocks, there is no need to change the instruction.

In an exemplary embodiment of the present invention, programming of block identity can be done automatically by a common control circuit or manually by a technician. As described above, in the maintenance mode, the control complex has the ability to write latch circuits 351 and 370-372 to exchange spare blocks and primary blocks. The ability to accomplish this is provided manually by the maintenance panel associated with the network frame. This panel provides an apparatus for controlling the same and faulty flip-flop circuits shown briefly in FIG. 6B as an array of pushbutton switches 380-387. These switches provide inputs to the associated negative logic NAND gates 388-395 that set or reset the associated latch circuits in the latch circuits 351, 370-372.

A suppression signal for the NAND gates 388-395 is provided by the output of the complement decoder 323 to prevent certain CPVA interface circuits from being manually switched when associated with the complement mode. However, at other times, the above-mentioned NAND gates are all partially enabled for the associated latch circuit to respond by pressing any of the switches 380-387, for example, pressing switch 380 will latch. Two sets of complementary panel network block indication bits MPNBID 2S ^* coupled to circuit 370 are generated, so that its Q output is switched to a high level. The switch 381 acts to reset the flip-flop circuit. Similarly, switches 382 and 383 set and reset ID1 flip-flop circuits 371 and switches 384 and 385 set and reset IDO flip-flop circuits 372, respectively. Finally, switches 386 and 387 set and reset the failed flip-flop circuits 386 and 387, respectively. Therefore, the technicians can assign the sameness to the redundant network block, exchange the redundant block with the primary block, and can selectively switch block on or offline with respect to control and switching of PCM information.

7A-7E, a circuit of CPVB interface 77 is shown. As noted above, the CPVB interface circuitry operates in the maintenance and call processing mode. The data bus that couples the CPVB interface circuit to the high level interface circuit is shown in (400, 7a) and includes low-grade data bits and parity LDO-LD7, LDP for copy 0 and copy 1 high level interface circuits. . These signals are coupled to a two-to-one multiplexer with a selector input driven by an HLA ^* / 1 signal coupled through an inverter 402. Thus, data bits DC-D7 and parity DP from the active high level interface circuit appear at the output of multiplexer 401. Parity is checked by parity checker 404 which generates a CPVBDPE parity error signal in response to the detection of an error. The data bits D0-D6 are thus connected as inputs to the low grade data register 405 and the high grade data register 406 (Fig. 7B). Likewise, data bits D0-D7 are coupled to the low grade address register 407 and data bits D0-D5 are coupled to the high grade address register 408 (FIG. 7G).

Thus, once a particular network block is addressed, the control complex has the ability to selectively load data into each of the four registers mentioned above. How to accomplish this is described next.

At the moment, it will be said that data is loaded into the low and high grade data registers representing the number of network slots formed and other data is loaded into the high and low grade address registers representing the connection memory addresses to which the connection is to be written.

Referring first to the address registers 407 and 408, their outputs are the bit counters in which the tri-state driver array 410 (Fig. 7d) passes the signal through the inverter 412 to the enabling input of the driver. When operated by the Q _D output for 411, it passes through this tri-state driver array 410. This data can then be loaded in parallel into counter 414. The counter outputs are inverted by the inversion driver 415 to provide the connection memory parity error clock signal CMPECLK ^* through the connection memory address signals CMA 0 ^* -CMA 9 ^* , the connection memory data latch signal CMDL ^* , and the double inverters 416, 417. Is buffered).

Similarly, the outputs of the low and high grade data registers 405 and 406 are connected memory data signals CMD 0 ^* -CMD 5 ^* , CMD 7 ^* -CMD 12 ^* , and the low and high grade parity bits CMDPLO ^*. And through inverting driver 420 to make CMDPHI ^* . Drivers in array 420 directly receive data bits D0-D3 to make CPV data bits CPVBD 0 ^* -CPVBD 3 ^* used as a function of the CPVA interface circuit as described above. One of the functions of these bits is to set and reset the check and fault latch circuits 370-372 and 351.

Before describing the operation of the circuit described so far, first, a pair of decoders 425, 426, and FIG. 7 used in the operation of the write connection unit in the connection memory will be described. Once the high and low class address and data registers are complete, the comparators respond to specific bits in the high class address register to generate a write signal for connection memory 0 or connection memory 1.

In this case, the connection memory is not redundant, but a pair of connection memories provided when the network forms three port comparisons.

Therefore, when comparing three ports, the number of network slots of the parts 2 and 3 should be written in the part 1 positions in the connection memories 0 and 1, respectively. Similar connections are written in each of the three parts.

Referring to the comparators 425 and 426, the enable input is a buffer full latch circuit 428 that produces a high buffer total signal when loading data for a connection into which four buffer registers are to be written, as described in more detail below. Driven by the output of When enabled, the two comparators 425 and 426 both compare the 3Q, 4Q and 6Q outputs of the high order address register 408 against PNBID 0, PNBID 1 and PNBID 2, respectively. Therefore, the third and fourth bits of the class address register are compared against the network block check kyode, hardwired for the primary block, and programmed for the redundant block. The sixth bit is programmed to be zero in case of normal call handling write pole and 1 in case of complement call handler recall, recalling the limitation imposed by comparators 323, 324 on the CPVA interface circuit. The PNBID 2 function is compared.

Finally, the fifth bit of the high order address register is compared to zero in comparator 425 and one in comparator 426. This fifth bit is programmed to select connection memory 0 or 1, so if 0, the comparator 425 is saturated, and if 1, the comparator 426 is saturated. The outputs of the comparators 425 and 426 are coupled to the D inputs of the respective latch circuits 430 and 431 having the output gated at 432 and 433 to form respective connection memory write signals CMOWR and CMIWR. In addition, the output of these gates is provided to a NOR gate 434 having an output that clocks a monostable multivibrator 436 that produces a clear CLR signal used to reset portions of the write circuit.

The structure and function of the remaining circuit elements can be seen more clearly by explaining the operation cycle. As described above, the CPVB interface circuit not only not only writes a new connection, but also during the normal period of the network in which a position in the connection memory is sequentially addressed to decrypt the already written connection for using this information to address the information memory, It acts to address the connection memory. Each network block has 772 timeslots, with 768 timeslots provided to the working channel and lost to 4 timeslot framing. In an exemplary embodiment, if the operating channel is not addressed during the four framing timeslots, the connection memory can receive new connection information from the common control circuit.

Finally, counter 414 is used to address the connection memory locations for call processing in turn, and to address specific locations during framing of the reset period to write new connections.

In view of this, it can be seen that the water collector 414 is formed with a modulo 4096 counter. This counter is clocked by the 41 nsec clock signal produced by the low level clock and has a period which is terminated during the reset period by another signal resulting from the low level clock. The reset pulse is 648nsec wide and 125μsec in duration.

If it is the beginning of the reset period and the connection data is not loaded into the register for writing into the connection memory, the reset signal CMRST is inverted by the inverter 440 to appear at the D input of the flip-flop circuit 441. do. This signal is clocked into the flip-flop circuit after 80 mu sec under the control state of the low level connection memory 81 mu sec clock LCM 81 ^* inverted by the inverter 442. Accordingly, the Q output of the flip-flop circuit 441 is driven to a low level, and this low level output appears at the D input of the second flip-flop circuit 444. This low level output is clocked into flip-flop circuit 444 after 41 nsec by LCM 41 ^* inverted by inverter 445. The low level Q output of flip-flop circuit 444 is provided to the load input of counter 414. As will be seen more clearly below, during the second half period of each 648 μsec reset pulse CMRST, the three-state driver 410 is disabled. In this state, all counter inputs are brought to high level by pull-up resistors connected to this counter. Accordingly, the 41 nsec clock pulse LCM 41 following the clock input of the counter 414 clocks all 1s in this counter. When the reset pulse ends, i.e., when the CMRST returns to low level, this signal is clocked through the flip-flop circuits 441 and 444 as before removing the load signal from the counter 414. Since the counter states are all kept at 1, the next 41 [mu] sec clock pulse advances the counter to coefficient 0, addressing the first position of the connected memoline through the address lines CMA 0 ^* -CMA 9 ^* . Each time slot has a width of 132 μsec and the counter 414 is clocked at a 41 μsec ratio, so that the connected memory address whose lowest bit comes from the third stage of the counter changes in a 162 μsec period. The second bit of counter 414 is inverted to produce a CDML ^* signal such that the CMDL ^* signal provides a positive-to-subconversion at 81μsec points of each 162μsec period.

Since the function of this signal is to latch data to be decoded from the addressed connected memory location, the latched data is used to address the information memory to decode a sample from the connected portion.

At the end of the 162 μsec period, the second bit of the counter 414 is switched again to perform positive-to-negative conversion of the connection memory parity error clock signal CMPECLK ^* , which acts to latch the parity error state from the connection memory card. Actuates through inverters 416 and 417 to cause it. At this time, the connection memory address is incremented by one.

At the end of the number 767 the extended reset pulse again loads all 1s in the counter as already described.

At this time, all 768 positions of the connected memory are decoded and the cycle starts to be renewed.

Before describing the correspondence period when a new connection is joined, a description will be given of how the data and address registers are loaded before the connection memory write cycle. This load operation can be taken upon passing and the counter 414 is activated upon sequential addressing of the connection memory.

The load of the address and data registers is under the control state of the readout circuit indicated by 450. The CPVA address bits CPVAA, O ^* CPVAA 1 ^* described with reference to FIG. 6 are decoded and gated by the network block call processor NBCPWR in order to load four registers at the time of question. For the first write operation, CPVAA 0 ^* and CPVAA 1 ^* are AND gate 451 when NBCPWR is shaken to a high level and saturated to clock bittabits D0-D5 in the class address register 408, It becomes a high level. For the second write operation, CPVAA 0 ^* goes low and CPVAA 1 ^* saturates when AND gate 452 clocks data bits D0-D7 into low-grade address register 407 when NBCPWR is present. It is kept at a high level so as to be in a state.

Thus, at this time, the low-level address register is selected from connection memory address bits 0-9, two bits corresponding to ID 0 and ID 1, bits for selecting connection memory 0 or connection memory 1 to write, and complementary call processing write cycles. Contains the PNIB2 bit that identifies the call processing.

In the case of the third part of the load cycle, CPVAA ^* goes to high level and CPVAA 1 ^* goes to low level, so when NBCPWR is present, AND gate 453 is saturated. The output of this gate is connected to the clock input of the high-level data register, thereby clocking bits D0-D6 into this register.

Finally, in the case of the fourth part of the write period, both CPVAA 0 ^* and CPVAA 1 are at high level, so when NBCPWR is present, AND gate 454 clocks data bits D0-D6 into low-grade data register 405. To be saturated. This data register then contains two bytes (each of which has parity) of data representing a connection portion to be written into the connection memory. Data bit D7 is always supplied to the D input of the buffer full latch circuit 428, which has a high level during the last write period and has a clock input driven by AND gate 454. Thus, during the fourth phase of the load period, The buffer full register 428 is clocked to drive the Q output to a high level, creating a high buffer full BFL signal. This signal allows the comparators 425 and 426 to produce a high level signal in accordance with the state of the high grade address bit register so that the comparators 425 and 426 produce a high level signal in accordance with the state of the high grade address bit register. Enable). The comparator that is enabled depends on the connection memory being written. The output signal is held at the corresponding Q input of the flip-flop furnace 430 or 431 in preparation for the reset period to be described next.

출력은 고레벨로 구동시킨다.

출력의 증가연부는 플립-플롭 회로(430, 431)을 클럭시키므로, 한 입력, 즉 플립-플롭 회로(430)의 입력에 나타나는 고레벨 신호는 이것의 Q출력을 고레벨로 구동시킨다. 이와 동시에, 고레벨

출력은 4개의 비트 계수기(411)에 인가된 부하를 제거시키도록, 이 계수기를 해독하게 되어, 모든 동작동안 이것의 출력들을 모두 1로 유지시킨다. 41μsec 후인 LCM 41의 다음 이송시에, 계수기(433)은 모두 0상태로 클럭된다. 반전기(412)에 의해 반전된 저레벨 Q_D는 3중-상태구동기(410)의 엔에이블 입력에 인가된다. 계수기(414)의 부하입력은 플립-플롭 회로(444)가 계수기(414)의 클럭-입력에 인가된 다음의 41μsec 클럭펄스의 상태를 변환시킬때 저레벨로 스위치 되었기 때문에 저등급 및 고등급 어드레스 비트레지스터로부터의 데이타는 3중-상태 구동기를 통과하여 계수기(414)에 클럭된다.As already described, 121 μsec after the CMRST is increased, the low level signal from the flip-flop circuit 441 is clocked into the flip-flop circuit 444 to drive the Q output of the circuit to a low level.

The output is driven to a high level.

Since the increasing edge of the output clocks the flip-flop circuits 430 and 431, a high level signal appearing at one input, i.e., the input of the flip-flop circuit 430, drives its Q output to a high level. At the same time, high level

The output is decoded to remove the load applied to the four bit counter 411, keeping its outputs all 1 during all operations. On the next transfer of LCM 41, 41 μsec later, the counter 433 is all clocked to zero. The low level Q _D inverted by the inverter 412 is applied to the enable input of the tri-state driver 410. The low and high class address bits are loaded at the counter 414 because the flip-flop circuit 444 was switched to low level when the flip-flop circuit 444 transitioned the state of the next 41 μsec clock pulse applied to the clock-in of the counter 414. Data from the register is clocked into the counter 414 through a three-state driver.

As a result, the counter 414 transfers the address already loaded into the registers 407 and 408 and the output of the driver 415 addresses this position in the connection memory. The clock pulse loaded with the counter 414 advances the counter 411 to the coefficient 1.

The next clock pulse does not change the state of the counter 414 because the Q _D output of the counter 4110 continues to operate the triple-state driver, so that a specific address is continuously applied to the parallel input of the counter 414. .

However, the multiplier 411 continues to count 41 μsec clock pulses. When the coefficient 4 is reached, the high level Q _c output is related to the high level Q output of the flip-flop circuit 430 to invert the AND gate 432 to saturate the AND gate 432 to produce the connection memory O write signal CMOWR. Gated to Q _D inverted by. Therefore, data held in the latch circuits 405 and 406 is written into the connection memory 0 at the address held in the counter 414.

Since the write signal is held until the multiplier 411 is advanced by the coefficient 8, it becomes a 16 mu sec period. When this occurs, gate 432 is disabled like tri-state driver 410 by the high level signal on output Q _D of counter 411. The next 41 μsec clock pulse loads the counter 414 all to one. After the CMRST returns to the low level, the scan period of all the connected memory addresses is completed as described earlier. The CMOWR signal is then switched to a high level to write the connection memory, and the NOR gate 434 is saturated to trigger the one short multivibrator 436 with a nominal period of 800 μsec. The output of the one short multivibrator 436 is coupled via the NOR gates 438, 437 to the clear input of the flip-flop circuits 430, 431 as well as the clear input of the buffer full flip-flop circuit 428. Thus, this signal acts to reset these flip-flop circuits so that they are ready to receive new connection data from the common control circuit.

At the end of the reset pulse CMRST, the latch circuits 441 and 444 are clocked as before and ultimately the Q of the latch circuit 444 so that the counter 411 loads all 1 in parallel when preparing for the next reset period. Will be driven to low level. Network operation continues along the lines described herein, all time slots are scanned every 125 microseconds, and the connections are written in a framing period that occurs every 125 microseconds each time the control complex determines that such a connection is to be written.

Optionally only one operation mode for writing the above-mentioned connections is available. Using this mode, one word of the connection memory, i.e., the first half of the two common connections, can be written during the framing period.

It is also possible to provide a secondary buffer such that two connections are written during the framing period. Alternatively, the connections can be written during the sequential scan period of all channels. In the case of this mode, the comparator is used to compare the latched address by the counter 414 to write the current address output. If a match is detected, the connection is written.

In addition to the stresses described so far, the repair circuit has the ability to write information to and decode information from the network block via the CPVB interface circuit. Referring to FIG. 7A, a state selector having a data output LD 0-LD 7 and a parity LDP of copy 0 and copy 1 of a high level interface circuit is shown. Information placed on this line is controlled by three selector bits that address multiple three-bit multiplexers in state selector 460. The selector input is a function CPVAA 0-CPVAA 2 that occurs in the CPVA interface circuit.

When the network block repair decoding function NBMNTRD is present, a specific code on this selector line causes the output line to be in the state of the selected input. For clarity, the inputs are shown in the table shown in FIG. 7E.

Effectively, the data shown in this table is coupled to the appropriate inputs of the multiplexer, to the address shown on the CPVAA line, so that this data is output to the output. Addresses 0-3 select the high rank address register, the low rank address register, the high rank data register and the low rank data register, respectively.

Thus, the repair circuit can reach the output of these registers to determine whether the already written information has been properly received. Address 4 serves to decode the functions associated with the repair circuit. Bit 0 indicates the status of the failed flip-flop circuit, and bit 1 indicates whether the block is a primary block or redundant block at the time of interrogation. Bit 1 is programmed by strapping the associated connection to ground for a given network block and a positive supply for a spare block. Also, bit 2 indicating the state of the address parity error flip-flop circuit, bit 3 indicating the state of the data parity error flip-flop circuit, and the state of the comparator interface parity error flip-flop circuit on the comparator interface circuit board 0 and 1 respectively. Bits 4 and 5 representing are decoded. Similarly, bits 6 and 7 decode the states of parity error flip-flop circuits for connection memories 0 and 1, respectively.

Address 5 is used to call the low-level clock with bit 0, which reads the status of the failed flip-flop circuit and bit 2, which reads the status of the error flip-flop circuit. The word corresponding to address 6 is not currently used. The word selected by address 7 decrypts the network block identity to the block in question, with bit 0 going to PNBID0, bit 1 to PNBID 1 and bit 2 to PNBID 2.

The ability of the repair circuit to join the state portion of the network block has already been dealt with. In summary, addresses 4-7 are used for the complementary write operation, where the data bits for the write operation pass through the CPVB interface circuitry and the addressing is decoded in the CPVA interface circuitry. As in the case of a complementary decryption operation, bits CPVAA 0-CPVAA 2 select a particular word. Data bits CPVBD 0-CPVBD 3 provide write activity data, with the function LLCTBFF being equivalent to CPVBD 0 for one address. Address 4 calls the CPVA interface circuit, CPVDB 0 sets the failed flip-flop circuit, CPVDB 1 resets the flip-flop circuit, and CPVBD 3 resets the common error flip-flop circuit on the card. Let's do it. Address 5 calls the low level clock card, LLCTBFF sets the failed flip-flop circuit on this card, CPVBD 1 resets the circuit, and CPVBD 3 resets the low level clock error flip-flop circuit. As in the case of the maintenance read operation, address 6 is not used. Address 7 calls the CPV interface circuit A card. Functions CPVBD 0 ^* and CPVBD 1 ^* are only written to the spare network block to program PNBID 0 and PNBID 1, respectively. As already described, the function CPVBD 2 ^* programs the NBID 2 function for all network blocks.

The detailed circuit description of the connection memory and the information memory will not be described because it is not important for understanding the present invention. Such a memory arrangement is described, for example, in US Pat. No. 4,031,328 to Petroda. Those skilled in the art can form memory elements and associated components to exchange data passing through the circuits described in detail herein.

In summary, the specification describes a satun-type network in which an extra network is provided to each element in the network at the expense of a single redundant network block network. The exemplary embodiment can be made up of four primary blocks, all serviced by a single redundant block, thus reducing manufacturing costs. Even in small systems using less than four primary blocks, significant savings are achieved because the control state remains the same regardless of the size of the system. In addition, the ability to handle all systems, whether small with a single primary block or large with four primary blocks in the same form, is a big advantage.

Switching from the primary block to the spare block or from the spare block to the primary block is a very simple operation.

This exchange has the ability to write a latch circuit to the CPVA interface circuit, so that it can be done by a repair circuit that assigns equality to redundant blocks, or by a technician operating a manual switch that controls these latch circuits.

If an exchange is made, the call process simply writes a command to write the connection to the particular address served by the spare block at the location of the primary block (or by the primary block at the location of the spare block in the case of a reverse exchange). Because of derivation, this call handling does not know to change.

The repair circuit has considerable flexibility in distributing on-line blocks and off-line blocks. For example, in an exchange operation, the repair circuit can perform a repair call processing write around the block to be operated without affecting the call processing. Thus, a memory map stored by the state processor for the block that is found to be broken can be used to write the same connection into the redundant block before putting the connection on the line.

The maintenance call processing write cycle is performed by setting the PNIB2 bit to 1 and executing a write command in a specific block. If this bit is later switched to zero and the primary block remains zero, both blocks can be written in parallel. Finally, due to the fact that the offline block is disabled only in the driver which returns data to the low level multiplexer, the offline block can be activated and checked. More specifically, even if a block is offline, the disable function continues to be identical by ID bits 0 and 1, even if the disable function does not affect the feedback bus.

Therefore, voice data entering the primary block having the same identity as the spare block flows through the spare block even when offline. Proper parity checks are made to ensure that the block is healthy and to selectively isolate faults. By simply switching PNIB 2 to a high level, the control complex has the ability to write connections to offline blocks during maintenance, which is more helpful in fault isolation. In short, it can be thought that providing only a single spare block limits flexibility, but in practice it provides considerable flexibility.

Claims (1)

The stored program common control circuit 51 and the connection section are set up to selectively interconnect the multiple access ports 32, 30, 31, 39, 40, and 41 so as to establish a call path between the desired ports. Sample the access port periodically to produce a digital dataword on the input buses 46, 47 for the network representing the sampled information, and having the network 50 responsive to the control circuit for A telecommunication switching device in the form of returning a digital dataword on an output bus from a network to an access port for partitioning, comprising: a device for assigning a unique identity code and a network block for allocating a specific network block to a write connection. Each comprising an addressing device 351 responsive to the common control circuit 51 for generating an identity code of Multiple primary network blocks 60, suitable for providing a connection to each of the assigned access port 32, 30, 31, 39, 40, 41 groups 35, 33, 34, 38, 40, 41 61, 62, 63); Match the identity code of the failed network block with the programmable identity code 372, 371, 370, which can be optionally set to match all access ports and the identity code of the primary blocks 60, 61, 62, 63. Programmable devices (351, 370, 371, 372) for setting the identity code of the redundant network block and the access point group assigned to the block in which the redundant network block has failed. A telecommunications switching device, comprising a single redundant network block (64) having a programmable device (351) for disabling the failed network block to respond and for enabling the redundant network block (64).

Images