KR830000477B1 - Automotive electrical systems - Google Patents

Abstract

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Description

Automotive electrical systems

1 is a general "block" diagram of the electrical system of a road vehicle.

2 is a block diagram of a transmitter forming part of the FIG. 1 system.

Figure 2a is a diagram illustrating the output from the transmitter of Figure 2;

3 is a block diagram of a receiver forming part of the FIG. 1 system.

4, 5, and 6 are circuit diagrams showing part of the receiver of FIG.

7 is a circuit diagram showing one load circuit of the receiver of FIG.

The present invention relates to a general-purpose automotive electrical system in which several electrical loads wired around the vehicle are regulated by a central console or switchboard.

In a typical electrical system, a switch directly controls the load, ie each switch is connected to the associated load or loads by a single flowing cable. This method is very ineffective for the use of conductors and requires the creation of complex wiring harnesses for vehicles.

As an idea to reduce the use conductors and simplify the wiring arrangement, it has been proposed to use a "multi-plex" control system in a vehicle. The electrical loads created by these systems are interconnected by relatively simple main wiring and the control switches do not directly control the load current, while they are only used to generate control signals that specifically determine whether or not the load is loaded.

In particular, it has been proposed to digitally control the load using a transmitter that is sensitive to the state of several regulating switches that generate a series of "digital" signals. These multiple loads are grouped together and each group is controlled by a receiver given a digital "address" code.

The transmitting device repeatedly issues a " page " that is configured as a series of digital words containing the " address "

The problem around automobiles has been known for some time that it is very difficult to operate complex electrical circuits due to the presence of electrical noise. To reduce the effects of this noise, the previously proposed "multiplex" electrical system is included in the receiver accumulator to accumulate the command words that apply to the receiver in the previous two pages and the latest information of the instructions This only occurs if there is a new command word that appears identical on the page.

Clearly, such devices have the effect of unnecessarily increasing the response time of the system.

One object of the present invention is to provide a digital " multiplex " vehicle electrical system so that high stability can be obtained against noise interference without the need for excessively long response times.

According to the present invention, there is a vehicle electric system including a transmission device that is sensitive to the state of a plurality of control switches, each generating a series of digital words including an "address" code and a command code. There is a receiver device, each of which controls several loads, each receiver has an "address" code identification means and also acts to control the associated load according to the command code contained in the same word as the "address" code, and has a transmitter Each word of the sequence includes a repetition of one code and an inverse of another code, in addition to the "address" code and the command code, and each receiver includes checking means for checking whether each code matches for repetition or inverse code. Doing.

Each word generated by the transmitter preferentially includes an "address" code, a repetition of an "address" code, a command code and an inverse code of the command code. In this case each receiver comprises means for preventing the command code and its reverse code from being received unless a valid "address" code has been received twice. This method provides a high degree of immunity to noise because each receiver receives command data when the "address" data has already been examined, and there is generally no confusion between the "address" code and the command code. to be.

First, in FIG. 1, there is a system with a transmitter 10 having an input regulated by several switches operated by a driver from a switch (S ₁ ) to a switch (S ₈ ). For example, each vehicle controls a number of vehicle functions, such as the main headlight, low headlight, left and right indicators, fog lights, and reversing lights.

Instead of connecting directly to the switch using a live conductor with a separate back, a single conductor 12 connected to all loads regulated by receivers 13, 14, 15, etc., located at various locations around the vehicle, And each switch adjusts the load of the relevant class. In this way, for example, there are four receivers at four corners of the car, each with its back adjusted at its associated corner. When necessary, there may be a switch (S _n ) to adjust the load other than the back.

The transmitter 10 is connected to the receiver by only a pair of conductors 16 and 17 which will later be called DATA BUS and CLOCK LINE, respectively.

It is shown in FIG. 2 that the transmitter 10 includes a circuit 20 of "microprocessors", with no connection and programming therein, but with the description of the output signals obtained below. Will be understood by man.

Each switch from switches S ₁ to S ₈ adjusts the connection on the input side of the circuit 20 towards the supply “rail” maintained at a regulated voltage (lower than the battery voltage). The circuit 20 is also connected to the common point of the two resistors 22 and 23 connected in series between the DATA BUS 16 and the vehicle ground.

The circuit 20 has its two output side parts connected to act on a circuit for transmitting a pulse code modulation signal to the DATA BUS 16 and the CLOCK LINE 17. The working circuit of the DATA BUS 16 includes an input transistor 24 whose emitter is grounded and its base is connected to the appropriate output side in parallel by a resistor 25 and a capacitor 26. . The collector of the transistor 24 is connected to the base of the pnp output transistor 28 by a resistor 27 and its emitter is connected to the "rail" 21. The resistor 29 is connected to bias between the base emitter of the transistor 28 and the capacitance 30 is connected to the DATA BUS 16 between the base and the "collector" of the transistor 28. It is connected to limit the rate of change of the signal at the connected "collector". The resistor 31 is connected between the bus line 16 and the ground portion to provide a suitable load on the transistor 28 and to determine the time constant of the capacitor 30.

The operating circuit for the clock line 17 is the same.

The output side of the circuit 20 is connected to the back arrangement portion 32 to indicate which of the switches from (S ₁ ) to (S ₈ ) is closed and also to the display panel 33 to indicate a defective lamp or the like. The back arrangement 32 is only intended to remind the driver what load is being loaded.

A system fault detector is included in the transmitter to be used to delay the onset of the transmitter's action with the switch on and also to ensure that the transmitted data sequence starts correctly.

The fault detector includes a dual monostable circuit 35, one of which has an input 2B connected to the output of the circuit 20 and the output Q ₂ is a "decade counter". 36 is connected to one of the "reset" terminals. "Counter" 36 has a QD output connected to one of its input terminals A _IN and the other terminal B _IN is an "asttable mutli-vibrator" based on the well-known 555-type integrated circuit 37. Is connected to the output of the circuit. The Q _A and Q _D outputs of the "counter" 36 are connected to the inputs of the "NAND gate" 38 and their outputs are connected to the 1 _B input of the dual "monos table" circuit 35. It is. The Q ₁ output of the dual “monos table” circuit is connected to the “reset” terminal of the microprocessor circuit 20 via the “inverter” circuit 39.

The counter 36 acts as a 10-division counter, and if the Q _A and Q _D outputs of the counter 36 simultaneously produce an output of 1, the dual "monos table" causes the microprocessor to return to its position via the "inverter". Give the circuit a "falling edge" input. This is typically avoided by giving an output pulse once per "page" from the microprocessor circuit 20, where one of the "monos table" circuits of circuit 35 is reset to 1 "microsecond". Generate a pulse to prevent " reset " the counter 36 once per page and prevent counting to nine. During startup, the microprocessor circuit is "reset" when the counter 36 receives 10 pulses from an unstable "multivibrator" and then a normal cycle begins.

Each of the receivers is given an "address" code, which in the present example is a 5-bit digital code. This allows up to 2 ⁵ -1 receivers (ie 31) to be applied. In the present example, each receiver handles five separate loads, so a 5-bit command code is needed to adjust each load. In addition, each receiver generates a 5-bit return code, indicating the current state of the five codes (open and closed).

The transmitter needs to generate a series of pulse coded words containing an instruction code of "address" code. The transmitter also needs to generate a CLOCK signal on the CLOCK LINE 17 synchronized with the bit of each coded word.

FIG. 2A shows the CLOCK LINE signal and the signal on the DATA BUS 16 in the effect of one cycle of the transmitter and one of the switches S ₁ to S ₈ varying with respect to the signal on the DATA BUS 16.

The upper waveform in FIG. 2A shows the CLOCK signal transmitted during one word when transmitted to DATA BUS 16. As shown, the signal on the clock line 17 is low before the word begins, and the signal on the clock line immediately before the word transmission begins is high for three clock periods, and then alternately low and high for the clock time. Continue until (50) times higher. The CLOCK LINE signal stays low for a while after that until the transmission of the next word begins.

The second waveform shown in FIG. 2A represents an encoded signal associated with 10001, which is a receiver code. As will be known later, the first one in the "address" sign begins as the triple length CLOCK pulse ends and continues for two CLOCK periods. When the data bus signal becomes high again for two clock periods, there is a gap of 14 clock periods. The data has a signal and is lowered again for two CLOCK periods and the "address" code is transmitted again. The command code is in this case a transmission representing the command code 10000 as only a single pulse. After that, the opposite of the command code, that is, 01111 is transmitted. Finally, the reply code 10000 is generated by the receiver and indicates that the load regulated by that receiver is adequately loaded.

The last waveform shown in FIG. 2A includes the same "address" code and "address" repeat code, but the command code is 11000 and the inverse command code is 00111. The reply code is 11000.

In this case, for example, when the "address" symbol 10001 points to the receiver in the front left corner of the car, the five loads adjusted by this receiver are left left headlight filament and left downlight filament, left light It becomes a front indicator light and a fog light. During the generation of the intermediate waveform of FIG. 2 only the "side light" switch S ₁ is closed, but at low waveforms a change occurs because the switch S ₂ of the main light "headlight" is closed. In the first case, the corresponding signal goes to the receiver in all four corners of the vehicle, while in the second case the additional signal goes only to the front corner receiver.

The receiver shown in FIG. 3 includes an input movement " resister " 50 whose load is regulated by an adjustment logic circuit 51 which receives an input signal from the CLOCK LINE 17.

The receiver includes a second " register " 52 and a third " registerer " 53 which actually give an output signal to actuate the circuit 54 to adjust its load. Each "Register" 50, 52, 53 is a 5-bit "Register", and the receiver works broadly as follows.

First, when a triple length CLOCK signal is received by the logic circuit 51, the first five bits of the word are clocked into the "register" 50. This 5-bit is moved into the "Register" 52 by the action of the circuit 51 and the next 5-bit word enters the "Register" 50.

After operating the second 5 bits of word, the confirmation logic 56 checks whether the "Register" 50 and 52 is the same as the receiver "address" code. If not, the receiver is closed. If so, the next 5 bits of the word are clocked into "Register" 50 and also moved to "Register" 52 and the fourth 5 bits is clocked into "Register" 50. The confirmation logic 56 checks whether the two command codes are opposite to each other or closes the receiver. If the two command codes are opposite, the contents of the "Register" 52 are moved to the "Register" 53 to cause the necessary change of the load state.

At this stage, the signals on the five output terminals from the operating circuit 54 representing the actual state of the load are moved into the "register" 50 and also controlled by the logic circuit 51. In the case of gate 57, it clocks with respect to DATA BUS 16.

3 also shows a trouble-free circuit 58 adjusted by the confirmation circuit 56. If circuit 56 fails to generate a command confirmation signal within a predetermined time interval (greater than two complete cycles of the transmitter), circuit 58 outputs the operating circuit to operate in the selected " safe " state. Generates.

)와 (

)로 구성되어 있으며 세단계의 회로(50b)는 사용되지 않고 있다. (

) 및 (

)의 각 회로의 CLOCK 단자는 단자A(제5도)에 연결되어 있고 또한 각각의 병열/직열 단자는 입력이 B단자(제5도)에 연결된 "인버터"(inverter)의 출력에 연결되어 있다. 회로(

)의 J와 K와 입력단자는 저항(61)을 경유 DATA BUS(16)에 연결되며 "클리핑 다이오드"(Clipping diodes)는 회로(

)에 대한 손해를 막기 위해 연결된다. 회로(

)의 J 및 K 입력단자는 회로(

)의 Q₃출력에 연결된다. 회로(

) 및 (

)의 "리세트" 단자는 C단자(제5도)에 연결된다.As shown in FIG. 4, the register 50 includes two MC 14035 moving register circuits connected in a “cascade”.

)Wow (

The circuit 50b of three steps is not used. (

) And (

CLOCK terminal of each circuit is connected to terminal A (figure 5) and each parallel / serial terminal is connected to the output of "inverter" whose input is connected to terminal B (figure 5). . Circuit(

) J and K and input terminals are connected to the DATA BUS 16 via a resistor 61, and the "Clipping diodes" are connected to the circuit (

Connected to prevent damages). Circuit(

J and K input terminals are

Is connected to the Q ₃ output. Circuit(

) And (

Is reset to the C terminal (Fig. 5).

) 및 (

)로 표시된 두개의 4빗트 "래치"(latch) 회로형 (MC14042)로 구성되어 있다. 회로 (

)의 D₀, D₁, D₂및 D₃DATA 입력 단자는 회로 (

)의 Q₀, Q₁, Q₂및 Q₃출력 중 하나에 해당되는 것에 연결되어 있고 또한 회로 (

)의 D₀입력은 회로 (

)의 Q₀출력에 연결되어 있다. 회로(

) 및 (

)의 클럭입력은 하나의 입력이 "난드"(NAND) "게이트"(63)의 출력에 연결되고 다른 입력이 D단자(제6도)에 연결되어 있는 "노아"(NOR) "게이트"(62)의 출력에 연결되어 있다. "게이트"(63)은 C단자로부터 출력이 있으며 또한 두개의 단자 E 및 F(제5도)로 부터 입력이 있다."Resta Star" is 52 (

) And (

It consists of two 4-bit "latch" circuit types (MC14042), denoted by. Circuit (

D ₀ , D ₁ , D ₂ and D ₃ DATA input terminals are

Connected to one of the Q ₀ , Q ₁ , Q _2, and Q ₃ outputs of

D ₀ input of the circuit (

Connected to the Q ₀ output. Circuit(

) And (

Clock input is connected to the output of "NAND" gate (63) and the other input is connected to the "NOR" (gate) (gate) ( It is connected to the output of 62). Gate 63 has an output from terminal C and also inputs from two terminals E and F (fig. 5).

) 및 (

)로 구성되어 있다. 회로(

)의 D₀에서 D₃까지의 데이타 입력은 회로(

)의 Q₀에서 Q₃출력에 연결되어 있으며 또한 회로(

)의 입력은 회로(

)의 Q₀출력에 연결되어 있다. 회로(

) 및 (

)의 클럭 입력은 "난드 게이트"(NAND gate)(63)으로부터 하나의 입력을 가지며, "난드 게이트"(65)로 부터 하나의 입력을 가지며 또한 G단자 제6도로부터 하나의 입력을 가지며 "노어 게이트"(64)의 출력에 연결되어 있다."Register" 53 also includes two "latch" circuits (MC14042)

) And (

It consists of). Circuit(

The data inputs from D ₀ to D ₃ of the

Is connected to the Q ₀ to Q ₃ output of the

) Input is a circuit (

Connected to the Q ₀ output. Circuit(

) And (

Clock input has one input from " NAND gate " 63, has one input from " NAND gate " 65, and has one input from G terminal 6, " Is connected to the output of the NOR gate " 64.

) 및 (

)의 적합한 한개의 Q 출력단자에 각각 하나의 단자가 연결되어 있는 (5)개의 익스클루시브 "오어 게이트"(EXCLUSIVE OR gates)(66), (67), (68), (69) 및 (70)을 포함한다. (66)에서 (70)까지의 각 "게이트"의 다른 단자는 의문시되는 수신기의 "어드레스" 부호를 정의 하도록 "써플라이 레일"(supply rail) 또는 접지에 연결되어 있다. 이들 다른 단자들은 제4도에서 열려진 채로 있다. "게이트"(66)에서 (70)까지의 출력은 그 출력이 "난드 게이트"(72)의 하나의 입력에 연결되고, 또 그 출력이 단자 H(제6도)에 연결되어 있는 "노어 게이트"(71)의 입력에 연결되어 있다."Address" recognition logic

) And (

(5) exclusive "or gates" 66, 67, 68, 69 and 69 with one terminal connected to one suitable Q output terminal of 70). The other terminal of each "gate" from (66) to (70) is connected to a "supply rail" or ground to define the "address" sign of the receiver in question. These other terminals remain open in FIG. Outputs from "gates" 66 to 70 are "nor gates" whose outputs are connected to one input of "nand gates" 72 and whose outputs are connected to terminal H (FIG. 6). Is connected to the input of 71.

) 및 (

)의 Q출력의 해당된 하나에 연결되고 다른 입력은 회로(

) 및 (

)의 Q출력의 해당된 하나에 연결되어 있다. "게이트"(73)에서 (77)까지의 출력은 또 다른 하나의 "노어 게이트"(78)의 입력에 연결되어 있으며 그 출력은 "난드 게이트"(72)의 다른 입력에 연결되어 있다.Confirmation logic 56 includes five proprietary "OR gates" (73), (74), (75), (76), and (77), each of which has one input connected to a circuit (

) And (

Is connected to the corresponding one of the Q outputs of

) And (

Is connected to the corresponding one of the Q outputs. The outputs from "gates" 73 to 77 are connected to the input of another "north gate" 78 and the output is connected to the other input of the "nan gate" 72.

NAND gate 65 is connected at its input to an output from " gate " 73 to 77.

) 및 (

)가 수신기 "어드레스" 부호와 맞는다면 "게이트"(66)에서 (70)까지의 전부호로부터 낮은 출력이 있게될 것이며 따라서 "노아 게이트"(NOR gate)(71)의 출력은 높아질 것이다. "어드레스"의 어느 빗트라도 회로(

) 또는 (

)의 해당 Q 출력과 다르면 그 "게이트"의 출력은 높아져서 "게이트"(71)의 출력이 낮아져 "게이트"(72)의 출력이 높아지게 한다. 이 후자의 상태는 만일 회로(

) 및 (

)의 어떠한 Q출력이 회로 (

), (

)의 해당 Q 출력과 다르면 유효하다. 게이트(65)의 출력은 회로(

), (

)의 Q 출력이 회로(

), (

)의 Q 출력의 역(반대)일때에만 낮다. 게이트(63)의 출력단자는 J 단자(제6도)에 연결되고 또한 회로(

)의 Q₀출력은 K단자(제6도)에 연결된다.It can be seen that "gates" 66 to 70 and 73 to 77 produce a low output when the inputs are the same for that input terminal. This way if the circuit (

) And (

If there is a match with the receiver "address" sign, there will be a low output from the "gate" 66 to 70 sign and thus the output of the "NOR gate" 71 will be high. Any bite in the "address" circuit (

) or (

Is different from the corresponding Q output of < RTI ID = 0.0 >),< / RTI > the output of " gate " 71 is lowered, causing the output of " gate " This latter state is called if the circuit (

) And (

Q output of any circuit

), (

Valid if the Q output is different from The output of the gate 65 is a circuit (

), (

Q output of the circuit (

), (

Low only when the inverse of the Q output The output terminal of the gate 63 is connected to the J terminal (Fig. 6) and the circuit (

Q ₀ output is connected to the K terminal (Fig. 6).

A trouble-free circuit includes an "inverter" whose input is connected to the "gate" 64 by a capacitor 81 and to the Vdd line of the receiver by a resistor 82 (its power supply stabilizer Each receiver included is not shown). The output of the "inverter" 80 is connected to the anode of the diode 83 which is connected to the input of another "inverter" 84. The input of this "inverter" 84 is grounded in parallel by a resistor 85 and a capacitor 86. Finally, the third " inverter " 87 has its history connected to the output of " inverter " 84 and its output is connected to a fault-free terminal (Figure 7).

) 및 (

)의 해당 Q 출력으로부터 회로(

), (

)가 새롭게 되게하는 것이 이 변화인 것이다. 이 변화는 또한 "인버타"(80)의 입력이 낮아지게 하여, 용량(86)이 다이오드(83)을 경유 작용되고, 따라서 고장없는 단자에서의 신호를 높게 유지해 준다. 용량(86)은 저항을 경유 방출하고 또한 정기적으로 재작용되지 않으면 그 전압이 낮게 떨어져 상기의 고장없는 출력은 낮아지게 되는데 다음에 그 효과가 설명될 것이다.The output of the gate 64 changes from low to high only when the output of the gate 65 is low, while the output of the gate 63 is low and the signal at the G terminal is also low and this change indicates the confirmation of the command code. Circuit(

) And (

Circuit from the corresponding Q output of

), (

It is this change that makes) new. This change also causes the input of the "inverter" 80 to be lowered, so that the capacitance 86 is acted upon via the diode 83, thus keeping the signal at the fault-free terminal high. The capacity 86 releases via a resistor and also if it is not periodically reacted, its voltage drops so that the trouble-free output is lowered, the effect of which will be explained next.

5 shows a part of the control logic 51, and also includes a part of the control logic for recognizing the triple length CLOCK pulses generated at the start of each word. For this purpose a local oscillator 90 consisting of two "nor gates" 91 and 92 and also a "feed back" circuit consisting of a resistor 93 and a capacitor 94 are provided. have. The resistor 93 is connected between the gate 91 of the input and output, the output of the gate 91 is connected to the input of the gate 92, and the capacitor 94 is the output of the gate 92 and the gate 91 Is connected between the inputs. The output of gate 92 acts on the clock terminals of two moving "registers" 95, 96 that together form an integrated circuit of the form (MC 14015). The DATA input of the "Register" 95 and the "Reset" input of the "Register" 96 are connected to the CLOCK LINE 17 via a resistor 97 and again "clipped" for protection of the integrated circuit. (Clipping) diode is provided. The two "inverters" 98 and 99 also connect clock line 17 to the "Reset" input of "Register" 95 and the DATA input of "Register" 96 respectively. , The output of "inverter" 99 is connected to the E terminal.

The Q ₃ outputs of the "Register" 95 and 96 are connected to the "SET" and "Reset" terminals of the D-type "flip-flop" circuit 100, respectively. And the CLOCK input are both grounded.

The Q output of the "flip-flop" circuit 100 is connected to one input of the "nan gate" 101, the other input of which is connected to the L terminal (FIG. 6). The Q ₃ output of "Register" 96 is also connected to the M terminal (Figure 6). The output terminal of " nan gate " 101 is connected to terminal C and also provides a " reset " signal to the receiver logic.

The "shift registers" 95 and 96 are clocked by the local oscillator 90. "Data" (data) CLOCK LINE signal between words is high is "Data" input of the low contrast, "Reg Star" (15), and the Q ₃ output of the "register star" is high "flip-flop" (100 ) While maintaining its "reset" state, i.e., lowering the Q output. If the signal at the L terminal is also low, the output of gate 101 is high. If a triple length pulse appears at CLOCK LINE 17 at the beginning of the word "data", "register" 96 is " But this high signal is clocked through the "Register" 95 and sets the "Flip Flop" 101 and lowers the output of the "Gate" 101. The frequency of the oscillator 90 Sufficiently, a high clock line is given enough to clock before the first "data" pulse begins.

The CLOCK LINE signal is also applied to the CLOCK input of the D-type "flip flop" circuit 102, which forms the first control "counter" for the receiver. The "reset" terminal of the circuit 102 is connected to the output of the "gate" 101. The D input terminal of the circuit 102 is connected to the N terminal (Fig. 6). The Q output of the circuit 102 is connected to the A terminal and the Q output is connected to the N terminal. Circuit 102 inputs divided in two, providing "out of phase" pulse "trains" at half of the CLOCK frequency at the A and N terminals whenever the output of "gate" 101 is low. Act as a step.

출력에 연결되고, 그들의 "리세트" 단자는 모두 "게이트"(101)의 출력에 연결되고, 그리고 그들의 세트 단자들은 모두 접지되어 있다. 회로(103)의 J 및 K 입력단자들은 회로(105)의

출력단자에 연결되어 있다. 회로(104)의 J 및 K 입력단자들은 회로(103)의 Q 출력에 연결되어 있다. 회로(105)의 D입력은 회로(103)의

출력으로부터 하나의 입력을 갖고 그리고 회로(104)의 (스캔)출력으로부터 다른 입력을 갖는 "게이트"(106)의 출력에 연결되어 있다.The second stage of the control "counter" consists of a JIK-type "flip-flop" circuit 104 and a D-type "flip-flop" circuit 105 connected to the "nor gate" 106 as a "counter" divided by five. It is a JIK type "flip flop" circuit 103. The CLOCK inputs of circuits 103, 104, and 105 are all

Connected to the output, their "reset" terminals are all connected to the output of "gate" 101, and their set terminals are all grounded. The J and K input terminals of circuit 103 are connected to

It is connected to the output terminal. The J and K input terminals of circuit 104 are connected to the Q output of circuit 103. The D input of the circuit 105 is the

It is connected to the output of the "gate" 106 having one input from the output and the other input from the (scan) output of the circuit 104.

출력은 P단자(제6도)에 연결된다.The Q output of the circuit 105 is connected to terminal F and

The output is connected to the P terminal (Fig. 6).

출력에 연결되어 있고, 그들의 리세트 단자들은 모두 "게이트"(101)의 출력에 연결되어 있고, 그리고 그들의 세트 단자들은 모두 접지 연결되어 있다. 회로(107)의 J 및 K 입력은 Q단자(제6도)에도 또한 연결된 회로(109)의 Q 출력에 연결되어 있다. 회로(108)의 J 및 K 입력은 회로(107)의 Q 출력에 연결되고, 그리고 회로(109)의 D입력은 회로(108)의 Q 출력으로부터 하나의 입력을 가지고 또한 회로(107)의 Q출력으로부터 다른 입력을 갖는 "게이트"(110)의 출력으로 연결되어 있다. 회로(107)의 Q 및

출력 그리고 회로(108)의

및

출력 그리고 회로(109)의 Q 출력은 각각 R, S, T, U 및 V 단자(모두 제6도)에 연결되어 있다.The control "counter" also includes two JIK-type "flip-flop" circuits 107, 108 and a D-type "flip-flop" circuit 109 connected to the "nor gate" 110 as a counter divided by five. ). The CLOCK inputs of circuits 107, 108 and 109 are all

Connected to the output, their reset terminals are all connected to the output of " gate " 101, and their set terminals are all connected to ground. The J and K inputs of circuit 107 are connected to the Q output of circuit 109 which is also connected to the Q terminal (FIG. 6). The J and K inputs of circuit 108 are connected to the Q output of circuit 107, and the D input of circuit 109 has one input from the Q output of circuit 108 and also Q of circuit 107. It is connected to the output of "gate" 110 with another input from the output. Q of circuit 107 and

Output and of circuit 108

And

The output and Q output of the circuit 109 are connected to the R, S, T, U and V terminals (all of FIG. 6), respectively.

출력으로 부터 입력들을 가진 것으로서 회로(105)의 Q 출력과 회로(109)의 Q 출력은 그 출력단자가 B단자에 연결되어 있다."Nand gate" 111 is the circuit of the 104

The Q output of the circuit 105 and the Q output of the circuit 109, which have inputs from the output, have their output terminals connected to the B terminals.

Returning to Figure 6, the rest of the control logic is shown here. "Nor gate" 120 has its two input terminals connected to the H and J terminals, respectively, and a third input terminal connected to the output of "Inverter" 121. The output of "gate" 120 is D It is connected to the CLOCK terminal of the type " flip flop " circuit 122, the grounded set input terminal, and the CLOCK terminal of the reset input terminal connected to the M terminal.

The D input of circuit 122 is connected to the output of "Nor Gate" 123 having two inputs from the N and P terminals, respectively, and a third input from the output of "Inverter".

The input to "Inverter" 121 is connected to the output of "Nor Gate" 124 with inputs from the S, T, and V terminals, respectively. "Nor gate" 125 also has inputs from the R, T, and V terminals, respectively. “Nor gate” 126 has inputs from the Q output of circuit 122 and has inputs from “gates” 124 and 125. The output of "gate" 126 is connected to the input of "inverter" 127 whose output is connected to the L terminal.

"Nor gate" 128 has inputs from the R, U and V terminals, respectively, and its output is connected to one input of "Nor gate" 129 and the other input is the output of "gate" 125. Is connected to. The output of the "gate" 129 is connected to the C terminal.

"Nand gate" 130 has inputs from the Q, R, and T terminals, respectively, and its output is connected to the G terminal. &Quot; Nand gate " 131 has inputs from A, K and V terminals, and inputs from Q output of circuit 122, respectively. The output of “gate 131 is connected to the input of“ inverter ”132, the output of which is grounded by capacitor 133 and npn transistor 136 by resistor 134 and capacitor 135. Are connected in parallel to the base of the transistor 136. The "emitter" of the transistor 136 is grounded and the "collector" is a pnp transistor biased by a resistor 139 connected between the base and the "emitter". It is connected to the base of 138 by a resistor 137. The "emitter" of the transistor 138 is connected to the receiver V _dd "rail", and the "collector" is connected to the DATA BUS 17. It is connected.

As described above, at the beginning of the transmission of the word "data" the CLOCK LINE signal is high and this high signal is clocked through the "Register" 95 and the reset signal at the output of the "gate" 101. Remove it.

)의 J 및 K 입력에 나타나고 그리고 이 "데이터"는 "레지스타"(

) 및 (

)의 CLOCK 입력에서 펄스의 높아가는 부분에 의해 "레지스타"(

) 및 (

)로 CLOCK 된다."Data bits" means "register" (

) And the "data" appear in the "Register" (

) And (

By the rising part of the pulse at the CLOCK input of the

) And (

CLOCK with).

) 및 (

)는 "어드레스"부호를 포함한다. 이 부호는 회로(105)의 Q 출력이 높게 될 때 "게이트"(63)에 의해 "게이트"되는 CLOCK 신호의 결과로서 회로(

) 및 (

) 안으로 들어간다.These pulses are derived from the Q output of circuit 002 and their rising portion occurs at the center of each "data bit". If you get five of these rising points,

) And (

) Contains the "address" sign. This sign indicates that the circuit (as a result of the CLOCK signal "gateed" by the "gate" 63 when the Q output of the circuit 105 becomes high (

) And (

) Into.

) 및 () 안으로 CLOCK 되고 그리고 "어드레스" 인식회로가 효력을 발생한다. 이렇게 하여 게이트(72)의 출력은 낮아져서 "레지스타" (

) 및 (

)안의 "어드레스"부호가 회로(

) 및 (

)와 같고 그리고 문제시된 수신기에 대해 preset해 높은 것과 같기만 하다면 회로(122)로 하여금 세트되도록 한다. 만일 이러한 현상이 발생되지 알으면 "게이트"(126)의 출력은 높아져서 "게이트"(101)의 출력으로 하여금 회로를 리세트하고 더 이상의 입력을 방지하게하는 원인이 된다."Data" means "Register" for another five pulses.

) And ( CLOCK IN and the "address" recognition circuit take effect. In this way, the output of the gate 72 is lowered to " register "

) And (

In the "address" symbol in the circuit (

) And (

And preset for the receiver in question so that the circuit 122 is set as long as it is high. If this phenomenon is known to occur, the output of the "gate" 126 will be high causing the output of the "gate" 101 to reset the circuit and prevent further input.

) 및 (

)에 대한 "데이터" 입력은 계속되어 명령부호가 이러한 "레지스타"에 CLOCK 된다. 또 다시 이 기간의 끝에서, 회로(

) 및 (

)는 "레지스타"(

) 및 (

)로 부터의 데이터로 부하되고 그리고 반대의 명령부호의 "클록킹 인"(CLOCKING IN)이 진행된다. 이 기간중 끝에서 "게이트"(73)에서 (77)까지는 두개의 부호들을 비교하고 그리고 "게이트"(65) 출력은 만일 그 두개의 부호가 반대이면 낮아진다. 이 신호는 "게이트"(63)에서의 신호와 그리고 "게이트"에서의 신호와 함께 "게이트"되어 회로(130) 및 (

)의 내용을 회로(

) 및 (

)에로 부하시키는 CLOCK 신호를 발생시킨다. 상기에 설명한 바와같이 많은 송신싸이클 용량(86)의 "디스차지"(DISCHARGES)에 대해 아무런 펄스도 나타나지 않으면 "인버타"(87)의 출력은 낮아진다. 이 단계에서 "게이트"(111)의 출력은 잠시 낮아져서 그 부하 "데이타"는 "레지스타" (

) 및 (

) 안으로 걸린다. 이러한 "레지스타"들의 "클록킹"은 계속하여 부하 "데이터"의 각각의 "빗트"는 K단자에서 직열로 출력을 내고 그리고 "게이트"(131)을 경유 DATA BUS 상으로 "게이트"된다."Register" (

) And (

The "data" entry for) continues and the command code is locked to this "register". Again at the end of this period, the circuit (

) And (

) Means "Register" (

) And (

Is loaded with the data from the C and CLOCKING IN of the opposite command code. At the end of this period, "gates" 73 to 77 compare two signs and the "gate" 65 output goes down if the two signs are opposite. This signal is " gateed " together with the signal at " gate " 63 and the signal at " gate "

) The contents of the circuit (

) And (

Generates a CLOCK signal that loads to). As described above, if no pulses appear for " DISCHARGES " of many transmit cycle capacities 86, then the output of " inverter " At this stage, the output of the "gate" 111 is briefly lowered so that the load "data" is "register" (

) And (

Takes in) "Clocking" of these "Registers" continues each "bit" of the load "data" outputs in series at the K terminal and "gates" onto the DATA BUS via the "gate" 131.

) (

)로회의 Q 출력단자의 해당한 하나에 연결된다.Then one loading circuit is shown in FIG. Input terminal 150 is the (

) (

Connected to the corresponding Q output terminal of the circuit.

The terminal 150 is connected in series with the base of the transistor star by the capacitor 151 and the resistor 152, the "data" is grounded, and the resistor 154 is connected to the base of the transistor star 153 and grounded. It becomes a "bias". The "collector" of the transistor star 153 is connected to the V _dd "rail" by two resistors 155, 156 and the junction of these resistors is connected to the base of the pnp transistor star 157 and that " The emitter is connected to the V _dd "rail".

The "collector" of the transistor star 157 is connected to the anode of the diode 158, the cathode of which is connected to the base of the npn transistor star 160 by a resistor 159 and the npn transistor by a resistor 161. It is connected to the "collector" of the g-star 162. The "emitters" of these two transistors 160, 162 are grounded and the resistor 163 is grounded to the base of the transistor star 162.

Transistor 160 ... "Collectar" is connected to the base of the Transistor star (162).

The "collector" of the transistor star 164 is connected to the base of the npn transistor star 164, and the "emitter" is connected to the base of the npn transistor star 165 to which "Emita" is grounded. The "collectors" of the transistor stars 164 and 165 are connected together, and also the collector winding 166 is connected to the storage battery "rail" 12 via a "free wheel" (free wheel). Diode 167 is connected across this winding. This collector has a normally open contact 168 that connects one end of the series resistor 169 to the "rail" 12. The other end of resistor 169 is grounded by a load. The one end of resistor 169 is connected to the anode of two diodes 170 and 171. The cathode of the diode 170 is grounded in series by two resistors 172 and 173.

The cathode of diode 171 is grounded in series by two resistors 174, 175. pnp transistor star 176 has its base connected to the junction of resistors 176, 173, its " emitter " connected to the other terminal to resistor 169, and its " collector " 177) to the base of the transistor star 162. The pnp transistor star 178 also has its base connected to the junction of resistors 174 and 175, its "emitter" connected to said other terminal of resistor 169, and its "collector" a resistor. 179 is connected to the cathode of diode 158.

The diode 180 connects the "collector" of the transistor star 162 to the input terminal 150.

When the load needs to be switched on, the signal at terminal 150 is high. This phenomenon causes the transistor star 153 to remain on while the capacity 151 is being taken.

During this period, current flowing through resistor 161 causes transistors 164 and 165 to turn on, thus actuating and closing collector winding 166.

The current flowing through the resistor 161 prevents the transistor star 178 from having any effect, and the current passing through the resistor 159 turns on the transistor star 160 and any effect of the transistor star 176. Prevents you from having

At the end of this initial period, the transistor star 178, which is turned on when the load current is normal, turns on the transistor star 164, 165, where the relay is turned on.

Ideally, if there is a fault such as a high current flowing through the load, the transistor star 178 is turned off because the voltage at the "Emita" drops below its "Emita" base connection. As a result, the transistor stars 164 and 165 are turned off and the relay is inoperative.

Ideally low or there is a fault such as no current flowing through the load, the transistor star 176 is turned on (the voltage drop on the resistor 169 is reduced to zero under open circuit conditions). ). This phenomenon causes the transistor star 162 to turn on, where it turns off the transistor stars 164 and 165 and does not actuate the collector.

Transistorstars 164 and 165 are stopped by diode 180 when the signal at terminal 150 is low. The capacitor 151 discharges.

The fault-free terminal (FIG. 4) is connected to the base of the pnp transistor star 190 with the "Emita" connected to the V _dd "rail". The "collector" of the transistor star 190 is connected to ground by two resistors 191 and 192, and the connection of these resistors is connected to the base of the npn transistor with "emitter" grounded.

The "collector" of the transistor star 993 is based on whether the base of the transistor star 164 or the "collector" of the transistor star 165 needs to be turned on or turned on by the diode 194. .

Claims (1)

As described above and shown in the drawings, a transmitter device sensitive to a state in a plurality of control switches and a plurality of loads each disposed around a vehicle to generate a sequence of digital words each including an "address" code and a command code. A plurality of receivers controlling each of the plurality of receivers, each receiver including a " address " code recognition means and operative to control the associated load in accordance with an instruction code contained in a word as in the " address " code, wherein each word of the digital sequence is Each including a transmitter comprising a repetition of one code and an opposite of the other code, in addition to the "address" code and the command code, and code checking means for checking whether each code coincides with the repetition or opposition. Automotive electrical system comprising a receiver.

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