KR830000284B1 - Electronic Digital Channel Selector - Google Patents

Abstract

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Description

Electronic Digital Channel Selector

1 is a block diagram of the present invention, i.e., an electronic digital channel selector.

2 is a detailed block diagram of the tuning pulse generator and the pulse generator circuit in FIG.

3 is a layout view of the AFT detector circuit in FIG.

4a to 4c are diagrams used to explain the operation of the AFT detector circuit of FIG.

5 is a layout view of the matrix control circuit in FIG.

6 is a layout view of the matrix circuit in FIG.

7 is a waveform diagram for explaining the matrix circuit operation of FIG.

8 is a layout view of a clock-clock converter according to a first embodiment of the present invention.

FIG. 9 shows the control operation by the influence of the clock-clock converter of FIG.

10 is a waveform diagram for explaining the operation of the clock-clock converter of FIG.

11 is a layout diagram of a clock-clock converter according to a second embodiment of the present invention.

FIG. 12 is a diagram illustrating the control operation under the influence of the clock-clock converter of FIG.

13 is a waveform diagram for explaining the operation of the clock converter of FIG.

The present invention relates to an electronic digital channel selector that can be used in television receivers or similar devices. Some television receivers on the market today use tuners with varactor action as voltage regulating capacitors.

In such a varactor type tuner, a tuning voltage of a predetermined magnitude is applied to the varactor according to the channel selection in order to allow the tuner to be tuned to the image carrier frequency of the selected television channel. In such a varactor-type tuner, since there is a natural variation of tuning elements in general, manual fine tuning or automatic fine tuning is required for accurate tuning between the image carrier frequency and the tuner of the selected channel.

Recent advances in integrated circuit technology continue to develop electronic digital tuners that do not require potentiometers. In an electronic digital tuner, the digital data of a particular television channel is converted into an analog tuned voltage by a digital-to-analog converter. This analog tuning voltage is applied to voltage-regulated tuning elements such as varactors to select the required channel. Such digital tuners also require AFT (automatic fine tuning) control by digital method.

In digital AFT control, the AFT clock pulses are counted by the AFT counter to precisely convert the magnitude of the tuning voltage supplied from the digital-analog converter to the voltage control tuner. The AFT discriminator checks whether the output carrier frequency from the tuner matches the preset intermediate carrier frequency. If the output carrier frequency matches the preset intermediate carrier frequency, the counting of the AFT counter stops for correct tuning between the tuner and the selected television channel.

The fundamental problem of AFT control mentioned above is that the response speed of the digital-to-analog converter of the discrimination circuit is slow. The rate of change of the tuning voltage depends on the AFT clock frequency, which is determined by the AFT frequency discriminator. The time when the detection signal is detected by the match between the intermediate carrier frequencies and the detection signal falls behind the time when the output carrier frequency of the tuner actually matches the predetermined intermediate carrier frequency. Therefore, when the AFT frequency discriminator detects the above-mentioned coincidence, the tuner's output carrier frequency will change due to the ever-changing tuning voltage, requiring further modification of the local oscillator.

As a result, the up and down oscillation of the tuning voltage occurs. Although this difficulty can be solved by lowering the frequency of the clock pulses applied to the AFT counter, it still requires a relatively long time for the tuner to tune to the video carrier frequency of the selected television channel.

Accordingly, an object of the present invention is to use a method of gradually lowering the frequency of the clock pulses applied to the AFT counter during the AFT operation so that the tuner can tune to the desired carrier frequency in a shorter time than when using a low frequency clock pulse. To make an electronic digital chanel selector.

According to the present invention, the electronic digital channel selector includes the following.

(1) memory; This is to store the digital signals corresponding to each of the various channels. Each digital signal is read in response to the channel's selection.

(2) digital analog transducers; Connected to a memory device, the analog signal voltage is converted to the digital signal output of the memory device.

(3) voltage control tuner devices; Connected to the digital-to-analog converter, the received carrier frequency of the selected channel is changed to a predetermined intermediate carrier frequency. The device responds to tuning voltages of different magnitudes to tune to different carrier frequencies of different channels. It is adjustable by varying the tuning voltage so that it can be precisely tuned to the carrier frequency of the selected channel.

(4) AFT circuit device; Connected to a voltage-controlled tuner device to detect whether the output carrier frequency of the tuner matches a predetermined intermediate carrier frequency.The time at which the AFT circuit device detects whether the tuner's output carrier frequency matches the predetermined intermediate carrier frequency is the tuning voltage. When it changes relatively quickly for this AFT control, it is later than the time when the tuner's output carrier frequency matches the predetermined intermediate carrier frequency.

(5) AFT counter device; It is connected to the digital-to-analog converter to calculate the AFT clock pulse during AFT control. The change in the number counted by the AFT counter during the AFT control causes the analog tuning voltage from the digital-analog converter to be applied to the AFT counter device. The AFT counter device changes according to the frequency of the clock pulses. The AFT counter device changes according to the frequency of the clock pulses applied to the AFT counter device. The AFT counter device allows the AFT circuit to be tuned to the output transfer frequency of the tuner. When a match between carrier frequencies is detected, it reacts by the AFT circuitry to stop counting the AFT clock pulses.

(6) AFT clock pulse frequency converter; The frequency of the AFT clock pulses applied to the AFT counter device is gradually lowered according to the intervals of the AFT control.

The clock pulse frequency converter according to the first aspect of the present invention has a frequency divider for generating divided clock pulses having several different frequencies, and the AFT circuit device detects an accurate tuning of the tuner to the received carrier frequency. Each time, a circuit for converting the frequency divided clock pulses supplied to the AFT counter device into another frequency division clock pulse of a lower frequency is also included.

The clock pulse frequency converting device according to the second aspect of the present invention has a frequency divider for dividing the frequency of the clock pulses to produce a plurality of frequency-divided clock pulses of different frequencies. There is a gate circuit for selectively supplying the circuit, and it is composed of a timer device for determining the time when the clock pulse supplied to the AFT counter device is converted into a frequency-divided clock pulse of a lower frequency. The timer device is arranged to operate in response to the start of AFT control and detection of a match between the tuner's output carrier frequency and a predetermined intermediate carrier frequency by the AFT circuit.

The digital-to-analog converter comprises a circuit portion for generating a series of pulses whose width is determined by the digital signal output of the memory device, a circuit portion for producing a low pass connected thereto, and a low pass filter connected thereto.

The invention will be more clearly understood by the accompanying circuit diagram and waveform diagram. Next, a description will be given of the electronic digital channel selector of the present invention with reference to FIG. This channel selector includes a digital memory circuit 11 having a capacity for storing a plurality of televisions, each of which represents digital channels. When one of the channel selectors is pressed in the channel selector circuit 12, it is passed to the serial digital information storage control circuit 13 indicating the pressed key, which sends a parallel address signal to the memory circuit 11 corresponding to the selected channel. Have them specify the memory location. In the read mode or the television reception mode, the digital information of the television channel is read out to the memory circuit 11 by selection of the television channel and applied to the tuning pulse generator 14. This tuning pulse generator 14 produces a series of pulses that are either a function of digital information under the control of a clock pulse CKI that has a predetermined period and duration, or has a relatively high frequency from clock pulse generator 15. These pulses have a duty factor. The tuning pulses are applied to the lowpass filter 17 through matrix circuit 16 (which acts as an amplifier until AFT control begins). The lowpass filter 17 produces an analog tuning voltage VT with a magnitude proportional to the duration of the tuning pulse bacteria. The analog tuning voltage VT is applied to voltage controlled tuning elements such as a voltage variable varactor in tuner 18's high frequency amplifier, local oscillation and mixing circuits. The tuner is tuned to the high frequency carrier frequency of the selected television channel. One indication here is that the band select voltage for selecting the low or high bands of the VHF and UHF channels is applied to the tuning circuit of the tuner 18 to switch the inductance of the tuning circuit. The tuner 18 converts the incoming high frequency image carrier number into an intermediate frequency. This intermediate frequency video signal is amplified by the intermediate frequency amplifier 19 and sent to an image detector.

Several tens of ms must pass after the channel is selected until the output voltage of the low pass filter 17 has a magnitude corresponding to the digital information from the memory circuit 11. The output of the intermediate frequency amplifier 19 is connected to the AFT frequency discriminator 20. The frequency discriminator has an S-shaped frequency-voltage characteristic centered on a predetermined intermediate frequency of 45.75 MHz. The AFT detector 21 is connected to the AFT frequency discriminator 20, and outputs an output signal X, Y or Z, respectively, depending on whether the image carrier frequency from the tuner 18 is lower than the predetermined intermediate frequency but higher or matched. Lose.

The AFT pulse generator 22 is for producing an AFT pulse group having the same period as the tuning pulse group under the control of the clock pulse CK ₂ . The AFT pulse group is sent to the matrix circuit 16. The pulse width of the AFT pulse group changes depending on the output state of the AFT detector 21. The matrix circuit 16 combines the tuning pulse group and the AFT pulse group.

The coupling mode (sum or difference) is determined by the matrix control circuit 23, which is a circuit that reacts by the outputs X and Y of the AFT detector 21. During the AFT control, the output voltage of the low pass filter 17 gradually increases or causes the tuner 18 to tune to the incoming high frequency carrier frequency.

When the tuner 18 accurately tunes to the high frequency carrier, the intermediate carrier frequency of the tuner 18 has a predetermined value and causes the AFT detector 21 to transmit Z, which is an accurate tune detection signal.

(The Z signal is generated whenever the output carrier frequency and the predetermined intermediate carrier frequency match.) As a result, the width and coupling mode (sum or difference) of the AFT pulse group are determined and fixed, and the low pass filter is fixed. The tuning voltage with magnitude continues to be output.

During the AFT control, the output voltage of the low pass filter changes at a rate proportional to the frequency of the AFT clock pulses supplied to the AFT pulse generator 22. The AFT frequency discriminator 20 has an operation delay time of about 10 ms necessary to remove the noise signal from the AFT signal.

The low pass filter 17 also has an operating area time of about 30 to 40 ms. Therefore, when the frequency of the AFT clock pulse is relatively low, that is, when the output voltage of the low pass filter 17 is relatively high, that is, when the output voltage of the low pass filter 17 is relatively changed, the AFT detector 21 ) Outputs the output signal Z later than the time when the output carrier frequency of the tuner 18 is at a predetermined intermediate frequency. As a result, frequency readjustment is required.

If the low frequency AFT clock pulses are used in consideration of the delay operation of the AFT frequency discriminator 20 and the low pass filter 17, it will take a long time to control the AFT. The present invention-electronic digital channel selector comprises a clock converter 24, which gradually reduces the frequency of the AFT clock pulses applied to each control interval AFT multipulse generator 22.

The pulse generator 22 and the clock converter 24 are connected to the channel selector circuit 12. After the channel is selected, the low pass filter outputs an output tuning voltage corresponding to the digital information signal from the memory circuit. After the passage of time, the pulse generator 22 and the clock converter 24 are designed to return to the state of the initial condition. During the write mode or tuning voltage setting mode (program mode), the digital information of the selected channel is generated by the tuning pulse generator 14 and the storage location corresponding to the channel selected in the memory circuit 11. Will be stored in.

During the write mode, the AFT pulse generator 22 and the clock converter 24 do not operate, and the matrix circuit 16 operates as an amplifier for the tuning pulse.

FIG. 2 shows the arrangement of the tuning pulse generator 14 and the pulse generator 22 in FIG. 1 in more detail. Parts of FIG. 2 that are the same as those of FIG. 1 are numbered the same and description is omitted.

The tuning pulse generator 14 is composed of a counter 31 and 32, a gate 33 and a "34", a shift register 35, a comparator 36, a decoder 37 and a latch circuit 38. The AFT pulse generator 22 includes a counter 41 and 42, a gate 43, a comparator 44, a decoder 45 and 47, and a latch circuit 46.

The counter 31 receives the clock pulse CK ₁ from the clock pulse generator 15, and the counter 32 receives the clock pulse CK ₂ through the gate 33. The gate 33 becomes inoperable by the Z output signal from the AFT detector 21, and becomes inoperable by the non-lock type gate drive switch used for setting the tuning voltage. . For example, the counters 31 and 32 are (12) bit registered counters and are in a reset state when they are connected for the first time. The frequency of the clock pulse CK1 is, for example, about 2,048 MHZ, and the frequency of the clock pulse CK ₂ is the frequency 512 obtained by dividing the frequency by 4096 (= 2 ¹² ). Therefore, whenever the counter 31 counts the clock pulse CK ₁ at 4096 (4096 is the number that the counter 31 can count to the maximum), one CK ₂ clock pulse is applied to the counter 32. The number counted by the counter 32 is stored in the register 35 through the select gate 34 in the case of the write mode, and the write mode is set by the read / write control switch.

The decoder 37 is composed of a NAND gate and a NOR gate and is for detecting a predetermined count number of the counter 31, for example, an initial count number 0. Each time the decoder 37 detects the initial count number, the output of the latch circuit 38 is set to a high level. The comparator 36 compares the number by the counter 31 with the number counted by the counter 32 stored in the register 35.

When both of these coincide, the comparator 36 resets the latch circuit 38 to bring the output to a low level. When the counter 31 counts the pulses of the clock pulse CK ₁ to the maximum count number, the time when the comparator 36 resets the latch circuit 38 is shifted by one period of the clock pulse CK1. do. As a result, the latch circuit 38 generates a pulse group. The period of the pulses is such that the maximum count time of the counter 31 becomes 1/512 seconds and the widths of the pulses are changed by the period / 4096 every 1/512 seconds. As described above, the pulse width is changed to the pulse group in which the pulse is gradually increased. As described above, for the pulse group in which the pulse width increases step by step, the local pass filter 17 outputs an output moving voltage which increases in a similar step. For example, with respect to the change in the pulse width of one step of the pulse group from the latch circuit 38, the tuning voltage changes by 8 mv. This 8 mv change in tuning voltage causes the frequency of the local oscillator of the tuner 18 to change at a low chanel band time (10 KHZ).

When the tuner 18 is correctly tuned to a particular channel by a change in the tuning voltage, the AFT detector 21 generates a Z signal to render the gate 33 inoperable. As a result, the clock pulse CK2 is not supplied to the counter 32 and the counter 32 stops counting. Accordingly, the width of the pulses from the latch circuit 38 and the output tuning voltage VT of the low pass filter are also fixed by the count number (the number when the count is stopped) fixed to the counter 32.

The fixed count number of the counter 32 is stored through the gate 34 in the storage of the memory circuit 11 by the action of the memory switch mem-chyslw. The setting of the tuning voltage VT for another selected channel is made by making the gate 33 operable by the action of the gate operating switch. The count made by the counter 32 for these other channels is stored in the corresponding storage location of the memory circuit 11. In the read mode, the action of the selection gate 34 is changed to draw the digital information stored in the memory circuit 11 to the register 35.

In the read mode, the pulse widths of the pulses from the latch circuit 38 are fixed and operate only on the digital information of the memory circuit 11. The counter 41 is a (12) bit synchronous type and counts the clock pulse CK ₁ from the clock pulse generator 15 in synchronization with the counter 31. Each time the initial count " 0 " of the counter 41 is detected, the encoder 45 sets the latch circuit 46 to cause a high output.

Clock pulse CK ₂ is sent to clock converter 24 where it is frequency-divided. Frequency-divided clock pulses are reset to an initial count by the reset signal when AFT control is initiated through gate 43 over several intervals of AFT control. The clock converter 24 is also reset to an initial state by the reset signal. The numbers counted by the counters 41 and 42 by the comparator 44 are compared, and when they coincide with each other, the latch circuit 46 is reset so that the output becomes low. The latch circuit 46 produces an AFT pulse group having the same period as the tuning pulse group from the latch circuit 38. The moment at which the AFT pulses are generated coincides with the moment at which the tuning pulses begin to be generated, and the width of the AFT pulses varies depending on the number counted on the AFT counter 42 during the AFT control period.

을 탐지하기 위하여 있다.When the AFT detector 21 outputs an output signal X which means that the output carrier frequency of the tuner 18 is too low, this AFT counter becomes a counter for subtraction, indicating that the output carrier frequency of the tuner 180 is too high. In the case of outputting the meaning of the output signal Y, the addition is performed, and the decoder 47 performs an initial count "0" and a maximum count value of the AFT counter 42.

Is to detect.

The matrix control circuit 23 reacts to the output X, Y of the AFT detector 21 and the output of the decoder 47. If the output X of the AFT detector 21 is high when the AFT control starts, the matrix circuit ( 16) combines the tuning pulses and the AFT pulses in a size ratio, for example, a ratio of 2: 1, using a calculator. Therefore, when the number of the AFT counter 42 changes by "1", the one-step change value of the pulse width of the AFT pulse gives a change of about 4 mV in the tuning voltage VT. This 4 mV change, for example, causes the low chanel to change the local oscillation frequency by approximately 5 KHZ.

As shown in FIG. 3, the AFT detector 21 includes a voltage divider 51, a NAND circuit 52, a NORE circuit 53, inverters 54, 55, 56 and a NOR circuit. It consists of 57. The voltage divider circuit 51 consists of resistors R ₁ -R ₄ of the same value.

The first AFT signal AFT ₁ shown in FIG. 4A is from the AFT frequency discriminator 20 and enters one side of the voltage divider 51, and the second AFT signal AFT is intermediate between R ₂ and R ₃ of the voltage divider 51. Enter the point. The other side of the voltage divider 51 is grounded.

As shown in FIG. 4a, AFT ₁ and AFT ₂ have opposite values for the reference voltage level V ₀ of about 6V. The NAND circuit 52 is composed of N-channel MOS transistors Q ₃ Q ₄ connected in series with P-channel MOS transistors Q ₁ Q ₂ connected in parallel.

The source of Q ₁ Q ₂ is connected to the voltage divider output o1 from the junction of R ₁ and R ₂ . (The voltage here is 6 volts, which is the average of AFT ₁ and AFT _2. ) The second output (02) of the voltage divider (half of the voltage of AFT ₂ ) is connected to the gate of transistor Q ₁ Q ₃ . The first output 10 is connected to the gate of Q ₂ Q ₄ . As seen in the NAND circuit 52, the transistor Q ₂ is normally in a non-conductive state and Q ₄ is in a conducting state.

The NOR circuit 53 is composed of a P-channel mo-transistor QQ ₆ connected in series and an N-channel mo-transistor Q Q ₇ Q ₈ connected in parallel.

The source of Q ₅ is connected to the first output 01 of the voltage divider 51. The gate of Q ₆ Q ₇ is connected to the second output Q ₂ of the voltage divider 51. Q ₅ The gate of Q ₈ is grounded.

As shown in the figure, transistor Q ₅ is in the conducting state in the normal state, and transistor Q ₈ is in the nonconducting state. The NOR circuit 57 consists of a series of connected P-channel mo-transistors Q ₉ Q ₁₀ and an N-channel Chanel transistors Q ₁₁ Q ₁₂ connected in parallel. The gate of transistor Q ₉ Q ₁₂ is connected to the output of the NAND circuit 52 through an inverter 56 composed of a thermo-transistor. The gate of Q ₁₀ Q ₁₁ is connected to the NOR circuit 53 through the Shimo-sverters 45 and 55. The output X of the AFT detector 21 is connected to the output of the inverter 56 and the output Y comes from the output of the inverter 55. Another output Z is connected to the drain of transistor Q _{12 and} the drain of Q ₁₀ Q ₁₁ .

In the operation of the AFT detectors 2 and 21, the transistor Q ₄ of the NAND circuit 52 is conducted in the normal state as mentioned above. Therefore, the voltage between the source and the substrate of transistor Q ₃ is raised by the saturation voltage between the source and the drain of transistor Q ₄ . As a result, Tran register Q ₃ with a threshold (threshold) voltage of the inverter consisting of Q ₁ in the count being increased by that. Therefore, when the voltage at the second output 02 of the voltage divider 51 (half the voltage of the AFT ₂ ) exceeds the voltage V ₁ higher than ½ VO, the output voltage of the NAND circuit 52 falls to various levels. Therefore, when the output response frequency of the tuner 18 is very lower than the preset intermediate carrier frequency (45,75MHZ), as shown in FIG. 4C, the output X goes up to a high level.

On the other hand, in the NOR circuit 53, since the transistor Q ₅ is conducting in a steady state, the threshold voltage of the inverter constituted by the transistors Q ₆ and Q ₇ is increased at a low level. The voltage 1, which switches to the level, falls below 1 / 2V 0. Therefore, as shown in FIG. 4B, the voltage at the second output 02 of the voltage divider 51 falls below the voltage V ₂ at a level lower than 1 / 2VO. As shown in Fig. 4c, the output Y changes from a low level to a high level, which means that the output carrier frequency of the tuner 18 is considerably higher than 45,75 MHz.

When the voltage at the voltage divider 51) 02) has a value between V ₁ and V ₂ , that is, the output carrier frequency of the tuner 18 is equal to 45,75 MHZ within an acceptable range. At that time, the output Z goes up to a high level as shown in FIG. 4C. As an example, the output carrier frequency will be close to 45,75 MHz in the range of ± 20 kHz.

과 AFT검파기(21)의 출력 X에 결합되어 있다.The matrix control circuit 23 can be designed as shown in FIG. The input of the NAND gate 61 is the output of the decoder 47.

And the output X of the AFT detector 21.

과 AFT검파기(21)의 출력 X에 결합되어 있다.In contrast, the NAND gate 23 can be designed as shown in FIG. The input of the NAND gate 61 is the output of the decoder 47.

And the output X of the AFT detector 21.

On the other hand, the input of the NAND gate 62 is coupled to the output Y of the AFT detector 21 and the "0" output of the decoder 47, respectively. The outputs of the NAND gates 61 and 62 are connected to mutually corresponding inputs of the cross-coupled NAND gates 63 and 64. The output of the gate 63 is connected to the inverter 65.

까지 감산 카운트를 하였을 때 NAND게이트(61)의 출력은 낮을 레벨로 되고 NAND게이트(63)의 출력을 높은 레렐로 되게된다. 그 결과로 행렬제어 회로(23)의 합출력은 높은 레벨로 되고 차 출력은 낮은 레벨이 되어 행렬회로(16)으로 하여금 가산기로 동자하게 한다. 따라서 동조전압 VT가 서서히 증가하고 국부발진기의 주파수와 튜너(18)의 출력반송주파수가 증가하게 된다. AFT제어의 시작에서 튜너(18)의 출력반송 주파수가 45,75MHZ보다 아주 높을 때, 다시 말해서 AFT검파기(21)의 출력 Y가 높은 레벨일대 AFT카운터(42)는 언급한 바와같이 가산 카운터로 동작한다. 그 결과로 NAND게이트(62)의 출력은 AFT제어의 시작시 낮은 레벨로되고 이는 NAND게이트(63)의 출력을 낮게한다.When the output carrier frequency of the tuner 18 at the start of the AFT control is much lower than 45,75 MHz, in other words, when the output X of the AFT detector 21 is at a high level, the AFT counter 42 is subtracted as mentioned above. It acts as a counter. Therefore, the counter 42 is at "0"

When the subtraction count is completed, the output of the NAND gate 61 becomes a low level and the output of the NAND gate 63 becomes a high level. As a result, the sum output of the matrix control circuit 23 is at a high level and the difference output is at a low level, causing the matrix circuit 16 to synchronize with the adder. Therefore, the tuning voltage VT gradually increases, and the frequency of the local oscillator and the output carrier frequency of the tuner 18 increase. When the output carrier frequency of the tuner 18 at the start of the AFT control is much higher than 45,75 MHz, that is, the output Y of the AFT detector 21 has a high level, the AFT counter 42 operates as an addition counter as mentioned. do. As a result, the output of the NAND gate 62 goes to a low level at the start of the AFT control, which lowers the output of the NAND gate 63.

As a result, the sum output and the difference output of the matrix control circuit 23 become low level and high level, respectively, so that the matrix circuit 16 operates as a subtractor. Accordingly, the tuning voltage VT gradually decreases, and the output carrier frequency of the tuner 18 gradually decreases.

Next, the arrangement and operation of the matrix circuit 16 of FIG. 6 will be described. The matrix circuit 16 includes NPN switching transistors Q ₁₅ and Q ₁₆ . Q ₁₅ has the emitter thereof is grounded and the collector is connected to the low-pass filter 17 which has received the power supply of 32V via the resistor R _6. Q ₁₆ is the emitter and the collector is grounded through a resistor R ₇ is connected to the collector of Q _15. R ₆ and R ₇ have the same resistance. Input signal to the base of the result Q ₁₅ based on the input signal and Q ₁₆ of from 2: is coupled at a ratio of 1: 1.

In the write mode, the R / W control signal has a logic level of "1" and disables the NOR gates 67, 68, and 71. However, the NOR gate 66 can operate because of the inverter 69. Transistor Q ₁₆ remains non-conducting when NOR gate 71 is inoperable.

Therefore, the tuning pulse generator 14 is connected to the base of the transistor Q ₁₅ through the NOR gate 66 and the OR gate 70. Therefore, in the write mode, the matrix circuit 16 only acts as an amplifier for the tuning pulses.

In the read mode the NOR gate 71 is operable but is connected to the base of the transistor Q ₁₅ via the NOR gate 70. Therefore, in the write mode, the matrix circuit 16 only acts as an amplifier for the tuning pulses.

In the read mode, NOR gate 71 is enabled but NOR gate 66 is disabled. In the read mode, after the TV channel is selected or switched, the AFT operation cannot be performed until the tuning voltage VT generated by the tuning pulse group from the tuning pulse generator 14 is stabilized. In the case where the AFT operation fails, the AFT operation suppression signals of logic level " 1 " are applied to the NOR gates 73 and 74 to disable them. As a result, the AFT pulse generator 22 is not coupled to the base of the transistor 16. The AFT operation suppression signal is also transmitted to the AND gate 76 through the inverter 77 to bring the output of the AND gate 76 to a low level. When suppressing the AFT operation, the tuning pulse generator 14 is coupled to the transistor Q ₁₅ through the NOR gate 67 or 68 according to the output state of the matrix control circuit 23. The AFT operation prevention function is released after about 100mS after the channel selection. Accordingly, the AFT counter 42 of the AFT pulse generator 22 is reset to the initial value.

At the start of the AFT control, the logic levels of the sum output and the difference output of the matrix control circuit 23 are determined as mentioned above. Now, suppose the sum output "0" and the difference output is "1". Under this condition, the output Y of the AFT detector 21 is at a high level, so the AFT counter 42 operates as an addition counter. Since the difference output is at a high level, the NOR gates 68 and 73 do not operate.

As a result, the AFT pulse generator 22 is connected to the base of the transistor Q ₁₆ through the inverter 75, the NOR gates 74, 72, and 71 in order. The tuning pulse generator 14 is connected to the base of Q ₁₅ through the NOR gate 67 and the OR gate 70. It should be noted here that the base input waveform of Q ₁₅ has the same polarity as the output waveform from the AFT pulse generator 22. The 7a turns to show the base input waveform of the input waveform, the base of Q _15, Q ₁₅ to turn the 7b.

However, voltage gain of the Q ₁₆ is because it is half of the voltage gain of the Q ₁₅ is the waveform as help 7c will appear on the collectors of Q _15.

Since AFT counter 42 is in the addition count mode, the width of the base input pulse of Q ₁₆ seen in FIG. 7b increases over time, which is the Q ₁₅ collector seen in FIG. 7c. The upper stage of the output pulse is reduced over time, and as a result, the magnitude of the output voltage TV of the low pass filter 17 and the frequency of the local oscillator are reduced.

As can be clearly seen from the output waveform of Fig. 7c, the matrix circuit 16 operates in the subtraction mode under the condition that the output state of the matrix control circuit is ADD = 0 and SUB = 1.

On the contrary, when ADD = 1 and SUB = 0, the output of the AFT detector 21 is at a high level, so the AFT counter 42 operates in the subtraction mode.

Since ADD = 1, the NOR gates 67 and 74 do not operate. FIG. 7D shows the output waveforms of the AFT pulse generator 22 when the AFT counter 42 is in the subtraction mode. The output waveforms of FIG. 7D are shown through the NOR gates 73, 72, and 71. FIG. Tran is connected to the base of Q register _16.

As a result, the base input waveform of Q ₁₆ is the opposite of the polarity and the output waveform of the AFT pulse generator 22, as shown in FIG. The output signal of the NOR gate 73 enters one input of the NOR gate 68 through the AND gate 76.

The other input of the NOR gate 68 is connected to the output of the tuning pulse generator 14.

Thus, a waveform such as the 7F diagram appears at the output of the NOR gate 68 or at the Q ₁₅ base. The period of the low level of FIG. 7f is longer than that of the waveform of FIG. 7a, which appears when only the tuning pulse generator 14 is connected to the base of Q15.

Figure 7e the base input waveform of Q ₁₆ as shown in is shown in the call rekta of the waveform as shown in the Figure 7g Q ₁₅ because the base input waveform of the 7f Q ₁₅ degrees. Since the AFT counter 42 is in the down count mode, the output waveform of Q ₁₅ increases in the width of the low level portion as seen in 7f, and the local oscillator frequency increases accordingly. It is therefore clear that matrix circuit 16 operates in additive mode when ADD = 1 and SUB = 0.

8 to 10 are for explaining the configuration and operation of the clock converter of the present invention. The clock pulse CK ₂ of 512HZ is supplied to the frequency divider 79 which is an unequalized counter. The frequency divider 79 is composed of four binary counters connected in series, F / (256HZ), F2 (128HZ) and F3. (64HZ) and produces a divided clock pulse of F4 (32HZ).

When the AFT suppression is terminated, the channel selection circuit 12 sends the reset pulse or the AFT control start pulse shown in FIG. 10a to the reset terminal of the flip-flop 80 composed of the cross-coupled NAND gates. The inverter 83 is also sent to the reset terminals of the flip flops 81 and 82.

By applying a reset pulse, the output Q of the flip-flops 80, 84, 85 and the output of the NAND gate 95 become high levels, as shown in FIG. As a result, the NAND gates 88, 92, 94 become inoperable and the NAND gates 87, 89, 90, 91, 93 become operable. Since the NAND gate 87 accepts pulses *** as input, the AFT counter 42 receives F1 clock pulses.

If the output carrier frequency of tuner 18 is very low than 45,75 MHz when AFT control is started, AFT counter 42 goes down and matrix circuit 16 is in add mode.

As a result, the tuning voltage VT increases over time at a rate proportional to the frequency of the clock pulse F1, causing the frequency of the local oscillator to increase as shown in FIG. When the local oscillation frequency reaches a frequency f ₀ which is adopted as a level capable of producing an accurate intermediate frequency, the AFT detector 21 produces an output signal Z. If the output carrier frequency of the tuner 18 is very higher than 45.75 MHz, the output signal Y of the AFT detector 21 will be at a high level. Thus, the AFT counter 42 is switched from the down count mode to the up count mode.

The output signal Z enters the flip-flops 80 and 81 through the inverter 86, whereby the output Q of the flip-flop 80 goes to a low level and the outputs of the flip-flops 81 and 82 are output. Q is at a high level. The first addition of the output signal Z renders the NAND gate 87 inoperable, and the NAND gate 88 becomes inoperable.

Since the output states of the flip-flops 84 and 85 are unchanged, the NAND gates 89, 90, 91, and 93 are in an operable state, and the NAND gates 92 and 94 are operable. ) Remains in an inoperable state. Thus, clock pulse F2 is applied to the AFT counter. In this period, the matrix circuit 16 is in the add mode and the AFT counter 42 is in the raise count mode. Therefore, the output waveform of the matrix circuit 16 shown in FIG. 7g reduces the width of the portion of the low level with time, thereby reducing the furnace voltage VT and lowering the local oscillation frequency with time as shown in FIG. You lose. The correction speed of the tuning voltage VT depends on the frequency of clock pulse F2. In this case, since the clock pulse F2 has a relatively high frequency, the AFT detector 21 outputs a signal that serves to drop the output Q of the flip-flop 81 to a low level when the local frequency falls to f ₀ . Generate signal Z. Later, an output signal Z, which is a signal that serves to drop the output Q of the AFT detector 21 to a low level, is produced. Later, the output X of the AFT detector 21 is at a high level, and the AFT counter 42 is switched to the down count mode.

Since the output Q of the flip-flop 81 is at a low level, the output of the NAND gate 95 is at a low level (Fig. 10f), and the output state of the flip-flop 84 is changed. As a result, the NAND gate 89 becomes inoperable, and the NAND gate 94 becomes in an operable state. Since no change occurred in the output state of the flip-flop 85, the NAND gate 91 remains in an operable state, and the NAND gate 92 remains in an inoperable state. Therefore, clock pulse F3 is applied to the AFT counter 42.

During this period, the AFT counter is in the down count mode, so that the width and the tuning voltage VT of the low level portion of the output waveform of the matrix circuit 16 shown in FIG. Since clock pulse F3 still has a high frequency, this causes the output Z of the AFT detector 21 to a high level when the local oscillation frequency is higher than f ₀ .

Therefore, as shown in FIG. 10, the output Q of the flip-flop 81 is at a high level, and the output Q of the flip-flop 82 is at a low level. At this time, the output of the NAND gate 96 is at a low level and the state of the flip-flop 85 changes. As a result, the NAND gate 91 is inoperable and the NAND gate 92 is movable. The clock pulse F4 having the lowest frequency is connected to the AFT counter 42. At the beginning of this time, the output carrier frequency of the tuner 18 is higher than 45.75 MHz, so that the output Y of the AFT detector 21 is at a high level. Therefore, the AFT counter 42 is switched to the raising count mode, so that the low level width of the output waveform of the matrix circuit 16 decreases with time and the tuning voltage VT similarly decreases with time. Since the frequency of clock pulse F4 is sufficiently low, the local oscillation frequency will similarly decrease with time for VT. The frequency of clock pulse F4 decreases with time, and thus the tuning voltage VT similarly decreases with time. Since the frequency of clock pulse F4 is sufficiently low, as soon as the local oscillation frequency reaches f ₀ , the output Z of AFT detector 21 can rise to a high level. As a result, the AFT clock pulses are blocked from being supplied to the AFT counter 42. The AFT control, which then takes place when necessary, is done only by the clock pulse F4 itself.

When the clock converter according to the present invention is used, the frequency of the AFT clock pulses supplied to the AFT counter 42 is gradually lowered for each AFT control period. Therefore, as shown in FIG. 9, the AFA control can be achieved in a shorter time than when only the clock pulse F4 is used.

The following is a description of another clock converter of the present invention corresponds to FIGS. 11 to 13. This second clock converter has a timer circuit that determines the time when the frequency of the clock pulse applied to the AFT 42 should be changed. Therefore, in the presence of this timer circuit, the width of the range where the local oscillation frequency exceeds or falls short of the preset level is narrowed, thereby enabling AFT control in a shorter time than when using the first clock converter according to the present invention.

In FIG. 11, reference numeral 101 denotes a frequency divider for dividing clock pulse CK ₂ into AFT clock pulses F1 (256 Hz), F2 (128 Hz), and F4 (32 Hz). The timer circuit mainly consists of flip-flops 105 and 106. Clock pulse CK ₃ (Fig. 13e) has a frequency of 128 Hz, and the frequency is divided in half by flip and flop 107. The output of this flip-flop 107 is fed to the flip and flop 105 via the NAND gate 111 when it is operable.

는 높은 레벨로 된다. 또 리세트펄스는 제13C도에서 보는 바와 같이NOR게이트(109)에 공급되어 출력을 낮은 레벨로 되게한다.The reset pulse (Fig. 13a), which is the AFT control start pulse, is supplied to the reset terminals of the flip and flops 105, 106, and 108, and the output Q is at a low level (

Becomes a high level. The reset pulse is also supplied to the NOR gate 109 as shown in FIG. 13C to bring the output to a low level.

는 낮은 레벨이 되게한다.As a result, the output Q of the flip-flop 102 makes the NAND gate 111 operable as shown in FIG. 13d. Thus, the flip-flops 105 and 106 count the output pulses of the NAND gate 111. The reset pulse is further transmitted to the flip-flop 103 through the inverter 119 so that the output Q is at a high level.

To make the level low.

가 공급되는 NAND게이트(113)은 동작기능이되고,

클럭이 공급되는 NAND게이트(114)는 동작불능이 되어 출력은 높은 레벨에 놓여 있게 된다. 플립-플롭(103)에 전달되어 출력 Q는 높은 레벨로

는 낮은 레벨이 되게한다.so

Supplied with the NAND gate 113 becomes an operation function,

The clocked NAND gate 114 becomes inoperable and the output is at a high level. Is delivered to flip-flop 103 so that output Q is at a high level.

To make the level low.

가 공급되는 NAND게이트(113)은 동작기능이되고,

클럭이 공급되는 NAND게이트(114)는 동작불능이 되어 출력은 높은 레벨에 놓여 있게된다. 플립-플롭(103)의 낮을 레벨의 출력

때문에 플립-플롭(104)의 출력 Q는 높은 레벨이 되고

는 낮은 레벨이 되어 NAND게이트(116)은 동작불능이 된다. 따라서 NAND게이트(113)으로부터 나온 클럭펄스 F1은 NAND (115, 117)을 통하여 AFT카운터(42)에 가해진다. 결과적으로 국부발진 주파수는 클럭펄스 F1의 주파수에 비례하는 속도로 수정되게 된다.(제12도)so

Supplied with the NAND gate 113 becomes an operation function,

The clocked NAND gate 114 becomes inoperable and the output is at a high level. Low level output of flip-flop 103

So that the output Q of the flip-flop 104 is at a high level

Becomes a low level and the NAND gate 116 becomes inoperable. Therefore, the clock pulse F1 from the NAND gate 113 is applied to the AFT counter 42 through the NANDs 115 and 117. As a result, the local oscillation frequency is corrected at a speed proportional to the frequency of the clock pulse F1 (Fig. 12).

, 플립-플롭(106)의 출력 Q와 플립-플롭(102)의 출력

는 모두 NOR게이트(112)의 입력이 된다. 플립-플롭(102)의

출력은 낮은 상태에 있으므로, NAND게이트 (111)의 출력, 플립-플롭(105)의 출력

그리고 플립-플롭(106)의 출력

가 모두 낮은 상태에 있으면 NOR게이트 (112)의 출력은 제13i도에서 처럼 높은 상태로 된다. NOR게이트(112)의 출력은 NAND게이트(110)의 한쪽 입력에 연결되어 있는데, 다른 한쪽 입력은 인버터(120)을 통하여 클럭펄스 CK₃에 결합되어 있다. 그러므로 NOR게이트(112)의 출력이 높은 상태로 되고, 클럭펄스 CK₃가 낮은 상태가 되면, NAND게이트(110)의 출력은 낮은 레벨이 된다. 이는 플립-플롭(102)의 출력은 낮은 상태가 되어 NAND게이트(11)의 출력으로 하여금 즉시 높은 상태가 되게한다. (제13j도)Output of NAND Gate 111, Output of Flip-Flop 105

, Output Q of flip-flop 106 and output of flip-flop 102

Are all inputs to the NOR gate 112. Flip-flop 102

Since the output is in the low state, the output of the NAND gate 111, the output of the flip-flop 105

And the output of flip-flop 106

If both are in the low state, the output of the NOR gate 112 becomes high as in FIG. 13I. An output of the NOR gate 112 is connected to one input of the NAND gate 110, and the other input is coupled to the clock pulse CK ₃ through the inverter 120. Therefore, when the output of the NOR gate 112 becomes high and the clock pulse CK ₃ becomes low, the output of the NAND gate 110 becomes low. This causes the output of the flip-flop 102 to go low, causing the output of the NAND gate 11 to immediately go high. (Figure 13j)

The change of the output state of the flip-flop 102 mentioned above causes the change of the output state of the flip-flop 103, and the NAND gate 113 becomes inoperable and the NAND gate 114 becomes inoperable. do. Since the change in the output state of the flip-flop 103 does not induce the change in the output state of the flip-flop 104, the NAND gate 115 remains in an operable state.

Accordingly, the clock pulse F2 is supplied to the AFT counter 42 through the NAND gates 115 and 117. Thus, the local oscillation frequency is calibrated at a lower speed than when the clock pulse F1 is supplied. Since the flip-flop 102 remains in the low level state, the timer circuit does not count clock pulse CK ₃ .

는 NOR게이트(112)의 모든 입력들이 낮은 상태일때 높은 상태를 유지하로 AND게이트(118)의 출력은 제13L도와같이 높은 상태가 되서 플립-플롭(108)의 출력

를 낮은 상태로 만든다. 이 변화에 의해 플립-플롭(104)의 출력상태는 바뀌게 되어

가 높은 상태가 된다. 그 결과 NAND게이트(115)는 동작불능의 상태가 되고 클럭펄스 F4는 NAND게이트 116, 117을 통하여 AFT카운터(42)에 공급된다. 언급한 바와 같이 클럭펄스스 F4는 충분히 낮은 주파수를 갖고 있으므로, 국부발진회로 주파수가 fo에 도달하는 시각과 AFT제어중지신호 Z가 생기는 시각이 일치할 수 있다. 이리하여 AFT제어는 끝나게 되는 것이다.When the local oscillation frequency reaches the frequency fo corresponding to the selected channel during the AFT control period using the clock pulse F2, the AFT control stop signal Z (13b) is transmitted to the NOR gate 109. As a result, the output Q of the flip-flop 102 becomes high so that the timer circuit operates again. Output of flip-flop 103

Is maintained high when all inputs of the NOR gate 112 are low, and the output of the AND gate 118 becomes high as shown in FIG.

To make it low. This change causes the output state of the flip-flop 104 to change.

Becomes high. As a result, the NAND gate 115 becomes inoperable and the clock pulse F4 is supplied to the AFT counter 42 through the NAND gates 116 and 117. As mentioned, the clock pulse F4 has a sufficiently low frequency, so that the time when the local oscillation circuit frequency reaches fo and the time when the AFT control stop signal Z is generated may coincide. Thus, the AFT control ends.

The method used in the practical circuit of the present invention mentioned above, in order to convert the digital information into an analog voltage, the digital information is converted into a pulse group having a duty element which is a function of the information, It went through a lowpass filter to become an analog voltage. Instead, it is possible to use a digital-to-analog converter designed to convert the digital signal directly into an analog signal.

Claims (1)

A counter 42 for counting a clock signal, a digital-to-analog converter 16 and 17 for converting the digital output signal of the counter to a direct current voltage, and a fully tuned tuner to which all or part of the electric direct current voltage is applied as a tuning voltage. In an electronic channel selector having automatic frequency adjustment signal generation circuits 20 and 21 for outputting an automatic frequency adjustment signal corresponding to a difference in tuning frequencies to control the oscillation frequency of a local oscillator of an automatic tuning tuner, the counter 42 And a clock signal converter 24 for lowering the frequency of the clock signal when it detects that the tuning frequency is out of time when the counter 42 stops. Digital Chanel Selector.

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