KR790001034B1 - Circuit for two wire type series data communication and power transfer - Google Patents

Circuit for two wire type series data communication and power transfer Download PDF

Info

Publication number
KR790001034B1
KR790001034B1 KR780002519A KR780002519A KR790001034B1 KR 790001034 B1 KR790001034 B1 KR 790001034B1 KR 780002519 A KR780002519 A KR 780002519A KR 780002519 A KR780002519 A KR 780002519A KR 790001034 B1 KR790001034 B1 KR 790001034B1
Authority
KR
South Korea
Prior art keywords
data communication
transistor
signal
circuit
uart
Prior art date
Application number
KR780002519A
Other languages
Korean (ko)
Inventor
이재흥
Original Assignee
박율선
동양정밀공업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박율선, 동양정밀공업주식회사 filed Critical 박율선
Priority to KR780002519A priority Critical patent/KR790001034B1/en
Application granted granted Critical
Publication of KR790001034B1 publication Critical patent/KR790001034B1/en

Links

Images

Landscapes

  • Bidirectional Digital Transmission (AREA)

Abstract

A binary data signal is superimposed on the power line which is connected to the main system(A) and the sub-system(B), therfore the transmission and reception of DC binary data is possible by a halfduplex series unsynchronizing method. Salient features of the circuit include use of only two lines, reducing the complexity of the circuitry and amount of wire needed.

Description

2선식 직렬데이터통신 및 전력 전달회로2-wire serial data communication and power transmission circuit

첨부한 도면은 본 발명의 회로도The accompanying drawings show the circuit diagram of the present invention.

본 발명은 2선식 직렬데이터통신 및 전력전달회로에 관한 것으로, 전원선을 통하여 2진 송수신 테이터를 전달할 수 있도륵 한 것이다.The present invention relates to a two-wire serial data communication and power transmission circuit, it is possible to transmit the binary transmission and reception data through the power line.

일반적으로 통신 및 전력전달회로에 있어서 서로 가까운 거리에 띨어져 있는 주장치측과 부장치측 사이에 2진데이터를 송수하는 경우, 종래에는 직류신호로 직접 송수하는 방법을 많이 사용하고 있으나, 이는 부장치측 자체내에 전원을 직접 내장하지 않고 전원을 주장치 측으로부티 공급받고저 할때에는 전원 선과 데이터 신호선을병행하여 별도로 설치하였기 때문에 불필요한 선의 낭비와 설치상의 복잡성등이 뒤따르게되는 문제점이 초래되는 실정이었다.In general, in the case of transmitting binary data between the main device side and the sub device side separated from each other in a communication and power transmission circuit, conventionally, a method of directly transmitting a direct current signal is widely used. When power was not supplied directly to the main unit itself and the power was supplied to the main unit, power lines and data signal lines were separately installed in parallel, resulting in unnecessary waste of wires and complexity of installation.

본 발명은 상기와 같은 문제점을 해소하기위하여 주장치와 부장치에 공히 공급되는 전원선위에 2진데이터 신호를 중첩시켜 2가닥의 선만으로도 전원과 직류 2진데이터신호를 하프 듀프렉스(Half Duplex)직럴비동기 방식에 의하여 송수할 수 있도록 하여 종래의 불필요한 선의 낭비 및 이에따른 설치상의 복잡성등의 결점을 해소함에 목적을 둔 것으로, 이를 첨부한 도면에 의하여 상세히 설명하면 다음과 같다.The present invention overlaps the binary data signal on the power supply line that is supplied to both the main and sub-devices to solve the above problems, and the power supply and the direct current binary data signal are only half-duplex. The purpose of the present invention is to solve the drawbacks such as waste of unnecessary wires and consequent installation complexity by allowing water to be transmitted by an asynchronous method, which will be described in detail with reference to the accompanying drawings.

첨부한 도면은 본 발명의 실시예를 나타낸회로도로서 본 발명은 주장치측(A)과 부장치측(B)으로 구분구성하여, 주장치측(A) 트랜스(Tl)의 1차측(a)과 도선(ℓ1) 및 부장치측(B) 트랜스(T2)의 1차측(a')를 통하여 각 부하에 전원을 전달되게 하고 주장치측(A) 트랜스(Tl) 2차측(b)에 중앙 연산장치(l)측의 비동기 데이터 통신정합회로(UART1)와 키보오드측(111)의 비동기데이터통신접합회로(UART2)의 직렬 송, 수신데이터를 송수하는 트랜지스터(Ql)(Q2) 및 (Q11)(Q12)를 각각 접속 연결하되, 트랜지스터(Ql)는 주장지측(A)의 비동기 데이터통신 정합회로(UARTl)에서 출력되는 직렬송신데이터에 의하여 동작되도록하며 트랜지스터(Ql)가 동작할때 트랜스(Tl) 2차측(b)의 테이터신호가 1차측(a)에 중첩되어 전선(ℓ1)이 실려지게 한다.The accompanying drawings are circuit diagrams showing an embodiment of the present invention. The present invention is divided into a main device side (A) and a sub device side (B), and the primary side (a) of the main device side (A) transformer (T l ) and Power is transmitted to each load through the lead (l 1 ) and the auxiliary device side (B) transformer (T 2 ) and to the main device side (A) and the transformer (T l ) secondary side (b). Transistors Q l (Q l ) for transmitting serial transmission and reception data of the asynchronous data communication matching circuit (UART 1) of the central processing unit ( 1) and the asynchronous data communication junction circuit (UART 2 ) of the keyboard side (111). 2 ) and (Q 11 ) (Q 12 ) are connected to each other, but the transistor Q l is operated by the serial transmission data output from the asynchronous data communication matching circuit UART l of the claim A. When (Q l ) is operated, the data signal of the transformer (T l ) secondary side (b) is superimposed on the primary side (a) so that the wire ( 1 ) is loaded.

트랜지스터(Q2)는 부장치축(B)에서 전선(ℓ1) 및 트랜스(Tl)의 1차측(a)으로 보내지는 직렬수신데이터가 트랜스(T1)의 2차측(b)에 유기될때 그 신호에 따라 on,off 되도록 하여, 비동기데이터통신 정합회로(UARTl)가 직렬수신데이터를 수신하도록 한다.Transistor (Q 2) is induced in the secondary side (b) of the minor axis (B) wires (ℓ 1) and the transformer primary side (a) is a serial receive data transformer (T 1) is sent to the (T l) in The asynchronous data communication matching circuit (UART l ) receives the serial reception data.

부장치측(B)의 트랜지스터(Ql1)는 주장치측(A)의 트랜지스터(Ql)과 동일한 기능을 하도록 비동기데이터통신정합회로(UART2)에서 출력되는 직결송신데이터에 의하여 on,off 동작하여 트랜지스터(Ql1)가 on,off 동작할때 트랜스(T2)의 2차측(b')에 데이터신호가 1차측(a')에 유기되도륵 하고,1차측(a')에 유기된신호가 전원선(ℓ1)을 통하여 트랜스(Tl) 1차측(a)으로 보내지도록 한다.The transistor Q l1 of the sub-device side B operates on and off by direct transmission data output from the asynchronous data communication matching circuit UART 2 so as to have the same function as the transistor Q l of the main device side A. When the transistor Ql1 is turned on and off, the data signal may be induced on the secondary side b 'of the transformer T 2 on the primary side a', and is induced on the primary side a '. The signal is sent to the transformer (T 1 ) primary side (a) via the power supply line (L 1 ).

트랜지스터(Q12)는 주장치측(A)에서 보내지는 직렬송신데이터가 트랜스(T2)의 2차측(b')에 유기될때on,off 동작하도록 구성하며, 이의 on,off 동작에 따라 비동기데이터 통신정합회로(UART2)가 데이터신호를 수신하도록 구성한다.The transistor Q 12 is configured to operate on and off when the serial transmission data sent from the main device side A is induced to the secondary side b 'of the transformer T 2 . The communication matching circuit UART 2 is configured to receive the data signal.

이와 같은 구성방법에 의한 본 발명의 작동상태를 설명하면 다음과 같다.Referring to the operating state of the present invention by the configuration method as described above are as follows.

키보오드(1l1)에서 송출된 신호가 엔코더(112)에 의하여 부호화되고, 이 부호화된 신호는 일단 래치(113)에 보관되어 비동기 데이터통신 정합회로(UART2)가 송신준비가 완료되면 비동기데이터통신 정합회로(UART2)에 병열로 보내지게 되고, 이 병렬신호는 다시 비동기데이터통신정합회로(UART2)에서 직렬송신데이터 신호로 바뀌어 트랜지스터(Ql1)의 베이스에 인가되는데, 비동기 데이터통신 정합회로(UART2)의 신호는 인 버터(l14)를 통하여 반전되어 트랜지스터(Q11)의 베이스에 인가되므로서 비동기 테이터통신정합회로(UART2)의 출력이 H(High)일때는 트랜지스터(Q11)가 off되고, 츨력이 L(Low)인 상태이서는 트랜지스터(Ql1)가 on되는 방식으로 직렬송신데이터에 따라 트랜지스터(Ql1)이 on,off 동작을 반복하게 된다.The signal transmitted from the keyboard 1111 is encoded by the encoder 112, and the encoded signal is stored in the latch 113 so that the asynchronous data communication matching circuit UART 2 is ready for transmission. The parallel signal is sent in parallel to the matching circuit (UART 2 ), and the parallel signal is converted into a serial transmission data signal from the asynchronous data communication matching circuit (UART 2 ) and applied to the base of the transistor (Q l1 ). The signal of the UART 2 is inverted through the inverter 1 14 and applied to the base of the transistor Q 11 , so that the transistor Q 11 when the output of the asynchronous data communication matching circuit UART 2 is H (High). Is turned off and the output is L (Low), the transistor Q l1 is turned on in such a manner that the transistor Q l1 repeats the on and off operations according to the serial transmission data.

따라서 트랜지스터(Q11)가 on. off 동작을 반복하게될때 트랜지스터(Ql1)의 콜렉터측에 연결된 트랜스(T2)의 2차 측(b')에 도통, 차단을 반복되게 되고, 이 신호가 트랜스(T2)의 1차측(a')을 통하여 전원선(ℓ1)과 중첩되어 트랜스(Tl)의 1차측(a)으로 보내지게 되면서 트랜스(Tl)의 1차측(a)에도 도통, 차단상태가 되어 이 신호가 2차측(b)에 유기된다.Thus transistor Q 11 is on. When the off operation is repeated, the conduction and disconnection are repeated to the secondary side b 'of the transformer T 2 connected to the collector side of the transistor Q l1 , and this signal is repeated on the primary side of the transformer T 2 ( via a ') is superposed to the power line (ℓ 1) trans (also interconnecting the primary side (a) of the transformer (T l) as sent to the primary side (a) of T l), is a cut-off state this signal is It is induced on the secondary side (b).

트랜스(T2)의 2차측(b)에 유기된 신호는 트랜지스터(Q2)의 베이스에 인가되어 트랜지스터(Q2)릍 on, off 동작을 반복하게 되는데,Transformer (T 2) the signal induced in the secondary side (b) of is applied to the base of the transistor (Q 2) there is repetition of the transistor (Q 2) reut on, off operation,

트랜지스터(Q2)의 베이스에 인가되는 신호가 H일때에는 트랜지스터(Q2)가 도통(on) 상태가 되어 전원(V2)이 저항(R8)을 거쳐 트랜지스터(Q2)를 통하여 흐르기 때문에 인버티(1l5)에는 L의 신호가 입력되어 반전되면서 H의 클럭이 나타나 멀리프렉서(116)을 거쳐 비동기 데이터통신 정합회로(UARTl)에 직렬수신데이터신호가 입력되게 돤다.When the signal applied to the base of the transistor Q 2 is H, the transistor Q 2 is turned on so that the power supply V 2 flows through the transistor Q 2 through the resistor R 8 . When the signal of L is input to the invert 111 and inverted, the clock of H appears and the serial reception data signal is input to the asynchronous data communication matching circuit UART l through the far-fractioner 116.

이 직렬 수신데이터 신호는 비동기 데이터통신 정합회로(UARTl)에서 병렬 수신데이터로 바뀌어져 중앙연산장치(1)로 보내어져, 처리된 다음, 통화로부(2)로 보내어져 키보오드(111)에서 누른 번호에 해당되는 회선을 연결하여 주게 된다.The serial received data signal is converted into parallel received data by the asynchronous data communication matching circuit UART l , sent to the central computing device 1, processed, and then sent to the call path unit 2 and the keyboard 111. The line corresponding to the number pressed in will be connected.

통화로부(2)의 회선연결이 완료되면 중앙연산장치(1)에서 병렬송신데이터신호가 송출되고, 이 병렬 신호는 비동기 데이터 통신 정합회로(UARTl)로 보내어져 직렬송신 데이터신호로 바뀌어진 다음 디말티프렉서(117)를 통하여 해당 번호의 회선으로 직렬 송신 데이터신호가 보내지게되고 이 신호는 트랜지스터(Ql)의 베이스에 인가되는데, 이때에도 마찬가지로 비동기데이터통신 정합회로(UARTl)의 출력이 H인상태에는 인버터(118)에 의하여 트랜지스터(Q1)이 off상태를 유지하게 되고 출력이 L인 상태에서는 on상태를 유지하게되는 방법으로 계속 on,off 동작을 직렬 송신데이터 신호의 수 만큼 반복하게 된다.When the line connection of the communication path part 2 is completed, the parallel transmission data signal is transmitted from the central computing unit 1, and this parallel signal is sent to the asynchronous data communication matching circuit (UART l ) to be converted into a serial transmission data signal. The serial transmission data signal is then sent to the line of the corresponding number through the demal tip plexer 117, and this signal is applied to the base of the transistor Q l . In this case, the asynchronous data communication matching circuit UART l When the output is H, the transistor Q 1 is kept off by the inverter 118, and the output is kept on when the output is L. On, off operation is continued. Repeat as many times.

따라서 트랜지스터(Q1)이 on,off 동작을 반복함에 따라 트랜스(Tl)의 2차측(b)도 on,off가 반복되고, 이에 따라 1차측(a)에 단속파의 직렬 신호가 유기되어 전원선(ℓ1) 전원(V1)과 중첩되어 부장치(B)의 트랜스(T2)의 1차측(a')으로 전송되게 되고, 이 신호는 트랜스(T2)의 2차 측(b')에 유기되어 저항(R14)(R21)을 통하여 트랜지스터(Ql2)의 베이스에 인가되어 트랜지스터(Q12)의 on,off 동작을 반복 시키게 되면서 트랜지스터(Q12)의 콜렉터측에 출력이 나타나게 되는데, 그 출력이 H인 상태에서는 비동기 데이터통신 정합회로(UART2)에 L의 신호가 입력되고, L의 상태에서는 H의 신호가 입력되는 방식으로 비동기데이터통신 정합회로(UART2)에 직렬 수신데이터신호가 입력되게 된다.Therefore, as the transistor Q 1 repeats the on and off operations, the secondary side b of the transformer T l is also turned on and off, thereby inducing a series of intermittent signals on the primary side a. The power supply line 1 overlaps the power supply V 1 and is transmitted to the primary side a 'of the transformer T 2 of the auxiliary device B, and this signal is transmitted to the secondary side of the transformer T 2 ( b ') in the organic resistance (R 14) (R21) as thereby through is applied to the base of the transistor (Q l2) repeating the on, off operation of the transistor (Q 12) output on the collector side of the transistor (Q 12) When the output is H, the signal of L is input to the asynchronous data communication matching circuit (UART 2 ), and the signal of H is input to the asynchronous data communication matching circuit (UART 2 ) in the state of L. The serial receive data signal is input.

비동기 데이터통신 정합회로(UART2)에 입력된 직렬수신데이터신호는 다시 병렬신호로 바뀌어진 다음, 해당 번호를 가르키는 탬프(L.E.D)를 점등시키게 되면서 부저를 울러 주게 된다.The serial reception data signal inputted to the asynchronous data communication matching circuit (UART 2 ) is converted into a parallel signal again, and the buzzer sounds by turning on the LED indicating the corresponding number.

이와 같이 본 발명은 주장치측과 부장치측에 테이터신호를 송수 함에 있어 별도의 데이터신호선을 사용하지 않고 전력선에 직렬 송수신 데어터신호를 중첩시켜 송수 할 수 있도록 함으로서 그 설치가 극히 간편한 특징을 지닌 것이다.As described above, the present invention is extremely easy to install by transmitting and receiving data signals on the power line without using a separate data signal line in transmitting data signals to the main device side and the sub device side.

Claims (1)

도면에 표시하고 본문에 상술한 바와같이, 직류 2진 데이터를 트랜지스터(Q1)(Q2) 및 (Ql1)(Q12)를 이용한 하프듀프잭스(Half Duplex) 직렬 비동기 방식에 의하여 전원선(ℓ1)이 중첩시켜 송수 할 수 있도록 함을 특징으로 하는 2선식 직렬 데이터 통신 및 전력 전달회로.As shown in the drawing and described in the body, the direct current binary data, the transistor (Q 1) (Q 2) and (Q l1) half duplicating Jacks (Half Duplex) power source line by the serial asynchronous method using (Q 12) A two-wire serial data communication and power transmission circuit characterized in that (l 1 ) can be transmitted by overlapping.
KR780002519A 1978-08-18 1978-08-18 Circuit for two wire type series data communication and power transfer KR790001034B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR780002519A KR790001034B1 (en) 1978-08-18 1978-08-18 Circuit for two wire type series data communication and power transfer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR780002519A KR790001034B1 (en) 1978-08-18 1978-08-18 Circuit for two wire type series data communication and power transfer

Publications (1)

Publication Number Publication Date
KR790001034B1 true KR790001034B1 (en) 1979-08-21

Family

ID=19208473

Family Applications (1)

Application Number Title Priority Date Filing Date
KR780002519A KR790001034B1 (en) 1978-08-18 1978-08-18 Circuit for two wire type series data communication and power transfer

Country Status (1)

Country Link
KR (1) KR790001034B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8809069B2 (en) 2011-05-20 2014-08-19 Perkinelmer Health Sciences, Inc. Lab members and liquid handling systems and methods including same
US9073052B2 (en) 2012-03-30 2015-07-07 Perkinelmer Health Sciences, Inc. Lab members and liquid handling systems and methods including same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8809069B2 (en) 2011-05-20 2014-08-19 Perkinelmer Health Sciences, Inc. Lab members and liquid handling systems and methods including same
US9259737B2 (en) 2011-05-20 2016-02-16 Perkinelmer Health Sciences, Inc. Lab members and liquid handling systems and methods including same
US9073052B2 (en) 2012-03-30 2015-07-07 Perkinelmer Health Sciences, Inc. Lab members and liquid handling systems and methods including same
US9283557B2 (en) 2012-03-30 2016-03-15 Perkinelmer Health Sciences, Inc. Lab members and liquid handling systems and methods including same

Similar Documents

Publication Publication Date Title
JPS6432554A (en) Binary data communication system
ES2000218A6 (en) On-line serial communication interfaces.
KR790001034B1 (en) Circuit for two wire type series data communication and power transfer
GB1533867A (en) Transmission line driver circuit
KR860004374A (en) Subscriber Line Interface Modem
KR810002002Y1 (en) Power transmitter of two lines and binary data
KR880001872Y1 (en) Multi-drop transmission method
SU1413707A1 (en) Optronic transducer
SU1264363A1 (en) Device for duplex transmission of digital information via two-wire communication line
JPS59123047A (en) Converting system of character code
SU1358086A1 (en) Apparatus for bi-directional transmission of digital signals with conductive separation
KR0127877Y1 (en) Communication system with rs-485/rs-232 converter
SU1439611A1 (en) Device for interfacing computer with subscriber through telegraph channel
EP0210506A3 (en) Transmitting and receiving device
SU510794A1 (en) Data transfer device
KR890002143Y1 (en) Modulating circuit of data transmission system
JPS57194647A (en) Optical communication system
KR900001795B1 (en) Adaptor for communicating between systems using different signals
KR820002311Y1 (en) Circuit for useing line voltage in telephone
JPS57176441A (en) Data transfer system
KR850005113A (en) 4-wire keyboard communication method
JPS553222A (en) Signal transmission/reception system
JPS54122005A (en) Direct-current data transmitter
KR960040557A (en) Machine Tool Serial I / O Signal Level Inverter
JPS553220A (en) Signal transmission/reception system

Legal Events

Date Code Title Description
FPAY Annual fee payment

Payment date: 19900728

Year of fee payment: 12

EXPY Expiration of term