KR20240107460A - Gate driving circuit and foldable display apparatus including the same - Google Patents

Abstract

This specification discloses a gate driving circuit that can improve driving margin by applying a back bias voltage to the back gate electrode of a pull-down transistor of a gate driver, and a foldable display device including the same. The gate driving circuit includes a gate driver including a plurality of stages that respectively drive the gate lines of the display panel, each of the plurality of stages being coupled between a low potential voltage and an output terminal, and responding to a signal from the Q node. A pull-down transistor that pull-down drives the output stage, and the output stage outputs a gate signal; A pull-up transistor coupled between the output stage and a high potential voltage and pulling up the output stage in response to a signal from the QB node; A first capacitor coupled between the Q node and the output terminal; and a second capacitor coupled between the QB node and the high potential voltage, and the back gate electrode of the pull-down transistor is coupled to the power line to which the back bias voltage is applied.

Description

Gate driving circuit and foldable display device including the same {GATE DRIVING CIRCUIT AND FOLDABLE DISPLAY APPARATUS INCLUDING THE SAME}

This specification relates to a display device, and more specifically, to a gate driving circuit and a foldable display device including the same.

As the information society develops, the demand for display devices for displaying images in various forms is increasing, and various display devices such as liquid crystal displays and organic light emitting display devices are being utilized.

This display device includes a data driving circuit that supplies data signals to data lines of the display panel, and a gate driving circuit that sequentially supplies gate signals to gate lines of the display panel.

Recently, as display devices have become thinner, technologies for embedding a gate driving circuit in a display panel along with a pixel array are being developed. The gate driving circuit built into such a display panel is known as a GIP (Gate In Panel) driving circuit.

The gate driving circuit includes at least one gate driver. To maintain stable output, the gate driver sets the voltage of the Q node lower than the low potential voltage (VGL) using a bootstrap through a capacitor between the Q node and the output terminal. In this way, the gate driver needs to maintain the gate source voltage (VGS) of the pull-down transistor greater than the threshold voltage (Vth) when driving the output stage to pull down.

However, when the gate driver is driven for a long period of time, when the threshold voltage shifts due to transistor element deterioration, the driving ability of the pull-down transistor is reduced, which reduces the driving margin of the gate driver due to reduced bootstrap efficiency.

The inventors of this specification have invented a device that can improve the driving margin of a gate driver by shifting the threshold voltage of a pull-down transistor without a separate additional doping process or additional capacitor design.

The problem to be solved according to an embodiment of the present specification is to provide a gate driving circuit capable of improving driving margin by applying a back bias voltage to the back gate electrode of the pull-down transistor of the gate driver, and a foldable display device including the same.

In addition, the problem to be solved according to an embodiment of the present specification is to drive display areas at different frequencies by varying the back bias voltage applied to the back gate electrode of the pull-down transistor of the gate driver according to the change in frequency for driving the display panel. The goal is to provide a gate driving circuit that can improve the luminance difference and a foldable display device including the same.

The problems to be solved according to an embodiment of the present specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A gate driving circuit according to an embodiment of the present specification includes a gate driver including a plurality of stages that respectively drive gate lines of a display panel, each of the plurality of stages being coupled between a low potential voltage and an output terminal, , a pull-down transistor that pull-down drives the output stage in response to a signal from the Q node, and the output stage outputs a gate signal; A pull-up transistor coupled between the output stage and a high potential voltage and pulling up the output stage in response to a signal from the QB node; A first capacitor coupled between the Q node and the output terminal; and a second capacitor coupled between the QB node and the high potential voltage, and the back gate electrode of the pull-down transistor is coupled to the power line to which the back bias voltage is applied.

A foldable display device according to an embodiment of the present specification includes: a display panel including a first display area driven at a first frequency and a second display area driven at a second frequency different from the first frequency; and a first gate driver that outputs a first gate signal to the first display area, wherein the first gate driver includes a first plurality of stages, and each of the first plurality of stages outputs a first gate signal. It includes a first pull-down transistor that pull-down drives the first output terminal, and a first pull-up transistor that pull-up drives the first output terminal, and the back gate electrode of the first pull-down transistor is connected to the first power line to which the first back bias voltage is applied. are coupled.

According to embodiments, the driving margin can be improved by applying a back bias voltage to the back gate electrode of the pull-down transistor of the gate driver.

Additionally, the back bias voltage applied to the back gate electrode of the pull-down transistor of the gate driver can be varied according to the change in the frequency for driving the display panel, thereby improving the difference in luminance between display areas driven at different frequencies.

In addition to the above-described effects, specific effects of the present invention are described below while explaining specific details for carrying out the invention.

1 shows a gate driving circuit according to an embodiment of the present specification.
Figure 2 shows a timing diagram of a gate driving circuit according to an embodiment of the present specification.
Figure 3 shows a gate driving circuit according to another embodiment of the present specification.
Figure 4 shows a characteristic curve of a transistor that shifts according to the application of a back bias voltage.
Figure 5 shows a foldable display device according to an embodiment of the present specification.
FIG. 6 shows a timing diagram of regions driving at different frequencies in FIG. 5.
Figure 7 shows a gate driving circuit of a foldable display device according to another embodiment of the present specification.
Figure 8 shows the output waveform of the gate signal delayed according to the back bias voltage.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete and that common knowledge in the technical field to which this specification pertains is provided. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as ‘after’, ‘after’, ‘after’, ‘before’, etc., ‘immediately’ or ‘directly’ Non-consecutive cases may also be included unless ' is used.

In the case of a description of the signal flow relationship, for example, 'a signal is transmitted from node A to node B', unless 'immediately' or 'directly' is used, it is transmitted from node A to another node. This may include cases where a signal is transmitted to the B node.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

Each feature of the various embodiments of the present specification can be combined or combined with each other, partially or entirely, and various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, a gate driving circuit and a foldable display device including the same according to some embodiments will be described.

1 shows a gate driving circuit according to an embodiment of the present specification.

Although not shown in FIG. 1 , the gate driving circuit may include at least one gate driver, and the gate driver may include a plurality of stages that output gate signals to each of the gate lines of the display panel.

Referring to FIG. 1, each of the plurality of stages includes a pull-down transistor (T1), a pull-up transistor (T2), a first capacitor (CB), a second capacitor (CQB), a transfer transistor (TA), and a first transistor (T3). , includes a second transistor (T4), a third transistor (T5), and a fourth transistor (T6).

The pull-down transistor (T1) is coupled between the low-potential voltage (VGL) and the output terminal (OUT), and pull-down drives the output terminal (OUT) to the low-potential voltage (VGL) in response to the signal of the Q node. The gate signal output through the output terminal (OUT) is provided to the gate line of the display panel.

The pull-up transistor (T2) is coupled between the output terminal (OUT) and the high potential voltage (VGH), and pull-up drives the output terminal (OUT) to the high potential voltage (VGH) in response to the signal from the QB node.

The first capacitor (CB) is coupled between the Q node and the output terminal (OUT). The first capacitor (CB) charges the signal of the Q node. The first capacitor (CB) is used as a bootstrap to make the voltage of the Q node lower than the low potential voltage (VGL), so that the pull-down transistor (T1) can be stably turned on in response to the signal of the Q node.

The second capacitor (CQB) is coupled between the QB node and the high potential voltage (VGH). The second capacitor (CQB) charges the signal of the QB node.

The transfer transistor (TA) transfers the signal from the Q2 node to the Q node in response to the low potential voltage (VGL).

The first transistor T3 transmits the start signal VST to the Q2 node in response to the clock signal CLK. Here, the first transistor T3 is illustrated as transmitting the start signal VST to the Q2 node, but it can transmit the carry signal output from the previous stage to the Q2 node.

The second transistor T4 transmits the high potential voltage VGH to the Q1 node in response to the start signal VST. Here, the second transistor T4 is illustrated as being driven in response to the start signal VST, but it can be driven in response to a carry signal output from the previous stage.

The third capacitor (C_ON) is coupled between the Q1 node and the clock signal (CLK). The third capacitor (C_ON) charges or discharges the signal of the Q1 node according to the clock signal (CLK).

The third transistor T5 transmits the clock signal CLK to the QB node in response to the signal from the Q1 node.

The fourth transistor T6 delivers a high potential voltage (VGH) to the QB node in response to the signal from the Q2 node.

The gate signal of the output terminal (OUT) may be provided to the data line of the display panel and may be provided to the next stage as a carry signal. The next stage can output the gate signal in the next order in response to the carry signal.

Figure 2 shows a timing diagram of a gate driving circuit according to an embodiment of the present specification.

Referring to Figures 1 and 2, in order to maintain a stable output, the gate driver uses a bootstrap through the first capacitor (CB) between the Q node and the output terminal (OUT) to lower the voltage of the Q node to a low potential voltage (VGL). ) set lower than that. The voltage of the Q node can be lowered to a bootstrapped low level.

The gate driver's bootstrap occurs the moment the output terminal (OUT) changes from the high potential voltage (VGH) to the low potential voltage (VGL). The better the driving ability of the pull-down transistor, the higher the bootstrap efficiency.

However, when the gate driver's pull-down transistor element deteriorates due to long-term driving and the driving ability is reduced, the negative threshold voltage (Vth) based on the PMOS transistor is shifted and the bootstrap efficiency decreases, which causes the gate driver's output The driving margin for normalization may decrease.

Embodiments of the present specification apply a back bias voltage by coupling a separate power line to the back gate electrode of the transistor without adding a capacitor under a separate doping process or narrow bezel condition, thereby shifting the threshold voltage of the transistor to generate a gate electrode. We want to improve the driver's operating margin.

Figure 3 shows a gate driving circuit according to another embodiment of the present specification.

Figure 4 shows a characteristic curve of a transistor that shifts according to the application of a back bias voltage.

A gate driving circuit according to an embodiment may include at least one gate driver, and the gate driver may include a plurality of stages that output gate signals to each of the gate lines of the display panel.

Referring to FIGS. 3 and 4 , each of the plurality of stages includes a pull-down transistor (T1), a pull-up transistor (T2), a first capacitor (CB), and a second capacitor (CQB). FIG. 3 shows a partial circuit of the gate driver, and configurations common to FIG. 1 are replaced with the description of FIG. 1.

The pull-down transistor (T1) is coupled between the low-potential voltage (VGL) and the output terminal (OUT), and pull-down drives the output terminal (OUT) to the low-potential voltage (VGL) in response to the signal of the Q node. The gate signal output through the output terminal (OUT) is provided to the gate line of the display panel.

Here, the back gate electrode of the pull-down transistor T1 is coupled to the power line PL to which the back bias voltage VBS is applied. The back bias voltage (VBS) may vary according to changes in the frequency of the display panel. For example, back bias voltage (VBS) may increase as frequency is lowered.

By adjusting the back bias voltage (VBS), the threshold voltage of the pull-down transistor (T1) can be adjusted to the target threshold voltage, thereby improving the driving margin of the gate driver without adding a process or losing layout design area.

The pull-up transistor (T2) is coupled between the output terminal (OUT) and the high potential voltage (VGH), and pull-up drives the output terminal (OUT) to the high potential voltage (VGH) in response to the signal from the QB node.

The first capacitor (CB) is coupled between the Q node and the output terminal (OUT). The first capacitor (CB) charges the signal of the Q node. The first capacitor (CB) is used as a bootstrap to make the voltage of the Q node lower than the low potential voltage (VGL) so that the pull-down transistor (T1) can be turned on stably.

The second capacitor (CQB) is coupled between the QB node and the high potential voltage (VGH). The second capacitor (CQB) charges the signal of the QB node.

Metal oxide semiconductor (MOS) devices have the characteristic of shifting the current-voltage curve (I-V curve) in parallel according to the back bias voltage (VBS) applied to the back gate electrode.

In this specification, a back gate electrode is formed on the body of a pull-down transistor in a gate driver circuit that requires maximum driving ability, then a separate power line (PL) is coupled, and a back bias voltage (VBS) is applied to increase the threshold voltage (Vth). By shifting, the driving margin of the gate driver can be improved by improving the driving ability of the corresponding pull-down transistor and improving bootstrap efficiency.

Meanwhile, the back bias voltage (VBS) may be applied at a higher value than the low potential voltage (VGL) during the turn-on period of the pull-down transistor (T1). Additionally, the back bias voltage (VBS) may be applied at a value lower than the low potential voltage (VGL) during the turn-off period of the pull-down transistor (T1).

In this embodiment, leakage current can be prevented by applying a value lower than the low potential voltage (VGL) during the turn-off period of the pull-down transistor (T1) to block the pull-down transistor (T1).

Figure 5 shows a foldable display device according to an embodiment of the present specification. FIG. 6 shows a timing diagram of regions driving at different frequencies in FIG. 5.

Referring to FIGS. 5 and 6 , the foldable display device includes a display panel 100 that can be folded. The foldable display device can drive the display panel 100 using multiple frequencies. For example, the display panel 100 may include a first display area 110 driven at a first frequency and a second display area 120 driven at a second frequency different from the first frequency.

For example, when the display panel 100 is not folded, it may be driven at a frequency of 120 Hz. When the display panel 100 is folded, the first display area 110 may be driven at a frequency of 120 Hz and the second display area 120 may be driven at a low frequency between 1 and 60 Hz.

For example, when the display panel 100 is folded, an image may be displayed in the first display area 110 and a keyboard may be displayed in the second display area 120. The first display area 110 may be named the basic frequency driving area 110. The second display area 120 may be referred to as a low frequency driving area 120.

For example, the basic frequency driving area 110 of the display panel 100 may be driven at a frequency of 120 Hz and the low frequency driving area 120 may be driven at a frequency of 30 Hz.

The gate driver of the foldable display device can sequentially scan gate lines by sequentially outputting gate signals in response to a start signal (GIP VST) and a clock signal (CLK).

However, in the foldable display device, a luminance difference may occur between the basic frequency driving area 110 and the low frequency driving area 120 due to a variation in the clock load of the gate driver.

The foldable display device according to an embodiment of the present specification uses the timing delay deviation of the gate signal output generated by varying the back bias voltage of the pull-down transistor of the basic frequency driving region 110 and the low frequency driving region 120 to increase luminance. We want to improve the deviation.

Figure 7 shows a gate driving circuit of a foldable display device according to another embodiment of the present specification. Figure 8 shows the output waveform of the gate signal delayed according to the back bias voltage.

Referring to FIGS. 1, 7, and 8, the foldable display device includes a first gate driver 210 and a second gate driver 220.

First, the first gate driver 210 includes a first plurality of stages (GIP1, GIP2, GIP3 ~) that sequentially output gate signals to the gate lines of the basic frequency driving region 110.

Each of the first plurality of stages (GIP1, GIP2, GIP3 ~) includes a pull-down transistor (T1), a pull-up transistor (T2), a first capacitor (CB), a second capacitor (CQB), a transfer transistor (TA), and a first plurality of stages (GIP1, GIP2, GIP3 ~). It includes a transistor (T3), a second transistor (T4), a third transistor (T5), and a fourth transistor (T6).

The pull-down transistor (T1) is coupled between the low-potential voltage (VGL) and the output terminal (OUT), and pull-down drives the output terminal (OUT) to the low-potential voltage (VGL) in response to the signal of the Q node. The gate signal output through the output terminal (OUT) is provided to the gate line of the display panel.

The back gate electrode of the pull-down transistor T1 is coupled to the first power line PL to which the first back bias voltage VBS1 is applied. The first back bias voltage VBS1 may vary according to changes in the first frequency driving the basic frequency driving region 110.

The pull-up transistor (T2) is coupled between the output terminal (OUT) and the high potential voltage (VGH), and pull-up drives the output terminal (OUT) to the high potential voltage (VGH) in response to the signal from the QB node.

The first capacitor (CB) is coupled between the Q node and the output terminal (OUT).

The second capacitor (CQB) is coupled between the QB node and the high potential voltage (VGH).

The transfer transistor (TA) transfers the signal from the Q2 node to the Q node in response to the low potential voltage (VGL).

The first transistor T3 of the stage GIP1 transmits the start signal VST to the Q2 node in response to the clock signal CLK. The first transistor T3 of each of the remaining stages (GIP2, GIP3 ~) transmits the signal from the output terminal of the previous stage to the Q2 node as a carry signal.

The second transistor T4 of the stage GIP1 transmits the high potential voltage VGH to the Q1 node in response to the start signal VST. The second transistor (T4) of the remaining stages (GIP2, GIP3 ~) receives the signal from the output terminal (OUT) of the previous stage as a carry signal and transmits the high potential voltage (VGH) to the Q1 node in response to the carry signal. .

The third capacitor (C_ON) is coupled between the Q1 node and the clock signal (CLK). The third capacitor (C_ON) charges or discharges the signal of the Q1 node according to the clock signal (CLK).

The third transistor T5 transmits the clock signal CLK to the QB node in response to the signal from the Q1 node.

The fourth transistor T6 delivers a high potential voltage (VGH) to the QB node in response to the signal from the Q2 node.

Next, the second gate driver 220 includes a second plurality of stages (GIP1, GIP2, GIP3, ...) that sequentially output the gate signal to the gate line of the low frequency driving region 120.

Each of the second plurality of stages (GIP1, GIP2, GIP3 ~) includes a pull-down transistor (T1), a pull-up transistor (T2), a first capacitor (CB), a second capacitor (CQB), a transfer transistor (TA), and a first capacitor (CQB). It includes a transistor (T3), a second transistor (T4), a third transistor (T5), and a fourth transistor (T6).

The pull-down transistor (T1) is coupled between the low-potential voltage (VGL) and the output terminal (OUT), and pull-down drives the output terminal (OUT) to the low-potential voltage (VGL) in response to the signal of the Q node. The gate signal output through the output terminal (OUT) is provided to the gate line of the display panel.

The back gate electrode of the pull-down transistor T1 is coupled to the second power line PL to which the second back bias voltage VBS2 is applied. The second back bias voltage VBS2 may vary according to the change in the second frequency driving the low frequency driving region 120. For example, the second back bias voltage VBS2 may increase as the second frequency decreases.

For example, when the foldable display panel 100 is folded, the basic frequency driving area 110 may be driven at a first frequency of 120 Hz, the low frequency driving area 120 may be driven at a second frequency of 30 Hz, At this time, the second back bias voltage (VBS2) may be set to a value greater than the first back bias voltage (VBS1) according to the change in the second frequency.

The pull-up transistor (T2) of the second gate driver 220, the first capacitor (CB), the second capacitor (CQB), the transfer transistor (TA), the first transistor (T3), the second transistor (T4), and the third The transistor T5 and the fourth transistor T6 have the same configuration as the first gate driver 210.

Figure 8 shows the timing delay of the gate signal according to the back bias voltage, where the solid line represents the delay due to the first back bias voltage (VBS1) and the dotted line represents the delay due to the second back bias voltage (VBS2).

As such, the foldable display device according to the embodiment sets the back bias voltage of the pull-down transistor in the basic frequency driving region 110 and the low frequency driving region 120 to the first back bias voltage (VBS1) or the second back bias voltage (VBS2). ), the luminance deviation can be improved by using the timing delay deviation of the gate signal output that occurs by varying the .

A gate driving circuit according to an embodiment of the present specification includes a gate driver including a plurality of stages that respectively drive gate lines of a display panel, each of the plurality of stages being coupled between a low potential voltage and an output terminal, , a pull-down transistor that pull-down drives the output stage in response to a signal from the Q node, and the output stage outputs a gate signal; A pull-up transistor coupled between the output stage and a high potential voltage and pulling up the output stage in response to a signal from the QB node; A first capacitor coupled between the Q node and the output terminal; and a second capacitor coupled between the QB node and the high potential voltage, and the back gate electrode of the pull-down transistor is coupled to the power line to which the back bias voltage is applied.

The back bias voltage may vary according to changes in the frequency of the display panel.

The back bias voltage may increase as the frequency of the display panel decreases.

The gate driving circuit includes a first gate driver driving a first display area driven at a first frequency; and a second gate driver driving a second display area driven at a second frequency different from the first frequency.

The first gate driver may include a first plurality of stages, and each of the first plurality of stages may have a back gate electrode of a pull-down transistor coupled to a first power line to which a first back bias voltage is applied.

The second gate driver may include a second plurality of stages, and each of the second plurality of stages may have a back gate electrode of a pull-down transistor coupled to a second power line to which a second back bias voltage is applied.

When the second frequency of the second display area becomes smaller than the first frequency of the first display area, the second back bias voltage may vary to a value greater than the first back bias voltage according to the change in the second frequency.

Each of the plurality of stages includes: a transfer transistor that transmits a signal of the Q2 node to the Q node in response to a low potential voltage; A first transistor that transmits a start signal or carry signal to the Q2 node in response to a clock signal; a second transistor that delivers a high potential voltage to the Q1 node in response to a start signal or a carry signal; a third capacitor coupled between the Q1 node and the clock signal; a third transistor that transmits a clock signal to the QB node in response to the signal of the Q1 node; And it may further include a fourth transistor that delivers a high potential voltage to the QB node in response to the signal from the Q2 node.

The back bias voltage may be applied at a value greater than the low potential voltage during the turn-on period of the pull-down transistor.

The back bias voltage may be applied at a value lower than the low potential voltage during the turn-off period of the pull-down transistor.

A foldable display device according to an embodiment of the present specification includes a display panel including a first display area driven at a first frequency and a second display area driven at a second frequency different from the first frequency; and a first gate driver that outputs a first gate signal to the first display area, wherein the first gate driver includes a first plurality of stages, and each of the first plurality of stages outputs a first gate signal. a first pull-down transistor for pull-down driving a first output terminal, and a first pull-up transistor for pull-up driving the first output terminal, wherein the back gate electrode of the first pull-down transistor is connected to a first power supply to which a first back bias voltage is applied. Coupled with the line.

According to embodiments, the driving margin can be improved by applying a back bias voltage to the back gate electrode of the pull-down transistor of the gate driver.

Additionally, the back bias voltage applied to the back gate electrode of the pull-down transistor of the gate driver can be varied according to the change in the frequency for driving the display panel, thereby improving the difference in luminance between display areas driven at different frequencies.

As described above, the present invention has been described with reference to the illustrative drawings, but the present invention is not limited to the embodiments and drawings disclosed herein, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is obvious that transformation can occur. In addition, although the operational effects according to the configuration of the present invention were not explicitly described and explained while explaining the embodiments of the present invention above, it is natural that the predictable effects due to the configuration should also be recognized.

Claims (20)

A gate driver including a plurality of stages that respectively drive the gate lines of the display panel,
Each of the plurality of stages is,
a pull-down transistor coupled between a low-potential voltage and an output terminal and pulling down the output terminal in response to a signal from a Q node, the output terminal outputting a gate signal;
a pull-up transistor coupled between the output terminal and a high potential voltage and pulling up the output terminal in response to a signal from the QB node;
a first capacitor coupled between the Q node and the output terminal; and
comprising a second capacitor coupled between the QB node and the high potential voltage,
The back gate electrode of the pull-down transistor is coupled to a power line to which a back bias voltage is applied,
Gate driving circuit. According to claim 1,
The back bias voltage varies depending on the change in frequency of the display panel,
Gate driving circuit. According to claim 2,
The back bias voltage increases as the frequency of the display panel decreases,
Gate driving circuit. According to claim 1,
a first gate driver driving a first display area driven at a first frequency; and
A second gate driver driving a second display area driven at a second frequency different from the first frequency,
Gate driving circuit. According to claim 4,
The first gate driver includes a first plurality of stages, and the back gate electrode of the pull-down transistor of each of the first plurality of stages is coupled to a first power line to which a first back bias voltage is applied,
Gate driving circuit. According to claim 5,
The second gate driver includes a second plurality of stages, and the back gate electrode of the pull-down transistor of each of the second plurality of stages is coupled to a second power line to which a second back bias voltage is applied,
Gate driving circuit. According to claim 6,
When the second frequency of the second display area is smaller than the first frequency of the first display area, the second back bias voltage is greater than the first back bias voltage according to the change in the second frequency. Variable to,
Gate driving circuit. According to claim 1,
Each of the plurality of stages is,
a transfer transistor that transfers the signal of the Q2 node to the Q node in response to the low potential voltage;
a first transistor transmitting a start signal or a carry signal to the Q2 node in response to a clock signal;
a second transistor transmitting the high potential voltage to the Q1 node in response to the start signal or the carry signal;
a third capacitor coupled between the Q1 node and the clock signal;
a third transistor transmitting the clock signal to the QB node in response to the signal of the Q1 node; and
Further comprising a fourth transistor transmitting the high potential voltage to the QB node in response to the signal of the Q2 node,
Gate driving circuit. According to claim 1,
The back bias voltage is applied at a value greater than the low potential voltage during the turn-on period of the pull-down transistor.
Gate driving circuit. According to claim 1,
The back bias voltage is applied at a value lower than the low potential voltage during the turn-off period of the pull-down transistor.
Gate driving circuit. a display panel including a first display area driven at a first frequency and a second display area driven at a second frequency different from the first frequency; and
A first gate driver outputting a first gate signal to the first display area,
The first gate driver includes a first plurality of stages,
Each of the first plurality of stages,
A first pull-down transistor for pull-down driving a first output stage that outputs the first gate signal, and a first pull-up transistor for pull-up driving the first output stage,
The back gate electrode of the first pull-down transistor is coupled to a first power line to which a first back bias voltage is applied,
Foldable display device. According to claim 11,
The first back bias voltage varies depending on the change in the first frequency,
Foldable display device. According to claim 11,
Further comprising a second gate driver outputting a second gate signal to the second display area,
Foldable display device. According to claim 13,
The second gate driver includes a second plurality of stages,
Each of the second plurality of stages,
It includes a second pull-down transistor that pull-down drives the second output terminal through which the second gate signal is output, and a second pull-up transistor that pull-up drives the second output terminal,
The back gate electrode of the second pull-down transistor is coupled to a second power line to which a second back bias voltage is applied,
Foldable display device. According to claim 14,
The second back bias voltage varies according to the second frequency change,
Foldable display device. According to claim 15,
The second back bias voltage increases as the second frequency decreases,
Foldable display device. According to claim 14,
When the second frequency of the second display area is smaller than the first frequency of the first display area, the second back bias voltage is greater than the first back bias voltage according to the change in the second frequency. Variable to,
Foldable display device. According to claim 11,
Each of the first plurality of stages,
a transfer transistor that transfers the signal of the Q2 node to the Q node in response to the low potential voltage;
a first transistor transmitting a start signal or a carry signal to the Q2 node in response to a clock signal;
a second transistor transmitting the high potential voltage to the Q1 node in response to the start signal or the carry signal;
a third capacitor coupled between the Q1 node and the clock signal;
a third transistor transmitting the clock signal to the QB node in response to the signal of the Q1 node; and
Further comprising a fourth transistor transmitting the high potential voltage to the QB node in response to the signal of the Q2 node,
Foldable display device. According to claim 14,
The first back bias voltage and the second back bias voltage are applied as a value greater than the low potential voltage during the turn-on period of the first pull-down transistor and the second pull-down transistor.
Foldable display device. According to claim 14,
The first back bias voltage and the second back bias are applied at a value lower than the low potential voltage during the turn-off period of the first pull-down transistor and the second pull-down transistor,
Foldable display device.

Images