KR20240084375A - Transmitting device for generating multi-level signal and signal transmission and reception system including the same - Google Patents

Abstract

A transmitting device according to an embodiment of the present disclosure for realizing the above-described problem is disclosed. The transmitting device includes an encoder that generates a plurality of encoding signals based on a preset protocol, a driving circuit that generates a pair of driving signals corresponding to each encoding signal for each encoding signal, and driving based on a delay control signal. It includes a delay circuit that changes the transition point of the signal and an output circuit that generates a plurality of multi-level signals having different signal levels based on a difference in the voltage level of the driving signal, wherein the delay control signal includes at least one multi-level signal. It is characterized by controlling the occurrence point of the cross point that occurs due to the transition of the level signal.

Description

A transmitting device that generates a multi-level signal and a signal transmission and reception system including the same {TRANSMITTING DEVICE FOR GENERATING MULTI-LEVEL SIGNAL AND SIGNAL TRANSMISSION AND RECEPTION SYSTEM INCLUDING THE SAME}

The present disclosure relates to a transmission device, and more specifically, to a transmission device that generates a multi-level signal in a high-speed communication interface and a signal transmission and reception system including the same.

Different components within one electronic device transmit and receive signals through an interface. For example, mobile devices can communicate using various methods such as USB, Thunderbolt, ethernet, MIPI (Mobile Industry Processor Interface), HDMI, DisplayPort, Serial ATA (SATA), and LVDS (Low-Voltage Differential Signaling). At this time, the data signal exchanged between each component may include a clock signal. In other words, a device that generates a signal generates a multi-level signal by embedding a clock signal in the data signal. Clock signals are transmitted and received based on a unit interval (UI).

Meanwhile, in a system that communicates using multi-level signals, the cross-points of multi-level signals within a unit interval may occur due to physical limitations such as jitter and intersymbol interference (ISI). Multiple occurrences may occur. Due to the time difference in the occurrence of the cross point, a difference in delay time between data signals, that is, skew, may occur during the process of restoring the data signal using a multi-level signal in the receiving device. Accordingly, technology is required to reduce the time difference between the occurrence times of cross points.

Republic of Korea Patent Publication No. 10-2017-0008077 (2017.01.23)

The present disclosure has been made in response to the above-described background technology, and includes a transmitter that generates a multi-level signal that adjusts the transition point of the multi-level signal to reduce the time difference between the cross point occurrence of the multi-level signal occurring within a unit section, and It relates to a signal transmission and reception system including this.

However, the problems to be solved by this disclosure are not limited to the problems mentioned above, and other problems not mentioned can be clearly understood based on the description below.

A transmitting device according to an embodiment of the present disclosure for realizing the above-described problem is disclosed. The transmitting device includes an encoder that generates a plurality of encoding signals based on a preset protocol, a driving circuit that generates a pair of driving signals corresponding to each encoding signal for each encoding signal, and driving based on a delay control signal. It includes a delay circuit that changes the transition point of the signal and an output circuit that generates a plurality of multi-level signals having different signal levels based on a difference in the voltage level of the driving signal, wherein the delay control signal includes at least one multi-level signal. It is characterized by controlling the occurrence point of the cross point that occurs due to the transition of the level signal.

Alternatively, the delay circuit may change the transition point of the driving signal to reduce the time difference between the generation points of at least one cross point that occurs between the plurality of multi-level signals.

Alternatively, the delay control signal may be generated so that the skew of the data signal generated based on the plurality of multi-level signals falls within a preset range. Alternatively, the plurality of encoding signals may be clock signals. It is embedded, and the delay control signal may be generated so that the masking period or masking margin period of the restored clock signal generated based on the plurality of multi-level signals falls within a preset range.

Alternatively, the delay control signal may be generated to shorten the masking period or to lengthen the masking margin period.

Alternatively, the delay circuit may provide a transition point of the driving signal when at least one multi-level signal transitions from a low level to a mid-level or from a high level to a mid-level while all of the plurality of multi-level signals transition. can be changed.

Alternatively, the delay circuit may advance the transition time of a first multi-level signal transitioning from a low level to a mid-level or a second multi-level signal transitioning from a high level to a mid-level.

A signal transmission and reception system according to an embodiment of the present disclosure for realizing the above-described problems is disclosed. The signal transmission and reception system includes a transmitting device that generates a plurality of multi-level signals having different signal levels and a receiving device that generates a data signal based on the plurality of multi-level signals, and the transmitting device includes a plurality of An encoder for generating encoding signals, a driving circuit for generating, for each encoding signal, a pair of driving signals corresponding to each encoding signal, a delay circuit for changing the transition point of the driving signal based on a delay control signal, and the driving. It is characterized by comprising an output circuit that generates the plurality of multi-level signals based on the signal.

Alternatively, the transmitting device may generate the plurality of multi-level signals to reduce a time difference between occurrence times of at least one cross point that occurs between the plurality of multi-level signals.

Alternatively, the transmitting device may determine which signal to advance the transition point among a first multi-level signal transitioning from a low level to a mid-level or a second multi-level signal transitioning from a high level to a mid-level.

Alternatively, the transmitting device may determine a driving signal that will advance the transition point among a plurality of driving signals that generate the determined multi-level signal.

Alternatively, the plurality of multi-level signals include embedded clock signals, and the restored clock signal includes a garbage edge as at least one intersection occurs between the plurality of multi-level signals, The transmitting device may generate the plurality of multi-level signals to advance the generation time of the garbage clock edge.

Alternatively, the garbage clock edge may be generated by a first multi-level signal transitioning from a low level to a mid-level or a second multi-level signal transitioning from a high level to a mid-level.

Alternatively, the receiving device may reduce the masking section or increase the masking margin section as the generation time of the garbage clock edge advances.

According to an embodiment of the present disclosure, the time difference between the cross point occurrence points of the multi-level signal is reduced, the skew of the data signal can be reduced, and the characteristics of the eye diagram can be improved.

In addition, according to an embodiment of the present disclosure, in the case of a signal transmission and reception system in which a clock signal is embedded in a multi-level signal, the effect of advancing the garbage clock edge occurs, thereby securing a masking margin section of the restored clock signal generated at the receiving device end, thereby enabling high-speed High accuracy of multi-level signals can also be guaranteed in the communication interface.

1 is a block diagram showing a signal transmission and reception system according to an embodiment of the present disclosure.
Figure 2 is an example diagram illustrating the relationship between a multi-level signal and a restored clock signal according to an embodiment of the present disclosure.
Figure 3 is a block diagram showing a multi-level signal generation circuit according to an embodiment of the present disclosure.
Figure 4 is an example diagram illustrating the relationship between a multi-level signal and a restored clock signal according to an embodiment of the present disclosure.
Figure 5 is a circuit diagram showing a multi-level signal generation circuit according to an embodiment of the present disclosure.
Figure 6 is a timing diagram showing signals according to an embodiment of the present disclosure.

Below, with reference to the attached drawings, embodiments of the present disclosure are described in detail so that those skilled in the art (hereinafter referred to as skilled in the art) can easily practice the present disclosure. The embodiments presented in this disclosure are provided to enable any person skilled in the art to use or practice the subject matter of this disclosure. Accordingly, various modifications to the embodiments of the present disclosure will be apparent to those skilled in the art. That is, the present disclosure can be implemented in various different forms and is not limited to the following embodiments.

The same or similar reference numerals refer to the same or similar elements throughout the specification of this disclosure. Additionally, in order to clearly describe the present disclosure, reference numerals of parts in the drawings that are not related to the description of the present disclosure may be omitted.

As used in this disclosure, the term “or” is intended to mean an inclusive “or” and not an exclusive “or.” That is, unless otherwise specified in the present disclosure or the meaning is not clear from the context, “X uses A or B” should be understood to mean one of natural implicit substitutions. For example, unless otherwise specified in the present disclosure or the meaning is not clear from the context, “X uses A or B” means that It can be interpreted as one of the cases where all B is used.

As used in this disclosure, the term “at least one of A or B” should be interpreted to refer to all of A, B, and a combination of A and B.

The term “and/or” as used in this disclosure should be understood to refer to and include all possible combinations of one or more of the listed related concepts.

The terms “comprise” and/or “comprising” as used in this disclosure should be understood to mean that certain features and/or elements are present. However, the terms "comprise" and/or "including" should be understood as not excluding the presence or addition of one or more other features, other components, and/or combinations thereof.

Unless otherwise specified in this disclosure or the context is clear to indicate a singular form, the singular should generally be construed to include “one or more.”

The term “Nth (N is a natural number)” used in the present disclosure can be understood as an expression used to distinguish the components of the present disclosure according to a predetermined standard such as a functional perspective, a structural perspective, or explanatory convenience. there is. For example, in the present disclosure, components performing different functional roles may be distinguished as first components or second components. However, components that are substantially the same within the technical spirit of the present disclosure but must be distinguished for convenience of explanation may also be distinguished as first components or second components.

The term “connection” used in the present disclosure refers not only to the case where components are “directly connected,” but also to the case where other components “exist” in the middle, and to “electrically connect” other components in between. It should be interpreted to include cases where it is “connected.”

The explanation of the foregoing terms is intended to aid understanding of the present disclosure. Therefore, if the above-mentioned terms are not explicitly described as limiting the content of the present disclosure, it should be noted that the content of the present disclosure is not used in the sense of limiting the technical idea.

1 is a block diagram showing a signal transmission and reception system according to an embodiment of the present disclosure.

Referring to FIG. 1, the signal transmission/reception system 10 may include a transmission device 100 and a reception device 200.

The transmitting device 100 may generate a data signal and a clock signal and transmit the signals to the receiving device 200 through a plurality of signal lines. A plurality of signal lines may form one lane. At this time, signals transmitted through a plurality of signal lines may be multi-level signals having different signal levels. Multi-level signals are correlated with each other and can transition. The transmitting device 100 may generate a multi-level signal by embedding a clock signal in a data signal. To this end, the transmitting device 100 may be equipped with an encoder, a driving circuit, an output circuit, etc., which will be described later with reference to FIG. 3.

The receiving device 200 may restore the clock included in the multi-level signal based on the multi-level signal received from the transmitting device 100. At this time, the receiving device 200 may perform an operation of masking clock edges so that one clock signal exists within a clock unit interval (UI). Specifically, the receiving device 200 may generate a clock signal based on a multi-level signal and mask all but one clock edge within a unit interval. Through this, the receiving device 200 can generate a restored clock signal (rCLK). In this specification, a clock edge refers to a rising edge where a clock signal changes from low level to high level. Meanwhile, garbage clock edges refer to clock edges other than the first clock edge that appear within a unit section.

The receiving device 200 and the transmitting device 100 can transmit and receive signals according to various communication protocols. For example, the receiving device 200 and the transmitting device 100 may transmit and receive multi-level signals based on an interface defined according to the Mobile Industry Processor Interface (MIPI) standard.

Meanwhile, the receiving device 200 may perform various operations to restore the clock signal included in the multi-level signal. For example, the receiving device 200 may detect a unit interval (UI) of a clock signal and mask a specific clock edge so that one clock signal exists within the unit interval. That is, when a plurality of clock edges appear within a unit section, the clock edges that appear in a specific section can be masked so that only one clock edge exists. At this time, the masked clock edge may mean a garbage clock edge, and the specific section may mean a masking section.

To increase the accuracy of the clock recovery operation performed by the receiving device 200, the transmitting device 100 may perform operations according to the present disclosure.

Cross points where multi-level signals intersect occur within a unit section, and at this time, multiple cross points may occur depending on the difference in each crossing point. The transmitting device 100 according to the present disclosure generates a multi-level signal to reduce the time difference between the occurrence points of the cross point, so when the data signal is restored at the receiving device 200, skew is reduced and the characteristics of the eye diagram are reduced. This can be improved. Additionally, when the receiving device 200 generates a restored clock signal (rCLK) using a multi-level signal, a masking margin section is secured, thereby ensuring high accuracy of the multi-level signal even in a high-speed communication interface.

Meanwhile, the transmitting device 100 may generate a data signal and transmit the signal to the receiving device 200 through a plurality of signal lines. In this case, the receiving device 200 may generate a data signal based on the signal.

For example, the transmitting device 100 may be an application processor (AP), and the receiving device 200 may be a display device. Alternatively, the transmitting device 100 may be an image sensor and the receiving device 200 may be an application processor (AP), but are not limited thereto.

Figure 2 is an example diagram illustrating the relationship between a multi-level signal and a restored clock signal according to an embodiment of the present disclosure.

Referring to FIGS. 1 and 2 together, the transmitting device 100 can generate multi-level signals TX1, TX2, and TX3 that transition at any one of different voltage levels. For example, each multi-level signal (TX1, TX2, TX3) may transition from one of the high level, mid level, and low level voltage levels to another voltage level.

At this time, in this specification, the point where the multi-level signals (TX1, TX2, and TX3) cross each other is referred to as a cross point.

The receiving device 200 may generate clock edges corresponding to the transition points of the multi-level signals TX1, TX2, and TX3, and generate a restored clock signal rCLK based on this. A clock edge may be generated in response to the occurrence point of the cross point.

In Figure 2, the first multi-level signal (TX1) transitions from high level to low level, the second multi-level signal (TX2) transitions from mid-level to high level, and the third multi-level signal (TX3) transitions from low level to low level. You can transition from level to mid-level.

In this case, the clock edge occurs at the cross point of the first multi-level signal (TX1) and the second multi-level signal (TX2) and at the cross point of the first multi-level signal (TX1) and the third multi-level signal (TX3). can be created.

Ideally, one cross point is created, but multiple cross points are generated due to physical limitations. Accordingly, each clock edge appears at the receiving device 200 with a time difference. Among these, one clock edge, for example, the second clock edge, may be masked and referred to as a garbage clock edge.

In this way, a masking section (A) is defined to mask the garbage clock edge, and the minimum value of the masking section (A) is defined by the communication interface. For example, the masking section (A) can be defined as 0.35 to 0.6 UI.

The remaining section of the unit section (UI) excluding the masking section (A) is referred to as the masking margin section (B). As the communication speed increases, the unit interval (UI) becomes shorter, but the minimum masking interval (A) must be secured. Therefore, the masking margin section (B) becomes shorter.

The transmitting device 100 according to an embodiment of the present disclosure can adjust the transition point of a multi-level signal to reduce the time difference between the generation points of the cross point. In particular, when a multi-level signal embeds a clock signal, the transmitting device 100 may advance the occurrence time of the second clock edge that appears in the masking section (A) in order to secure the masking margin section (B). This increases the masking margin section (B) and ensures signal accuracy even in high-speed communication.

Meanwhile, in FIG. 2, three multi-level signals (TX1, TX2, TX3) are shown, and three voltage levels that the multi-level signals (TX1, TX2, TX3) can have are shown as high level, mid level, and low level. This is an example and the number and voltage levels of multi-level signals may vary.

FIG. 3 is a block diagram showing a multi-level signal generation circuit according to an embodiment of the present disclosure, and FIG. 4 is an exemplary diagram explaining the relationship between a multi-level signal and a restored clock signal according to an embodiment of the present disclosure.

3 and 4, the multi-level signal generation circuit 110 may include a control circuit 111, an encoder 112, a driving circuit 113, a delay circuit 114, and an output circuit 115. there is. The control circuit 111 may be divided into a separate configuration from the multi-level signal generation circuit 110. The multi-level signal generation circuit 110 may further include other components not shown, such as logic elements and signal processing circuits, in addition to the components described above.

The control circuit 111 may direct a series of operations to generate multi-level signals TX1, TX2, and TX3. The control circuit 111 may generate a delay control signal that adjusts the generation time of the multi-level signals TX1, TX2, and TX3 in order to reduce the time difference between the cross point generation times. That is, the delay control signal is used to control the occurrence point of a cross point that occurs when at least one multi-level signal transitions.

The control circuit 111 may determine which signal to advance the transition point among the multi-level signals TX1, TX2, and TX3. For example, the control circuit 111 may determine a multi-level signal that transitions to a mid-level. The control circuit 111 may determine a driving signal that will advance the transition point among a plurality of driving signals that generate the determined multi-level signal.

The control circuit 111 can identify situations in which a plurality of cross points occur and control the transition timing of specific multi-level signals (TX1, TX2, and TX3) based on this. Multiple cross points may occur in a situation where multiple multi-level signals (TX1, TX2, TX3) all transition.

Referring to (a) of FIG. 4, the first multi-level signal (TX1) transitions from high level to low level, the second multi-level signal (TX2) transitions from mid-level to high level, and the third multi-level signal (TX2) transitions from mid-level to high level. This is a case where the signal (TX3) transitions from low level to mid level. The control circuit 111 can advance the time of occurrence of the cross point of the first multi-level signal TX1 and the third multi-level signal TX3 by advancing the time when the third multi-level signal TX3 starts transition. there is.

Referring to (b) of FIG. 4, the first multi-level signal (TX1) transitions from high level to mid-level, the second multi-level signal (TX2) transitions from mid-level to low level, and the third multi-level signal (TX2) transitions from mid-level to low level. This is when the signal TX3 transitions from low level to high level. The control circuit 111 can advance the time of occurrence of the cross point of the first multi-level signal (TX1) and the third multi-level signal (TX3) by advancing the time when the first multi-level signal (TX1) starts transition. there is.

That is, the control circuit 111 may generate a delay control signal to advance the timing at which at least one multi-level signal (TX1, TX2, TX3) starts transition. The delay control signal is used to advance the transition point of at least one multi-level signal. The delay control signal ensures that the skew of the data signal generated based on a plurality of multi-level signals (TX1, TX2, TX3) falls within a preset reference range, or that the masking section or masking margin section of the restoration clock signal (rCLK) is preset. It can be created to fall within a set range. For example, the delay control signal may be generated to shorten the masking period or to lengthen the masking margin period.

The encoder 112 may generate a plurality of encoded signals in which a clock signal is embedded based on a preset protocol.

The driving circuit 113 may generate a pair of driving signals corresponding to the encoding signal.

The delay circuit 114 may adjust the transition point of the driving signal based on the delay control signal generated by the control circuit 111. That is, the delay circuit 114 can change the transition point of the driving signal to reduce the time difference between the occurrence times of at least one cross point that occurs between the plurality of multi-level signals TX1, TX2, and TX3. The delay circuit 114 delays the driving signal when all of the plurality of multi-level signals (TX1, TX2, and TX3) transition and at least one multi-level signal transitions from a low level to a mid-level or from a high level to a mid-level. The transition point can be changed. The delay circuit 114 may advance the transition time of a multi-level signal transitioning from a low level to a mid-level or a multi-level signal transitioning from a high level to a mid-level.

The output circuit 115 may generate a plurality of multi-level signals TX1, TX2, and TX3 having different signal levels based on the driving signal. The output circuit 115 may transmit a plurality of multi-level signals (TX1, TX2, TX3) to the receiving device (200 in FIG. 1) through channels corresponding to each of the plurality of multi-level signals (TX1, TX2, TX3). .

The receiving device 200 may generate a data signal and a restored clock signal (rCLK) based on a plurality of multi-level signals (TX1, TX2, and TX3). The data signal may be skewed as at least one crossover occurs between the plurality of multi-level signals (TX1, TX2, and TX3). Additionally, the recovery clock signal rCLK may include a garbage edge. The transmitting device (100 in FIG. 1) may generate a plurality of multi-level signals to reduce skew or advance the occurrence time of a garbage clock edge. The garbage clock edge may be generated by a multi-level signal transitioning from a low level to a mid-level or a multi-level signal transitioning from a high level to a mid-level. The receiving device 200 may reduce the masking section or increase the masking margin section as the time of occurrence of the garbage clock edge advances.

FIG. 5 is a circuit diagram showing a multi-level signal generation circuit according to an embodiment of the present disclosure, and FIG. 6 is a timing diagram showing a signal according to an embodiment of the present disclosure.

Referring to FIG. 5, the multi-level signal generation circuit 110 may have three channels. Below, the driving circuit 113, delay circuit 114, and output circuit 115 for one channel will be described, and the contents can be similarly applied to the remaining channels.

The driving circuit 113 may receive an encoding signal and generate a pair of driving signals DA1 and DA2 corresponding to the encoding signal. The voltage level of the first multi-level signal TX1 may be determined based on the voltage level difference between the pair of driving signals DA1 and DA2.

The delay circuit 114 may advance or delay the transition point of the driving signal based on the delay control signal. Delay circuit 114 may include a pair of buffers.

The output circuit 115 may include a pair of transistors, a pull-up resistor, and a pull-down resistor that receive a pair of driving signals DA1 and DA2. All of a pair of transistors can be implemented as NMOS transistors.

The output circuit 115 may generate the first multi-level signal TX1 by controlling the turn-on or turn-off of a pair of transistors based on the driving signals DA1 and DA2. The generated first multi-level signal may be transmitted to a receiving circuit through a channel. For example, the first multi-level signal TX1 may be generated based on the difference in voltage levels of the driving signals DA1 and DA2.

Referring to FIG. 6, the control circuit 111 may generate a delay control signal so that the first to sixth driving signals DA1, DA2, DB1, DB2, DC1, and DC2 transition as shown in ①. The control circuit 111 turns off the first driving signal DA1 at a second time point t2, turns on the second driving signal DA2, maintains the third driving signal DB1 in the turned-on state, and turns on the fourth driving signal DB1. The driving signal DB2 may be turned off, the fifth driving signal DC1 may be turned on, and the sixth driving signal DC2 may be kept turned on. As a result, the first cross point of the first multi-level signal (TX1) and the second multi-level signal (TX2) occurs at the third time point (t3), and the first multi-level signal (TX2) occurs at the fifth time point (t5). A second cross point of the third multi-level signal (TX1) and the third multi-level signal (TX3) occurs. Accordingly, the restored clock signal rCLK generated by the receiving device includes clock edges that appear at the third time point t3 and the fifth time point t5.

The control circuit 111 uses the first to sixth driving signals DA1 and DA2 as shown in ② in order to reduce the time difference between the occurrence of the first cross point and the occurrence of the second cross point at the third time point t3. , DB1, DB2, DC1, DC2) can generate a delay control signal to transition. The control circuit 111 may advance the transition time of the third multi-level signal TX3 transitioning from the low level to the mid level. To this end, the control circuit 111 may turn on the fifth driving signal DC1 at the first time point t1. As a result, the first multi-level signal TX1 and the third multi-level signal TX3 intersect at the fourth time point t4. Accordingly, the clock edge of the restored clock signal (rCLK) appears at the third time point (t3) and the fourth time point (t4), so that the clock edge that appears in the later order can be advanced.

Meanwhile, the extent to which the turn-on time of the fifth driving signal DC1 is advanced may be determined by the control circuit 111. For example, the control circuit 111 may determine the timing of advancing the first to third multi-level signals TX1, TX2, and TX3 based on the characteristics of the channel through which they are transmitted.

Meanwhile, in this specification, a configuration for reducing the time difference between two cross point generation times is disclosed, but the control circuit 111 can reduce the time difference between three or more cross point generation times. For example, the control circuit 111 may control the time difference between cross point generation times by advancing the transition times of two or more driving signals.

The various embodiments of the present disclosure described above may be combined with additional embodiments and may be changed within the scope understandable to those skilled in the art in light of the above detailed description. The embodiments of the present disclosure should be understood in all respects as illustrative and not restrictive. For example, each component described as unitary may be implemented in a distributed manner, and similarly, components described as distributed may also be implemented in a combined form. Accordingly, all changes or modified forms derived from the meaning and scope of the claims of the present disclosure and their equivalent concepts should be construed as being included in the scope of the present disclosure.

10: Signal transmission and reception system
100: Transmitting device
110: Multi-level signal generation circuit
111: control circuit
112: encoder
113: driving circuit
114: delay circuit
115: output circuit
200: receiving device
210: clock signal restoration circuit

Claims (14)

An encoder that generates a plurality of encoded signals based on a preset protocol;
For each encoding signal, a driving circuit that generates a pair of driving signals corresponding to each encoding signal;
a delay circuit that changes the transition point of the driving signal based on the delay control signal; and
An output circuit that generates a plurality of multi-level signals having different signal levels based on the voltage level difference of the driving signal,
The delay control signal is,
A transmitting device for controlling the occurrence point of a cross point that occurs when at least one multi-level signal transitions. According to paragraph 1,
The delay circuit is,
A transmitting device characterized in that the transition point of the driving signal is changed to reduce the time difference between the occurrence points of at least one cross point that occurs between the plurality of multi-level signals. According to paragraph 2,
The delay control signal is,
A transmitting device, characterized in that the skew of the data signal generated based on the plurality of multi-level signals is generated to fall within a preset range. According to paragraph 2,
The plurality of encoding signals have clock signals embedded therein,
The delay control signal is,
A transmitting device, characterized in that the masking section or masking margin section of the restored clock signal generated based on the plurality of multi-level signals is generated to fall within a preset range. According to paragraph 4,
The delay control signal is,
A transmitting device, characterized in that the masking section is shortened or the masking margin section is created to be long. According to paragraph 1,
The delay circuit is,
As the plurality of multi-level signals all transition,
A transmitting device that changes a transition point of the driving signal when at least one multi-level signal transitions from a low level to a mid-level or from a high level to a mid-level. According to clause 6,
The delay circuit is,
A transmitting device characterized in that it advances the transition time of a first multi-level signal transitioning from a low level to a mid-level or a second multi-level signal transitioning from a high level to a mid-level. A transmitting device that generates a plurality of multi-level signals having different signal levels; and
It includes a receiving device that generates a data signal based on the plurality of multi-level signals,
The transmitting device is,
An encoder that generates a plurality of encoded signals;
For each encoding signal, a driving circuit that generates a pair of driving signals corresponding to each encoding signal;
a delay circuit that changes a transition point of the driving signal based on a delay control signal; and
an output circuit that generates the plurality of multi-level signals based on the driving signal;
A signal transmission and reception system comprising: According to clause 8,
The transmitting device is,
A signal transmission and reception system characterized in that the plurality of multi-level signals are generated to reduce the time difference between the occurrence points of at least one cross point occurring between the plurality of multi-level signals. According to clause 9,
The transmitting device is,
A signal transmission and reception system characterized by determining which signal to advance the transition point among a first multi-level signal transitioning from a low level to a mid-level or a second multi-level signal transitioning from a high level to a mid-level. According to clause 10,
The transmitting device is,
A signal transmission and reception system characterized by determining a driving signal that will advance the transition point among a plurality of driving signals that generate a determined multi-level signal. According to clause 8,
The plurality of multi-level signals include embedded clock signals,
The restoration clock signal is,
As at least one intersection occurs between the plurality of multi-level signals, it includes a garbage clock edge,
The transmitting device is,
A signal transmission and reception system characterized in that the plurality of multi-level signals are generated to advance the generation time of the garbage clock edge. According to clause 12,
The garbage clock edge is,
A signal transmission and reception system characterized by being generated by a multi-level signal transitioning from a low level to a mid-level or a multi-level signal transitioning from a high level to a mid-level. According to clause 13,
The receiving device is,
A signal transmission and reception system characterized by reducing the masking section or increasing the masking margin section as the generation time of the garbage clock edge advances.

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