US20200235739A1 - High-speed signal driving device - Google Patents
High-speed signal driving device Download PDFInfo
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- US20200235739A1 US20200235739A1 US16/656,992 US201916656992A US2020235739A1 US 20200235739 A1 US20200235739 A1 US 20200235739A1 US 201916656992 A US201916656992 A US 201916656992A US 2020235739 A1 US2020235739 A1 US 2020235739A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
- H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Definitions
- the present invention relates to a driving device, and especially to a high-speed driving device to improve transmission quality of signals between a host and a device.
- An USB peripheral device of the USB2.0 standard includes a high-speed signal driving circuit.
- the high-speed signal driving circuit of the USB2.0 port includes a front-stage driver and a back-stage driver.
- the high-speed signal driving circuit transmits data to an external device connected by the USB peripheral device, it is required to maintain a fixed output voltage amplitude (or swing) such as 400 mV on an output node of the back-stage driver.
- the output voltage amplitude is determined by a load resistor of the external device, a load resistor of the host and the rated current of the back-stage driver.
- both the load resistor of the host and the load resistor of the device may be set to 45 ohms.
- the rated current Ispec of the high-speed driving circuit will be set to about 18 mA, such as 17.8 mA.
- the voltage amplitude at the output node of the back-stage driver cannot always maintain as the fixed output voltage such as 400 mV, but may be present as a voltage flipping from a high voltage level to a low voltage level or from the low voltage level to the high voltage level.
- a device and a method for precisely controlling and adjusting a signal flipping speed are required.
- the present invention discloses a new driving circuit that may adjust the delay time of a plurality of delayed signals generated in accordance with a signal by a delay adjuster, thereby achieving more precise control of signal rising and falling time.
- the driving circuit adds a fixed driving current to the signal transmission end to reduce rising and falling time of the signal.
- An embodiment of the present invention discloses a driving device that includes an assist driver, a delay adjuster, and a plurality of drivers.
- the assist driver receives a control signal and is coupled to a first output node and a second output node to output a first current to the first output node and the second output node.
- the delay adjuster receives the control signal to generate a plurality of delay signals, wherein each of the delay signals respectively has a different delay time corresponding to the control signal.
- the plurality of drivers respectively receives the control signal and one of the delay signals, and are respectively coupled to the first output node and the second output node via a first output end and a second output end.
- the plurality of drivers When the control signal is at a first logic level, the plurality of drivers respectively output a second current to the first output node via the first output end in response to the delay time. When the control signal is at a second logic level, the plurality of drivers respectively output the second current to the second output node via the second output in response to the delay time.
- FIG. 1 is a schematic diagram of a driving device 100 in accordance with an embodiment of the disclosure.
- FIG. 2 is a schematic diagram of a driving device circuit 200 in accordance with the embodiment of the disclosure.
- FIG. 3 is a schematic diagram of a driver 300 in FIG. 2 in accordance with the embodiment of the disclosure.
- FIG. 4 is a schematic diagram of an assist driver 400 in FIG. 2 in accordance with the embodiment of the disclosure.
- FIG. 5 is a block diagram of a driving device circuit 500 in accordance with another embodiment of the disclosure.
- FIG. 6 is a schematic diagram of a driver 600 in FIG. 5 in accordance with the embodiment of the disclosure.
- FIG. 7 is a schematic diagram of an assist driver 700 in FIG. 5 in accordance with the embodiment of the disclosure.
- FIG. 1 is a schematic diagram of a driving device 100 in accordance with an embodiment of the disclosure.
- the driving device 100 includes a front-stage driver 101 , a back-stage driver 102 , load resistors of a host 110 , including a first resistor R 1 and a second resistor R 2 , and load resistors of a device 112 , including a third resistor R 3 and a fourth resistor R 4 .
- the back-stage driver 102 via a pair of differential switches such as a p-type MOSFET 106 and a p-type MOSFET 108 respectively receives a pair of differential control signals Ctrln and Ctrlp output by the front-stage driver 101 , to control the direction of the current from a current source 104 , so as to accomplish the control of another pairs of differential signals flipping at a node DP and a node DM.
- a pair of differential switches such as a p-type MOSFET 106 and a p-type MOSFET 108 respectively receives a pair of differential control signals Ctrln and Ctrlp output by the front-stage driver 101 , to control the direction of the current from a current source 104 , so as to accomplish the control of another pairs of differential signals flipping at a node DP and a node DM.
- the voltage at the node DP rises up to the high voltage level, and the voltage at the node DM is pulled down to a ground voltage level.
- the signal Ctrlp output by the front-stage driver 101 is at the logic low level, the p-type MOSFET 108 turns on, the p-type MOSFET 106 turns off, the voltage at the node DM is at the high voltage level, and the voltage at the node DP is pulled down to the ground voltage level.
- the front-stage driver 101 directly adjusts the time of signal flipping between the node DP and the node DM via controlling the slew rate of the gate voltage from the p-type MOSFETs 106 and 108 of the back-stage driver 102 .
- the signal flipping between the node DP and the node DM means that the signal at the node DP changes from the low level to the high voltage level, meanwhile the signal at the node DM changes from the high level to the low voltage level, or the signal at the node DP changes from the high voltage level to the low level, meanwhile the signal at the node DM changes from the low level to the high level.
- the signal at the nodes DP and DM is a voltage signal or a current signal.
- the current output by the current source 104 is equal to the rated current Ispec of the driving device 100 .
- the high level and the low level are opposite to each other.
- the front-stage driver 101 outputs the differential signals Ctrln and Ctrlp to the p-type MOSFETs 106 and 108 , to indirectly control the signal flipping at the nodes DP and DM by adjusting the voltages of the control signals on the gates of p-type MOSFETs 106 and 108 , that is by controlling the slew rate of the gate voltage.
- the above operations cannot meet the increasingly precise adjustment requirement.
- FIG. 2 is a schematic diagram of a driving device circuit 200 in accordance with the embodiment of the disclosure.
- the driving device 200 includes a delay adjuster 202 , a driving portion 204 including at least a plurality of drivers S 1 ⁇ S 8 , an assist driver 206 , load resistors of a host 212 including a first resistor R 1 and a second resistor R 2 , and load resistors of a device 214 including a third resistor R 3 and a fourth resistor R 4 .
- the delay adjuster 202 receives a control signal 210 from the front-stage driver to generate a plurality of delay signals D 1 ⁇ D 7 , wherein the control signal 210 is one of a pair of differential signals from the front-stage driver, and corresponding to the control signal 210 each of the delay signals D 1 ⁇ D 7 has a different delay time.
- the driving portion 204 is coupled to the first output node DP and the second output node DM. As shown in FIG. 2 , each of the drivers S 1 ⁇ S 8 of the driving portion 204 includes an input end and two output ends.
- the driver S 1 includes an input control end Ctrl, a first output end Out 1 , and a second output end Out 2 , wherein the input control end Ctrl is coupled to the control signal 210 , the first output end Out 1 and the second output end Out 2 are respectively coupled to the first output node DP and the second output node DM.
- the input control end Ctrl of each of the drivers S 1 ⁇ S 8 receives the control signal 210 and the plurality of delay signals D 1 ⁇ D 7 .
- the input control end Ctrl of the driver S 1 receives the control signal 210
- the respective control end Ctrl of the drivers S 2 ⁇ S 8 receive the delay signals D 1 ⁇ D 7 one-by-one.
- the input control end Ctrl of driver S 2 receives delay signal D 1
- the input control end Ctrl of driver S 3 receives delay signal D 2
- the input control end Ctrl of driver S 8 receives delay signal D 7 .
- each of the drivers S 1 ⁇ S 8 outputs a current from the first output end Out 1 to the first output node DP in sequence of S 1 to S 8 in response to the control signal 210 and the delay signals D 1 ⁇ D 7 .
- each of the drivers S 1 ⁇ S 8 respectively outputs a current from the first output end Out 1 to the second output node DM in sequence in response to the control signal 210 and the delay signals D 1 ⁇ D 7 .
- the driving portion 204 includes eight single drivers S 1 ⁇ S 8
- the delay adjuster 202 includes seven delayers X 1 ⁇ X 7 that are coupled to each other in sequence.
- TD to represent the delay time of one of the delayers X 1 ⁇ X 7 .
- N*TD represents the sum of the delay time of the first N delayers, corresponding to the delayers X 1 ⁇ X 7
- N can be a positive integral 1 ⁇ 7
- the delay signals D 1 ⁇ D 7 respectively have 1*TD ⁇ 7*TD delay time corresponding to the control signal 210 .
- the drivers S 1 ⁇ S 8 are respectively turned on under the driving of the control signal 210 and the delay signals D 1 ⁇ D 7 .
- Each of the drivers S 1 ⁇ S 8 outputs a current to the second resistor R 2 and the fourth resistor R 4 in sequence, so that the voltage at the first output node DP gradually increases from a low voltage level to a high voltage level, or each of the drivers S 1 ⁇ S 8 outputs a current to the first resistor R 1 and the third resistor R 3 in sequence, so that the voltage at the second output node DM gradually increases from a low voltage level to a high voltage level.
- the eight drivers S 1 ⁇ S 8 are all turned on, the current that flows through the first output node DP or the second output node DM is equal to the rated current Ispec of the driving device.
- the drivers S 1 ⁇ S 8 are turned on in sequence for working effectively.
- the process takes a time of about 7*TD, which is the time it takes for a signal of either of the nodes DP or DM for rising from the low voltage level to the high voltage level or for falling from the high voltage level to the low voltage level.
- the driving portion 204 includes the drivers S 1 ⁇ S 8 , the current respectively may output from each of the drivers S 1 ⁇ S 8 is configured to be equal to one-eighth of the rated current Ispec of the driving device.
- the voltage of an output signal sent to the first output node DP or the second output node DM gradually increases from the low voltage level.
- the process takes a time of 7*TD, meanwhile the voltage of the output signal reaches a maximum value. Therefore, a precise controlling of the rising or falling time of the output signal from the first output node DP/the second output node DM may be done by adjusting the delay time TD of the delayers X 1 ⁇ X 7 or by adjusting the delay time 1*TD ⁇ 7*TD that the delay signals D 1 ⁇ D 7 corresponding to the control signal 210 .
- the delay time TDs of each of the delayers X 1 ⁇ X 7 are similar. In other embodiments, the delay time TD of each of the delayers X 1 ⁇ X 7 may be similar, different, or partially similar. In other embodiments, the current respectively output from the drivers S 1 ⁇ S 8 may be different or be partially similar, as long as the sum of the current of each of the drivers is equal to the rated current Ispec of the driving device. It should be noted that the number of drivers and the delay adjusters is merely illustrative and is not a limitation of the present invention.
- the driving device 200 further includes an assist driver 206 .
- the assist driver 206 includes a first output end Out 1 , a second output end Out 2 , and a control node Ctrl.
- the first output end Out 1 and the second output end Out 2 are respectively coupled to the first output node DP and the second output node DM.
- the control node Ctrl of the assist driver 206 directly receives the control signal 210 , and pre-generates a current with the value of one-eighth of the rated current Ispec of the driving device at the first output end Out 1 or the second output end Out 2 .
- the current is sent to the first output node DP and the second output node DM to appropriately speed up the output signals' flipping at the first output node DP and the second output node DM.
- the operation described above provides a partial current, such as one-eighth of the Ispec, to the first output node DP and the second output node DM in advance to speed up the output signal flipping, wherein the magnitude of the current may also be other value.
- This operation may resolve a problem that the load capacitance at the first output node DP or the second output node DM is too large, for example, the load capacitance is larger than 6 pF but smaller than 10 pF, so that the speed of the output signal flipping at the first output node DP or the second output node DM is slow. The detail will be described later.
- FIG. 3 is a schematic diagram of any of the drivers S 1 ⁇ S 8 in FIG. 2 in accordance with the embodiment of the disclosure.
- each of the drivers S 1 ⁇ S 8 in FIG. 2 includes a current source 300 , a first p-type MOSFET 302 , a second p-type MOSFET 304 , and an inverter 306 .
- the source S of the first p-type MOSFET 302 is coupled to the source S of the second p-type MOSFET 304
- the source S of the first p-type MOSFET 302 and the source S of the second p-type MOSFET 304 are commonly coupled to the current source 300 .
- the drain D of the first p-type MOSFET 302 serves as the first output end Out 1
- the drain D of the second p-type MOSFET 304 serves as the second output end Out 2
- the input end of the inverter 306 is coupled to the gate G of the second p-type MOSFET 304
- the output end of the inverter 306 is coupled to the gate G of the first p-type MOSFET 302 , wherein the input end of the inverter 306 of each of the drivers 202 serves as the control node Crtl of each of the drivers S 1 ⁇ S 8 .
- a current respectively output from each of the drivers S 1 ⁇ S 8 may be similar, different, or partially similar, as long as the sum of the current of each of the drivers is equal to the rated current Ispec of the driving device.
- the currents output by each current source 300 of each of the drivers may be similar, different, or partially similar, as long as the sum of the current output by the current source 300 of each of the drivers is equal to the rated current Ispec of the driving device.
- FIG. 4 is a schematic diagram of an assist driver 206 in FIG. 2 in accordance with the embodiment of the disclosure.
- the assist driver 206 includes a first control module 401 , a second control module 402 , and an assist module 403 .
- the first control module 401 receives the control signal 210 and sends a first control signal C 1 to the assist module 403
- the second control module 402 receives the control signal 210 and sends a second control signal C 2 to the assist module 403
- the assist module 403 receives the first control signal C 1 and the second control signal C 2 and outputs a current from the first output end Out 1 or the second output end Out 2 .
- the first control module 401 includes an inverter 404 , a NAND gate 405 , a delayer 407 , and a XOR gate 406 .
- the first input end of the XOR gate 406 is coupled to the input end of the delayer 407 and the input end of the inverter 404 to receive the control signal 210 .
- the output end of the delayer 407 is coupled to the second input end of the XOR gate 406 .
- the first input end of the NAND gate 405 is coupled to the output end of the inverter 404 .
- the second input end of the NAND gate 405 is coupled to the output end of the XOR gate 406 .
- the output end of the NAND gate 405 serves as the output end of the first control module 401 to send a first control signal C 1 to the assist module 403 .
- the delay time of the delayer 407 may be set to be but not limited in 1 ns.
- the second control module 402 includes an inverter 408 , a NAND gate 409 , a delayer 411 , a XOR gate 410 , and the other inverter 412 .
- the input end of the inverter 412 is coupled to the control signal 210 .
- the output end of the inverter 412 is coupled to the input end of the delayer 411 and the input end of the inverter 408 .
- the first input end of the XOR gate 410 is coupled to the input end of the delayer 411 and the input end of the inverter 408 , to receive the output signal from the inverter 412 .
- the output end of the delayer 411 is coupled to the second input end of the XOR gate 410 .
- the first input end of the NAND gate 409 is coupled to the output end of the inverter 408 .
- the second input end of the NAND gate 409 is coupled to the output end of the XOR gate 410 .
- the output end of the NAND gate 409 serves as the output end of the second control module 402 to send a second control signal C 2 to the assist module 403 .
- the delay time of the delayer 411 may also be set to be but not limited in 1 ns.
- the assist module 403 includes a current source 413 , a third p-type MOSFET 414 , and a fourth p-type MOSFET 415 .
- One end of the current source 413 is coupled to an operation voltage
- the other end of the current source 413 is coupled to the source S of the third p-type MOSFET 414 and the source S of the fourth p-type MOSFET 415 .
- the gate G of the third p-type MOSFET 414 is coupled to the first control signal C 1 from the first control module 401
- the drain D of the third p-type MOSFET 414 serves as the first output end Out 1 of the assist module 403 .
- the gate of the fourth p-type MOSFET 415 is coupled to the second control signal C 2 from the second control module 402 , and the drain D of the fourth p-type MOSFET 415 serves as the second output end Out 2 of the assist module 403 .
- the first control signal C 1 from the first module 401 is logic high level, so that the third p-type MOSFET 414 in the assist module 403 is turned off.
- the first input end of the XOR gate 406 receives the control signal 210 which currently is in logic high level state
- the second input end of the XOR gate 406 receives the control signal 210 which currently is in logic low level state, i.e.
- the control signal 210 before 1 ns thus the output of the XOR gate 406 is logic high level, and due to the logic low level output by the inverter 404 , the control signal C 1 sent by the NAND gate 405 to the assist module 403 is logic high level, at this moment, the third p-type MOSFET 414 in the assist module 403 is turned off.
- the control signal 210 is changed from a logic low level, such as logic L, to a logic high level, such as logic H, the second control signal C 2 from the second module 402 is logic low level, so that the fourth p-type MOSFET 415 in the assist module 403 is turned on.
- the first input end of the XOR gate 410 receives the inverted signal of the control signal 210 of the current logic high level state
- the second input end of the XOR gate 410 receives the inverted signal of the control signal 210 of the logic low level state, i.e. the inverted signal of the control signal 210 before 1 ns, thus the output of the XOR gate 410 is logic high level
- the control signal C 2 sent by the NAND gate 409 to the assist module 403 is logic low level, at this moment, the fourth p-type MOSFET 415 in the assist module 403 is turned on.
- the control signal 210 when the control signal 210 is changed from the logic high level to the logic low level, the first control signal C 1 from the first module 401 is logic low level, so that the third p-type MOSFET 414 in the assist module 403 is turned on, and the second control signal C 2 from the second module 402 is logic high level, so that the fourth p-type MOSFET 415 in the assist module 403 is turned off.
- the control signal 210 When the control signal 210 is maintained at the logic high level or maintained at the logic low level, the first control signal C 1 from the first control module 401 and the second control signal C 2 from the second control module 402 are simultaneously maintained at the logic high level, the third p-type MOSFET 414 and the fourth p-type MOSFET 415 in the assist module 403 are simultaneously turned off.
- the assist module 403 When the assist module 403 receives the first control signal C 1 of the logic high level and the second control signal C 2 of the logic low level, output the current of the current source 413 via the second output end Out 2 of the assist module 403 .
- the assist module 403 receives the first control signal C 1 of the logic low level and the second control signal C 2 of the logic high level, output the current of the current source 413 via the first output end Out 1 of the assist module 403 .
- the assist module 403 receives the first control signal C 1 of the logic high level and the second control signal C 2 of the logic high level, no current is output by the assist module 403 .
- the current of the current source 413 can be set to the average value of the currents generated in each of the drivers shown in FIG. 2 .
- the current of the current source 413 may be set to one-eighth of the rated current Ispec of the driving device.
- the assist driver 400 shown in FIG. 4 outputs a current prior to the drivers S 2 ⁇ S 8 , so that a maximum current accumulated at the first output node DP or the second output node DM is greater than one-eighth of the rated current Ispec of the driving device, the current output to the first output node DP or the second output node DM is pre-emphasized to further increase the amplitude of the output signal at the first output node DP or the second output node DM, so that the slope of the output signal rising and falling is turned steeper, to improve the transmission quality of the output signal.
- the assist driver 400 does not output any current, and because the delay time of the delayer 407 in the first control module 401 is the same as the delay time of the delayer 411 in the second control module 402 , wherein the delay time is set at a pre-determined value such as 1 ns, so that the assist driver 400 may be turned off before the output signal at the first output node DP or the second output node DM finishes a flipping action, to remove the influence on the amplitude of the output signal at the first output node DP or the second output node DM (de-emphasis) in time.
- a pre-determined value such as 1 ns
- Flipping time of the output signal at the first output node DP or the second output node DM can be controlled as the sum of the delay time of each of the delayers X 1 ⁇ X 7 .
- the flipping time of the output signal at the first output node DP or the second output node DM can be controlled as 7*TD.
- the flipping time of the output signal at the first output node DP or the second output node DM should be larger than 300 ps and be smaller than the delay time of the delayer 407 in the first control module 401 and smaller than the delay time of the delayer 411 in the second control module 402 .
- the output signal of the NAND gate in FIG. 4 can be directly coupled to the input end of the inverter 306 in FIG. 3 , and can also be coupled to one or more delayers or an even number of inverters first (not shown), after then, it may be coupled to the output end of the inverter 306 in FIG. 3 . It can be freely adjusted in accordance with the required circuit application and a logic level that is the logic high level or the logic low level.
- the rising and falling time of the signal flipping may be adjusted by controlling the current output from each of the current sources 300 .
- FIG. 5 is a block diagram of a driving device circuit 500 in accordance with another embodiment of the disclosure.
- the driving circuit 500 receives a pair of differential control signals 210 and 220 , so that it is necessary to add a delay adjuster 203 .
- the delay adjuster 203 includes delayers X 8 ⁇ X 14 .
- the delay adjuster 203 has the same structure as the delay adjuster 202 , so as to delay the control signal 220 .
- the delay that the delay adjuster 203 applied on the control signal 210 is synchronized with the delay that the delay adjuster 202 applied on the control signal 210 .
- the delay adjuster 203 generates a plurality of delay signals D 8 ⁇ D 14 corresponding to the delay signals D 1 ⁇ D 7 in FIG. 2 .
- each of the delay signals D 1 ⁇ D 7 in FIG. 2 being respectively coupled to the first input end Ctrl 1 of each of the drivers S 2 ⁇ S 8
- each of the delay signals D 1 ⁇ D 7 in FIG. 5 is respectively coupled to the first input end Ctrl 1 ′ of each of the drivers S 2 ′ ⁇ S 8 ′
- the delay signals D 8 ⁇ D 14 are respectively coupled to a second input control node Ctrl 2 ′ of each of the drivers S 2 ′ ⁇ S 8 ′ one-by-one.
- the control signals 210 and 220 are directly coupled to an assist driver 206 ′. The specific content will be described with reference to FIG. 6 and FIG. 7 .
- FIG. 6 is a schematic diagram of any of the drivers S 1 ′ ⁇ S 8 ′ in FIG. 5 in accordance with the embodiment of the disclosure.
- the difference between each of the drivers S 1 ′ ⁇ S 8 ′ in FIG. 5 and each of the drivers S 1 ⁇ S 8 in FIG. 3 is that a single driver in FIG. 5 , such us driver S 1 ′, does not include the inverter 306 shown in FIG. 3 , thus the gate of the first p-type MOSFET 302 directly serves as the second input control node Ctrl 2 ′ to receive the control signal 220 .
- FIG. 7 is a schematic diagram of an assist driver 206 ′ in FIG. 5 in accordance with the embodiment of the disclosure.
- the difference between the assist driver 206 ′ in FIG. 7 and the assist driver 206 in FIG. 4 is that the second control module 402 ′ in FIG. 7 does not include the inverter 412 shown in FIG. 4 , and the first input of the XOR gate 410 in the second control module 402 ′ is directly coupled to the control signal 220 , and the input of the delayer 411 in the second control module 402 ′ is directly coupled to the control signal 220 .
- the assist driver 700 in FIG. 7 and the driver S 1 ′ in FIG. 5 output a current prior to the driver S 2 ′ ⁇ S 8 ′, so that the current at the second output node DM gradually increases from a pre-determined current value, such as a quarter of the Ispec, to the value of the Ispec during a fixed time period.
- the fixed time period may be precisely controlled by adjusting the delay of the delayers X 8 ⁇ X 14 in FIG. 5 , i.e.
- the pre-determined current value is determined by the sum of the rated current of the current source 413 included by the assist driver 700 and the rated current of the current source 301 included by the driver S 1 in FIG. 5 .
- the rated current of a current source 413 included by the assist driver 700 is I 1 , such as one-eighth of the Ispec
- the rated current of the current source 300 included by the driver S 1 is I 2 , such as one-eigth of the Ispec
- the current at the first output node DP or the second output node DM is I 1 +I 2 , i.e. a quarter of the Ispec.
- the driving device of the disclosed embodiment of the present invention can be further applied to a higher speed data interface, such as Low-voltage Differential Signaling (LVDS), Mobile Industry Processor Interface (MIPI), and Peripheral Component Interconnect-Express (PCI-E) . . . etc.
- LVDS Low-voltage Differential Signaling
- MIPI Mobile Industry Processor Interface
- PCI-E Peripheral Component Interconnect-Express
Abstract
Description
- This application claims priority of China Patent Application No. 201910044600.0 filed on Jan. 17, 2019, the entirety of which is incorporated by reference herein.
- The present invention relates to a driving device, and especially to a high-speed driving device to improve transmission quality of signals between a host and a device.
- An USB peripheral device of the USB2.0 standard includes a high-speed signal driving circuit. The high-speed signal driving circuit of the USB2.0 port includes a front-stage driver and a back-stage driver.
- In the USB2.0 standard, when the high-speed signal driving circuit transmits data to an external device connected by the USB peripheral device, it is required to maintain a fixed output voltage amplitude (or swing) such as 400 mV on an output node of the back-stage driver. The output voltage amplitude is determined by a load resistor of the external device, a load resistor of the host and the rated current of the back-stage driver. According to the USB2.0 standard, both the load resistor of the host and the load resistor of the device may be set to 45 ohms. Thus, in order to maintain the output voltage amplitude as 400 mV, the rated current Ispec of the high-speed driving circuit will be set to about 18 mA, such as 17.8 mA.
- Obviously, the voltage amplitude at the output node of the back-stage driver cannot always maintain as the fixed output voltage such as 400 mV, but may be present as a voltage flipping from a high voltage level to a low voltage level or from the low voltage level to the high voltage level. Thus, in order to improve the performance for transmitting data from the high-speed signal driving circuit to the external device connected by the USB peripheral device, a device and a method for precisely controlling and adjusting a signal flipping speed are required.
- In order to resolve the issue described above, the present invention discloses a new driving circuit that may adjust the delay time of a plurality of delayed signals generated in accordance with a signal by a delay adjuster, thereby achieving more precise control of signal rising and falling time. In addition, when the signal starts to flip, the driving circuit adds a fixed driving current to the signal transmission end to reduce rising and falling time of the signal.
- An embodiment of the present invention discloses a driving device that includes an assist driver, a delay adjuster, and a plurality of drivers. The assist driver receives a control signal and is coupled to a first output node and a second output node to output a first current to the first output node and the second output node. The delay adjuster receives the control signal to generate a plurality of delay signals, wherein each of the delay signals respectively has a different delay time corresponding to the control signal. The plurality of drivers respectively receives the control signal and one of the delay signals, and are respectively coupled to the first output node and the second output node via a first output end and a second output end. When the control signal is at a first logic level, the plurality of drivers respectively output a second current to the first output node via the first output end in response to the delay time. When the control signal is at a second logic level, the plurality of drivers respectively output the second current to the second output node via the second output in response to the delay time.
-
FIG. 1 is a schematic diagram of adriving device 100 in accordance with an embodiment of the disclosure. -
FIG. 2 is a schematic diagram of adriving device circuit 200 in accordance with the embodiment of the disclosure. -
FIG. 3 is a schematic diagram of adriver 300 inFIG. 2 in accordance with the embodiment of the disclosure. -
FIG. 4 is a schematic diagram of anassist driver 400 inFIG. 2 in accordance with the embodiment of the disclosure. -
FIG. 5 is a block diagram of adriving device circuit 500 in accordance with another embodiment of the disclosure. -
FIG. 6 is a schematic diagram of adriver 600 inFIG. 5 in accordance with the embodiment of the disclosure. -
FIG. 7 is a schematic diagram of anassist driver 700 inFIG. 5 in accordance with the embodiment of the disclosure. - The present invention can be more fully understood by reading the subsequent detailed description with references made to the accompanying figures.
- It should be understood that the figures are not drawn to scale in accordance with standard practice in the industry. In fact, it is allowed to arbitrarily enlarge or reduce the size of devices for clear illustration.
- The high-speed signal driving circuit of the USB2.0 port includes a front-stage driver and a back-stage driver.
FIG. 1 is a schematic diagram of adriving device 100 in accordance with an embodiment of the disclosure. As shown inFIG. 1 , thedriving device 100 includes a front-stage driver 101, a back-stage driver 102, load resistors of ahost 110, including a first resistor R1 and a second resistor R2, and load resistors of adevice 112, including a third resistor R3 and a fourth resistor R4. - As shown in
FIG. 1 , the back-stage driver 102 via a pair of differential switches such as a p-type MOSFET 106 and a p-type MOSFET 108 respectively receives a pair of differential control signals Ctrln and Ctrlp output by the front-stage driver 101, to control the direction of the current from acurrent source 104, so as to accomplish the control of another pairs of differential signals flipping at a node DP and a node DM. Specifically, as shown inFIG. 1 , when the signal Ctrln output to a gate of the p-type MOSFET 106 is at a logic low level, and the signal Ctrlp output to a gate of the p-type MOSFET 108 is at a logic high level, the p-type MOSFET 106 turns on and the p-type MOSFET 108 turns off, and thus one half of the current output from thecurrent source 104 flows to the second resistor R2 connected to the node DP of thehost 110, and the other half of the current flows to the fourth resistor R4 connected to the node DP of thedevice 112. At this moment, the voltage at the node DP rises up to the high voltage level, and the voltage at the node DM is pulled down to a ground voltage level. Similarly, when the signal Ctrlp output by the front-stage driver 101 is at the logic low level, the p-type MOSFET 108 turns on, the p-type MOSFET 106 turns off, the voltage at the node DM is at the high voltage level, and the voltage at the node DP is pulled down to the ground voltage level. Based on the description above, the front-stage driver 101 directly adjusts the time of signal flipping between the node DP and the node DM via controlling the slew rate of the gate voltage from the p-type MOSFETs stage driver 102. The signal flipping between the node DP and the node DM means that the signal at the node DP changes from the low level to the high voltage level, meanwhile the signal at the node DM changes from the high level to the low voltage level, or the signal at the node DP changes from the high voltage level to the low level, meanwhile the signal at the node DM changes from the low level to the high level. The signal at the nodes DP and DM is a voltage signal or a current signal. According to an embodiment of the present invention, the current output by thecurrent source 104 is equal to the rated current Ispec of thedriving device 100. According to some embodiments of the present invention, the high level and the low level are opposite to each other. - But the structure described above has 2 drawbacks: (1) the front-
stage driver 101 outputs the differential signals Ctrln and Ctrlp to the p-type MOSFETs type MOSFETs -
FIG. 2 is a schematic diagram of adriving device circuit 200 in accordance with the embodiment of the disclosure. As shown inFIG. 2 , thedriving device 200 includes adelay adjuster 202, adriving portion 204 including at least a plurality of drivers S1˜S8, anassist driver 206, load resistors of ahost 212 including a first resistor R1 and a second resistor R2, and load resistors of adevice 214 including a third resistor R3 and a fourth resistor R4. Thedelay adjuster 202 receives acontrol signal 210 from the front-stage driver to generate a plurality of delay signals D1˜D7, wherein thecontrol signal 210 is one of a pair of differential signals from the front-stage driver, and corresponding to thecontrol signal 210 each of the delay signals D1˜D7 has a different delay time. Thedriving portion 204 is coupled to the first output node DP and the second output node DM. As shown inFIG. 2 , each of the drivers S1˜S8 of thedriving portion 204 includes an input end and two output ends. For example, the driver S1 includes an input control end Ctrl, a first output end Out1, and a second output end Out2, wherein the input control end Ctrl is coupled to thecontrol signal 210, the first output end Out1 and the second output end Out2 are respectively coupled to the first output node DP and the second output node DM. The input control end Ctrl of each of the drivers S1˜S8 receives thecontrol signal 210 and the plurality of delay signals D1˜D7. Specifically, the input control end Ctrl of the driver S1 receives thecontrol signal 210, the respective control end Ctrl of the drivers S2˜S8 receive the delay signals D1˜D7 one-by-one. For example, the input control end Ctrl of driver S2 receives delay signal D1, the input control end Ctrl of driver S3 receives delay signal D2, and the input control end Ctrl of driver S8 receives delay signal D7. Moreover, when thecontrol signal 210 is at a first logic level, such as at a high voltage level, each of the drivers S1˜S8 outputs a current from the first output end Out1 to the first output node DP in sequence of S1 to S8 in response to thecontrol signal 210 and the delay signals D1˜D7. When thecontrol signal 210 is at a second logic level, such as at a low voltage level, each of the drivers S1˜S8 respectively outputs a current from the first output end Out1 to the second output node DM in sequence in response to thecontrol signal 210 and the delay signals D1˜D7. - In a present embodiment, the
driving portion 204 includes eight single drivers S1˜S8, and thedelay adjuster 202 includes seven delayers X1˜X7 that are coupled to each other in sequence. Using TD to represent the delay time of one of the delayers X1˜X7. If N*TD represents the sum of the delay time of the first N delayers, corresponding to the delayers X1˜X7, N can be apositive integral 1˜7, the delay signals D1˜D7 respectively have 1*TD˜7*TD delay time corresponding to thecontrol signal 210. In sequence, the drivers S1˜S8 are respectively turned on under the driving of thecontrol signal 210 and the delay signals D1˜D7. Each of the drivers S1˜S8 outputs a current to the second resistor R2 and the fourth resistor R4 in sequence, so that the voltage at the first output node DP gradually increases from a low voltage level to a high voltage level, or each of the drivers S1˜S8 outputs a current to the first resistor R1 and the third resistor R3 in sequence, so that the voltage at the second output node DM gradually increases from a low voltage level to a high voltage level. Until the eight drivers S1˜S8 are all turned on, the current that flows through the first output node DP or the second output node DM is equal to the rated current Ispec of the driving device. During the process that the current at the first output node DP or the second output node DM is accumulated from zero or a fixed current value to the rated current Ispec, the drivers S1˜S8 are turned on in sequence for working effectively. The process takes a time of about 7*TD, which is the time it takes for a signal of either of the nodes DP or DM for rising from the low voltage level to the high voltage level or for falling from the high voltage level to the low voltage level. In the present embodiment, the drivingportion 204 includes the drivers S1˜S8, the current respectively may output from each of the drivers S1˜S8 is configured to be equal to one-eighth of the rated current Ispec of the driving device. During the process that the eight drivers S1˜S8 are successively turned on in sequence, the voltage of an output signal sent to the first output node DP or the second output node DM gradually increases from the low voltage level. When the eight drivers S1˜S8 are all turned on, the process takes a time of 7*TD, meanwhile the voltage of the output signal reaches a maximum value. Therefore, a precise controlling of the rising or falling time of the output signal from the first output node DP/the second output node DM may be done by adjusting the delay time TD of the delayers X1˜X7 or by adjusting thedelay time 1*TD˜7*TD that the delay signals D1˜D7 corresponding to thecontrol signal 210. In this embodiment, the delay time TDs of each of the delayers X1˜X7 are similar. In other embodiments, the delay time TD of each of the delayers X1˜X7 may be similar, different, or partially similar. In other embodiments, the current respectively output from the drivers S1˜S8 may be different or be partially similar, as long as the sum of the current of each of the drivers is equal to the rated current Ispec of the driving device. It should be noted that the number of drivers and the delay adjusters is merely illustrative and is not a limitation of the present invention. - As shown in
FIG. 2 , the drivingdevice 200 further includes anassist driver 206. Theassist driver 206 includes a first output end Out1, a second output end Out2, and a control node Ctrl. The first output end Out1 and the second output end Out2 are respectively coupled to the first output node DP and the second output node DM. When the logic level of thecontrol signal 210 is changed (for example, it may be changed from a logic high level to a logic low level, or changed from the logic low level to the logic high level), the control node Ctrl of theassist driver 206 directly receives thecontrol signal 210, and pre-generates a current with the value of one-eighth of the rated current Ispec of the driving device at the first output end Out1 or the second output end Out2. The current is sent to the first output node DP and the second output node DM to appropriately speed up the output signals' flipping at the first output node DP and the second output node DM. The operation described above provides a partial current, such as one-eighth of the Ispec, to the first output node DP and the second output node DM in advance to speed up the output signal flipping, wherein the magnitude of the current may also be other value. This operation may resolve a problem that the load capacitance at the first output node DP or the second output node DM is too large, for example, the load capacitance is larger than 6 pF but smaller than 10 pF, so that the speed of the output signal flipping at the first output node DP or the second output node DM is slow. The detail will be described later. -
FIG. 3 is a schematic diagram of any of the drivers S1˜S8 inFIG. 2 in accordance with the embodiment of the disclosure. As shown inFIG. 3 , each of the drivers S1˜S8 inFIG. 2 includes acurrent source 300, a first p-type MOSFET 302, a second p-type MOSFET 304, and aninverter 306. The source S of the first p-type MOSFET 302 is coupled to the source S of the second p-type MOSFET 304, and the source S of the first p-type MOSFET 302 and the source S of the second p-type MOSFET 304 are commonly coupled to thecurrent source 300. The drain D of the first p-type MOSFET 302 serves as the first output end Out1, and the drain D of the second p-type MOSFET 304 serves as the second output end Out2. The input end of theinverter 306 is coupled to the gate G of the second p-type MOSFET 304, and the output end of theinverter 306 is coupled to the gate G of the first p-type MOSFET 302, wherein the input end of theinverter 306 of each of thedrivers 202 serves as the control node Crtl of each of the drivers S1˜S8. As described above, a current respectively output from each of the drivers S1˜S8 may be similar, different, or partially similar, as long as the sum of the current of each of the drivers is equal to the rated current Ispec of the driving device. Thus, the currents output by eachcurrent source 300 of each of the drivers may be similar, different, or partially similar, as long as the sum of the current output by thecurrent source 300 of each of the drivers is equal to the rated current Ispec of the driving device. -
FIG. 4 is a schematic diagram of anassist driver 206 inFIG. 2 in accordance with the embodiment of the disclosure. As shown inFIG. 4 , theassist driver 206 includes afirst control module 401, asecond control module 402, and anassist module 403. Thefirst control module 401 receives thecontrol signal 210 and sends a first control signal C1 to theassist module 403, thesecond control module 402 receives thecontrol signal 210 and sends a second control signal C2 to theassist module 403, and theassist module 403 receives the first control signal C1 and the second control signal C2 and outputs a current from the first output end Out1 or the second output end Out2. - As shown in
FIG. 4 , thefirst control module 401 includes aninverter 404, aNAND gate 405, adelayer 407, and aXOR gate 406. The first input end of theXOR gate 406 is coupled to the input end of thedelayer 407 and the input end of theinverter 404 to receive thecontrol signal 210. The output end of thedelayer 407 is coupled to the second input end of theXOR gate 406. The first input end of theNAND gate 405 is coupled to the output end of theinverter 404. The second input end of theNAND gate 405 is coupled to the output end of theXOR gate 406. The output end of theNAND gate 405 serves as the output end of thefirst control module 401 to send a first control signal C1 to theassist module 403. According to an embodiment of the present invention, the delay time of thedelayer 407 may be set to be but not limited in 1 ns. - As shown in
FIG. 4 , thesecond control module 402 includes aninverter 408, aNAND gate 409, adelayer 411, aXOR gate 410, and theother inverter 412. The input end of theinverter 412 is coupled to thecontrol signal 210. The output end of theinverter 412 is coupled to the input end of thedelayer 411 and the input end of theinverter 408. The first input end of theXOR gate 410 is coupled to the input end of thedelayer 411 and the input end of theinverter 408, to receive the output signal from theinverter 412. The output end of thedelayer 411 is coupled to the second input end of theXOR gate 410. The first input end of theNAND gate 409 is coupled to the output end of theinverter 408. The second input end of theNAND gate 409 is coupled to the output end of theXOR gate 410. The output end of theNAND gate 409 serves as the output end of thesecond control module 402 to send a second control signal C2 to theassist module 403. According to an embodiment of the present invention, corresponding to thedelayer 407 described above, the delay time of thedelayer 411 may also be set to be but not limited in 1 ns. - As shown in
FIG. 4 , theassist module 403 includes acurrent source 413, a third p-type MOSFET 414, and a fourth p-type MOSFET 415. One end of thecurrent source 413 is coupled to an operation voltage, the other end of thecurrent source 413 is coupled to the source S of the third p-type MOSFET 414 and the source S of the fourth p-type MOSFET 415. The gate G of the third p-type MOSFET 414 is coupled to the first control signal C1 from thefirst control module 401, and the drain D of the third p-type MOSFET 414 serves as the first output end Out1 of theassist module 403. The gate of the fourth p-type MOSFET 415 is coupled to the second control signal C2 from thesecond control module 402, and the drain D of the fourth p-type MOSFET 415 serves as the second output end Out2 of theassist module 403. - When the
control signal 210 is changed from a logic low level, such as logic L, to a logic high level, such as logic H, the first control signal C1 from thefirst module 401 is logic high level, so that the third p-type MOSFET 414 in theassist module 403 is turned off. Specifically, in thefirst control module 401, the first input end of theXOR gate 406 receives thecontrol signal 210 which currently is in logic high level state, the second input end of theXOR gate 406 receives thecontrol signal 210 which currently is in logic low level state, i.e. thecontrol signal 210 before 1 ns, thus the output of theXOR gate 406 is logic high level, and due to the logic low level output by theinverter 404, the control signal C1 sent by theNAND gate 405 to theassist module 403 is logic high level, at this moment, the third p-type MOSFET 414 in theassist module 403 is turned off. When thecontrol signal 210 is changed from a logic low level, such as logic L, to a logic high level, such as logic H, the second control signal C2 from thesecond module 402 is logic low level, so that the fourth p-type MOSFET 415 in theassist module 403 is turned on. Specifically, in thesecond control module 402, the first input end of theXOR gate 410 receives the inverted signal of thecontrol signal 210 of the current logic high level state, the second input end of theXOR gate 410 receives the inverted signal of thecontrol signal 210 of the logic low level state, i.e. the inverted signal of thecontrol signal 210 before 1 ns, thus the output of theXOR gate 410 is logic high level, and due to the logic high level output by theinverter 408, the control signal C2 sent by theNAND gate 409 to theassist module 403 is logic low level, at this moment, the fourth p-type MOSFET 415 in theassist module 403 is turned on. Similarly, when thecontrol signal 210 is changed from the logic high level to the logic low level, the first control signal C1 from thefirst module 401 is logic low level, so that the third p-type MOSFET 414 in theassist module 403 is turned on, and the second control signal C2 from thesecond module 402 is logic high level, so that the fourth p-type MOSFET 415 in theassist module 403 is turned off. When thecontrol signal 210 is maintained at the logic high level or maintained at the logic low level, the first control signal C1 from thefirst control module 401 and the second control signal C2 from thesecond control module 402 are simultaneously maintained at the logic high level, the third p-type MOSFET 414 and the fourth p-type MOSFET 415 in theassist module 403 are simultaneously turned off. - When the
assist module 403 receives the first control signal C1 of the logic high level and the second control signal C2 of the logic low level, output the current of thecurrent source 413 via the second output end Out2 of theassist module 403. When theassist module 403 receives the first control signal C1 of the logic low level and the second control signal C2 of the logic high level, output the current of thecurrent source 413 via the first output end Out1 of theassist module 403. When theassist module 403 receives the first control signal C1 of the logic high level and the second control signal C2 of the logic high level, no current is output by theassist module 403. The current of thecurrent source 413 can be set to the average value of the currents generated in each of the drivers shown inFIG. 2 . For example, according to an embodiment of the present invention inFIG. 2 , the current of thecurrent source 413 may be set to one-eighth of the rated current Ispec of the driving device. - Referring together to
FIG. 2 , when thecontrol signal 210 is flipped, theassist driver 400 shown inFIG. 4 outputs a current prior to the drivers S2˜S8, so that a maximum current accumulated at the first output node DP or the second output node DM is greater than one-eighth of the rated current Ispec of the driving device, the current output to the first output node DP or the second output node DM is pre-emphasized to further increase the amplitude of the output signal at the first output node DP or the second output node DM, so that the slope of the output signal rising and falling is turned steeper, to improve the transmission quality of the output signal. In other words, when the load capacitance at the first output node DP or the second output node DM is large, the rising and falling time of the output signal at the first output node DP or the second output node DM is further compressed by theassist driver 400 inFIG. 4 when thecontrol signal 210 is flipped. When thecontrol signal 210 ends up the flipping, theassist driver 400 does not output any current, and because the delay time of thedelayer 407 in thefirst control module 401 is the same as the delay time of thedelayer 411 in thesecond control module 402, wherein the delay time is set at a pre-determined value such as 1 ns, so that theassist driver 400 may be turned off before the output signal at the first output node DP or the second output node DM finishes a flipping action, to remove the influence on the amplitude of the output signal at the first output node DP or the second output node DM (de-emphasis) in time. - Flipping time of the output signal at the first output node DP or the second output node DM can be controlled as the sum of the delay time of each of the delayers X1˜X7. For example, as shown in
FIG. 2 , when the delay time of each of the delayers X1˜X7 is similar, and the delay time of each of the delayers X1˜X7 is TD, then the flipping time of the output signal at the first output node DP or the second output node DM can be controlled as 7*TD. According to current technique, the flipping time of the output signal at the first output node DP or the second output node DM should be larger than 300 ps and be smaller than the delay time of thedelayer 407 in thefirst control module 401 and smaller than the delay time of thedelayer 411 in thesecond control module 402. - In another embodiment of the present disclosure, the output signal of the NAND gate in
FIG. 4 , such as aNAND gate 405, can be directly coupled to the input end of theinverter 306 inFIG. 3 , and can also be coupled to one or more delayers or an even number of inverters first (not shown), after then, it may be coupled to the output end of theinverter 306 inFIG. 3 . It can be freely adjusted in accordance with the required circuit application and a logic level that is the logic high level or the logic low level. - In another embodiment of the present disclosure, as shown in
FIG. 3 , the rising and falling time of the signal flipping may be adjusted by controlling the current output from each of thecurrent sources 300. -
FIG. 5 is a block diagram of adriving device circuit 500 in accordance with another embodiment of the disclosure. As shown inFIG. 5 , unlike the embodiment inFIG. 2 , the drivingcircuit 500 receives a pair ofdifferential control signals delay adjuster 203. Thedelay adjuster 203 includes delayers X8˜X14. Thedelay adjuster 203 has the same structure as thedelay adjuster 202, so as to delay thecontrol signal 220. The delay that thedelay adjuster 203 applied on thecontrol signal 210 is synchronized with the delay that thedelay adjuster 202 applied on thecontrol signal 210. Specifically, thedelay adjuster 203 generates a plurality of delay signals D8˜D14 corresponding to the delay signals D1˜D7 inFIG. 2 . Corresponding to each of the delay signals D1˜D7 inFIG. 2 being respectively coupled to the first input end Ctrl1 of each of the drivers S2˜S8, each of the delay signals D1˜D7 inFIG. 5 is respectively coupled to the first input end Ctrl1′ of each of the drivers S2′˜S8′, and the delay signals D8˜D14 are respectively coupled to a second input control node Ctrl2′ of each of the drivers S2′˜S8′ one-by-one. And the control signals 210 and 220 are directly coupled to anassist driver 206′. The specific content will be described with reference toFIG. 6 andFIG. 7 . -
FIG. 6 is a schematic diagram of any of the drivers S1′˜S8′ inFIG. 5 in accordance with the embodiment of the disclosure. As shown inFIG. 6 , the difference between each of the drivers S1′˜S8′ inFIG. 5 and each of the drivers S1˜S8 inFIG. 3 is that a single driver inFIG. 5 , such us driver S1′, does not include theinverter 306 shown inFIG. 3 , thus the gate of the first p-type MOSFET 302 directly serves as the second input control node Ctrl2′ to receive thecontrol signal 220. -
FIG. 7 is a schematic diagram of anassist driver 206′ inFIG. 5 in accordance with the embodiment of the disclosure. As shown inFIG. 7 , the difference between theassist driver 206′ inFIG. 7 and theassist driver 206 inFIG. 4 is that thesecond control module 402′ inFIG. 7 does not include theinverter 412 shown inFIG. 4 , and the first input of theXOR gate 410 in thesecond control module 402′ is directly coupled to thecontrol signal 220, and the input of thedelayer 411 in thesecond control module 402′ is directly coupled to thecontrol signal 220. - Referring to
FIG. 5 toFIG. 7 , when thecontrol signal 210 is flipped, such as being changed from the logic high level to the logic low level, itsdifferential signal 220 is flipped correspondingly, such as being changed from the logic low level to the logic high level. At this moment, theassist driver 700 inFIG. 7 and the driver S1′ inFIG. 5 output a current prior to the driver S2′˜S8′, so that the current at the second output node DM gradually increases from a pre-determined current value, such as a quarter of the Ispec, to the value of the Ispec during a fixed time period. The fixed time period may be precisely controlled by adjusting the delay of the delayers X8˜X14 inFIG. 5 , i.e. by adjusting the delay time TD of each single delayer, wherein the delay time TD of each of the delayers X8˜X14 may be adjusted. The pre-determined current value is determined by the sum of the rated current of thecurrent source 413 included by theassist driver 700 and the rated current of thecurrent source 301 included by the driver S1 inFIG. 5 . For example, the rated current of acurrent source 413 included by theassist driver 700 is I1, such as one-eighth of the Ispec, and the rated current of thecurrent source 300 included by the driver S1 is I2, such as one-eigth of the Ispec, and then the current at the first output node DP or the second output node DM is I1+I2, i.e. a quarter of the Ispec. Similar to the structure inFIG. 4 , theassist driver 700 inFIG. 7 functions as a pre-emphasis and a de-emphasis to further speed up the output signal flipping at the first output node DP and the second output node DM, and to counteract a influence of load capacitance at the first output node DP or the second output node DM. - In addition to being applicable to USB, the driving device of the disclosed embodiment of the present invention can be further applied to a higher speed data interface, such as Low-voltage Differential Signaling (LVDS), Mobile Industry Processor Interface (MIPI), and Peripheral Component Interconnect-Express (PCI-E) . . . etc.
- The ordinal in the specification and the claims of the present invention, such as “first”, “second”, “third”, etc., has no sequential relationship, and is just for distinguishing between two different devices with the same name. In the specification of the present invention, the word “couple” refers to any kind of direct or indirect electronic connection. The present invention is disclosed in the preferred embodiments as described above, however, the breadth and scope of the present invention should not be limited by any of the embodiments described above. Persons skilled in the art can make small changes and retouches without departing from the spirit and scope of the invention. The scope of the invention should be defined in accordance with the following claims and their equivalents.
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US7298173B1 (en) * | 2004-10-26 | 2007-11-20 | Marvell International Ltd. | Slew rate control circuit for small computer system interface (SCSI) differential driver |
US7486112B2 (en) * | 2005-08-23 | 2009-02-03 | Nec Electronics Corporation | Output buffer circuit with de-emphasis function |
US8228096B2 (en) * | 2007-03-02 | 2012-07-24 | Kawasaki Microelectronics, Inc. | Circuit and method for current-mode output driver with pre-emphasis |
US9871539B2 (en) * | 2013-07-16 | 2018-01-16 | Mediatek Inc. | Driver circuit for signal transmission and control method of driver circuit |
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US10700685B1 (en) | 2020-06-30 |
CN109783421A (en) | 2019-05-21 |
CN109783421B (en) | 2022-05-03 |
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