KR20240082018A - Method for manufacturing the same - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to forming a stacked pattern on a substrate, wherein the stacked pattern includes active layers and sacrificial layers alternately stacked with each other; forming a sacrificial pattern extending in a first direction on the stacked pattern; forming a nitrided pattern by nitriding both side walls of the sacrificial pattern; forming a recess in the stacked pattern by etching the stacked pattern using the sacrificial pattern as a mask, wherein the active layers include a plurality of semiconductor patterns exposed by the recess; forming a source/drain pattern filling the recess; removing the sacrificial pattern, the nitride pattern, and the sacrificial layers to expose the plurality of semiconductor patterns; forming a gate insulating film on the exposed plurality of semiconductor patterns; and forming a gate electrode on the gate insulating layer, wherein an upper portion of the nitride pattern has a first width in a second direction, a lower portion of the nitride pattern has a second width in the second direction, and The second width is greater than the first width.

Description

Method for manufacturing semiconductor devices {Method for manufacturing the same}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same.

Semiconductor devices are attracting attention as important elements in the electronics industry due to characteristics such as miniaturization, multi-functionality, and/or low manufacturing cost. Semiconductor devices can be divided into semiconductor memory devices that store logical data, semiconductor logic devices that operate and process logical data, and hybrid semiconductor devices that include memory elements and logic elements. As the electronics industry develops highly, demands for the characteristics of semiconductor devices are increasing. For example, demands for high reliability, high speed, and/or multifunctionality for semiconductor devices are increasing. In order to meet these required characteristics, structures within semiconductor devices are becoming increasingly complex, and semiconductor devices are also becoming increasingly highly integrated.

The problem to be solved by the present invention is to provide a semiconductor device with improved reliability and a method of manufacturing the same.

A method of manufacturing a semiconductor device according to the concept of the present invention includes forming a stacking pattern on a substrate, the stacking pattern including active layers and sacrificial layers alternately stacked with each other; forming a sacrificial pattern extending in a first direction on the stacked pattern; forming a nitrided pattern by nitriding both side walls of the sacrificial pattern; forming a recess in the stacked pattern by etching the stacked pattern using the sacrificial pattern as a mask, wherein the active layers include a plurality of semiconductor patterns exposed by the recess; forming a source/drain pattern filling the recess; removing the sacrificial pattern, the nitride pattern, and the sacrificial layers to expose the plurality of semiconductor patterns; forming a gate insulating film on the exposed plurality of semiconductor patterns; and forming a gate electrode on the gate insulating layer, wherein an upper portion of the nitride pattern has a first width in a second direction, a lower portion of the nitride pattern has a second width in the second direction, and The second width may be larger than the first width.

In the method of manufacturing a semiconductor device according to the present invention, a nitrided pattern is formed by nitriding both side walls of the sacrificial pattern, and the width of the lower part of the nitrided pattern may be wider than the width of the upper part. As a result, the lower and upper widths of the gate electrode and gate cutting patterns formed through multiple etching processes can be kept constant. The width of the gate electrode and gate cutting patterns can be formed consistently, and the formation of empty space in the gate electrode can be prevented. As a result, the present invention can improve the reliability of semiconductor devices.

1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention.
Figure 4 is a plan view for explaining a semiconductor device according to an embodiment of the present invention.
FIGS. 5A to 5E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of FIG. 4, respectively.
6 to 21C are diagrams for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.
FIGS. 6, 8, 10, 14, 16, and 20 are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.
FIGS. 7A, 9A, 11A, 15A, 17A, and 21A are cross-sectional views taken along line A-A' of FIGS. 6, 8, 10, 14, 16, and 20, respectively.
FIGS. 7B, 9B, 15B, 17B, and 21B are cross-sectional views taken along line B-B' of FIGS. 6, 8, 14, 16, and 20, respectively.
FIG. 11B is a diagram for explaining a method of manufacturing a semiconductor device according to other embodiments of the present invention.
FIG. 12 is an enlarged view showing an example of area M of FIG. 11A.
FIGS. 13A and 13B are diagrams showing processes after the processes shown in FIGS. 12A and 12B, respectively.
FIGS. 15C, 17C, and 21C are cross-sectional views taken along line C-C' of FIGS. 14, 16, and 20, respectively.
FIG. 15D is a cross-sectional view taken along line D-D' in FIG. 14.
FIGS. 18A and 18B are diagrams showing processes after the processes shown in FIGS. 17A and 17B, respectively.
FIGS. 19A and 19B are enlarged views showing an example of region N of FIG. 18A.

1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention.

Referring to FIG. 1, a single height cell (SHC) may be provided. Specifically, a first power wire (M1_R1) and a second power wire (M1_R2) may be provided on the substrate 100. The first power wiring (M1_R1) may be a path through which the drain voltage (VDD), for example, a power voltage, is provided. The second power wire (M1_R2) may be a path through which the source voltage (VSS), for example, a ground voltage, is provided.

A single height cell (SHC) may be defined between the first power wire (M1_R1) and the second power wire (M1_R2). A single height cell (SHC) may include one PMOSFET region (PR) and one NMOSFET region (NR). In other words, the single height cell (SHC) may have a CMOS structure provided between the first power wire (M1_R1) and the second power wire (M1_R2).

Each of the PMOSFET region PR and the NMOSFET region NR may have a first width W1 in the first direction D1. The length of the single height cell (SHC) in the first direction (D1) may be defined as the first height (HE1). The first height HE1 may be substantially equal to the distance (eg, pitch) between the first power wire M1_R1 and the second power wire M1_R2.

A single height cell (SHC) can constitute one logic cell. In this specification, a logic cell may refer to a logic element (eg, AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, a logic cell may include transistors for configuring a logic element and wires connecting the transistors to each other.

Referring to FIG. 2, a double height cell (DHC) may be provided. Specifically, a first power wire (M1_R1), a second power wire (M1_R2), and a third power wire (M1_R3) may be provided on the substrate 100. The first power wire (M1_R1) may be disposed between the second power wire (M1_R2) and the third power wire (M1_R3). The third power wiring (M1_R3) may be a path through which the drain voltage (VDD) is provided.

A double height cell (DHC) may be defined between the second power wire (M1_R2) and the third power wire (M1_R3). The double height cell DHC may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

The first NMOSFET region NR1 may be adjacent to the second power wire M1_R2. The second NMOSFET region NR2 may be adjacent to the third power wire M1_R3. The first and second PMOSFET regions PR1 and PR2 may be adjacent to the first power wire M1_R1. From a plan view, the first power line M1_R1 may be disposed between the first and second PMOSFET regions PR1 and PR2.

The length of the double height cell (DHC) in the first direction (D1) may be defined as the second height (HE2). The second height HE2 may be approximately twice the first height HE1 of FIG. 1 . The first and second PMOSFET regions PR1 and PR2 of the double height cell (DHC) may be bundled to operate as one PMOSFET region.

Accordingly, the channel size of the PMOS transistor of the double height cell (DHC) may be larger than the channel size of the PMOS transistor of the single height cell (SHC) of FIG. 1. For example, the channel size of the PMOS transistor of a double height cell (DHC) may be approximately twice that of the PMOS transistor of a single height cell (SHC). As a result, double height cells (DHC) can operate at higher speeds compared to single height cells (SHC). In the present invention, the double height cell (DHC) shown in FIG. 2 may be defined as a multi-height cell. Although not shown, a multi-height cell may include a triple-height cell whose cell height is approximately three times that of a single-height cell (SHC).

Referring to FIG. 3, a first single height cell (SHC1), a second single height cell (SHC2), and a double height cell (DHC) may be two-dimensionally arranged on the substrate 100. The first single height cell SHC1 may be disposed between the first and second power wires M1_R1 and M1_R2. The second single height cell SHC2 may be disposed between the first and third power wires M1_R1 and M1_R3. The second single height cell SHC2 may be adjacent to the first single height cell SHC1 in the first direction D1.

The double height cell (DHC) may be disposed between the second and third power wires (M1_R2 and M1_R3). The double height cell (DHC) may be adjacent to the first and second single height cells (SHC1 and SHC2) in the second direction (D2).

A separation structure DB may be provided between the first single height cell SHC1 and the double height cell DHC, and between the second single height cell SHC2 and the double height cell DHC. By the separation structure DB, the active area of the double height cell DHC may be electrically separated from the active areas of each of the first and second single height cells SHC1 and SHC2.

Figure 4 is a plan view for explaining a semiconductor device according to embodiments of the present invention. FIGS. 5A to 5E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of FIG. 4, respectively.

The semiconductor device shown in FIGS. 4 and 5A to 5E is an example that represents the first and second single height cells SHC1 and SHC2 of FIG. 3 in more detail.

Referring to FIGS. 4 and 5A to 5E , first and second single height cells SHC1 and SHC2 may be provided on the substrate 100 . Logic transistors constituting a logic circuit may be disposed on each of the first and second single height cells SHC1 and SHC2. The substrate 100 may be a semiconductor substrate containing silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. As an example, the substrate 100 may be a silicon substrate.

The substrate 100 may have a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. Each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may be an active region. Each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may extend in the second direction D2.

The first active pattern AP1 and the second active pattern AP2 may be defined by the trench TR formed on the upper part of the substrate 100 . The first active pattern AP1 may be provided on each of the first and second PMOSFET regions PR1 and PR2. The second active pattern AP2 may be provided on each of the first and second NMOSFET regions NR1 and NR2. The first and second active patterns AP1 and AP2 may extend in the second direction D2. The first and second active patterns AP1 and AP2 are part of the substrate 100 and may be vertically protruding parts.

The device isolation layer (ST) may fill the trench (TR). The device isolation layer (ST) may include a silicon oxide layer. The device isolation layer ST may not cover the first and second channel patterns CH1 and CH2, which will be described later.

A first channel pattern (CH1) may be provided on the first active pattern (AP1). A second channel pattern (CH2) may be provided on the second active pattern (AP2). Each of the first channel pattern (CH1) and the second channel pattern (CH2) may include a first semiconductor pattern (SP1), a second semiconductor pattern (SP2), and a third semiconductor pattern (SP3) sequentially stacked. . The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in the vertical direction (ie, the third direction D3).

Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Preferably, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon.

A plurality of first source/drain patterns SD1 may be provided on the first active pattern AP1. A plurality of first recesses RS1 may be formed on the first active pattern AP1. First source/drain patterns SD1 may be provided in each of the first recesses RS1. The first source/drain patterns SD1 may be impurity regions of a first conductivity type (eg, p-type). A first channel pattern (CH1) may be interposed between a pair of first source/drain patterns (SD1). In other words, the stacked first to third semiconductor patterns SP1, SP2, and SP3 may connect a pair of first source/drain patterns SD1 to each other.

A plurality of second source/drain patterns SD2 may be provided on the second active pattern AP2. A plurality of second recesses RS2 may be formed on the second active pattern AP2. Second source/drain patterns SD2 may be provided in each of the second recesses RS2. The second source/drain patterns SD2 may be impurity regions of a second conductivity type (eg, n-type). A second channel pattern (CH2) may be interposed between a pair of second source/drain patterns (SD2). In other words, the stacked first to third semiconductor patterns SP1, SP2, and SP3 may connect a pair of second source/drain patterns SD2 to each other.

The first and second source/drain patterns SD1 and SD2 may be epitaxial patterns formed through a selective epitaxial growth (SEG) process. For example, the top surface of each of the first and second source/drain patterns SD1 and SD2 may be located at substantially the same level as the top surface of the third semiconductor pattern SP3. As another example, the top surface of each of the first and second source/drain patterns SD1 and SD2 may be higher than the top surface of the third semiconductor pattern SP3.

The first source/drain patterns SD1 may include a semiconductor element (eg, SiGe) having a lattice constant greater than the lattice constant of the semiconductor element of the substrate 100 . Accordingly, the pair of first source/drain patterns SD1 may provide compressive stress to the first channel pattern CH1 between them. The second source/drain patterns SD2 may include the same semiconductor element (eg, Si) as that of the substrate 100 .

Gate electrodes GE may be provided crossing the first and second channel patterns CH1 and CH2 and extending in the first direction D1. The gate electrodes GE may be arranged in the second direction D2 according to the first pitch. Each of the gate electrodes GE may vertically overlap the first and second channel patterns CH1 and CH2. The gate electrodes GE may include first to fourth gate electrodes GE1 to GE4 sequentially arranged in the second direction D2.

The gate electrode GE includes a first portion PO1 interposed between the substrate 100 and the first semiconductor pattern SP1, and a first portion PO1 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. Includes two parts (PO2), a third part (PO3) sandwiched between the second semiconductor pattern (SP2) and the third semiconductor pattern (SP3), and a fourth part (PO4) on the third semiconductor pattern (SP3) can do.

Referring again to FIG. 5E, the gate electrode GE is formed on the top surface TS, bottom surface BS, and both side surfaces SW1, SW2 of each of the first to third semiconductor patterns SP1, SP2, and SP3. can be provided. In other words, the transistor of the logic cell LC according to this embodiment may be a three-dimensional field effect transistor (eg, MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

Referring again to FIGS. 4 and 5A to 5E , the first single height cell SHC1 may have a first border BD1 and a second border BD2 facing each other in the second direction D2. The first and second boundaries BD1 and BD2 may extend in the first direction D1. The first single height cell SHC1 may have a third border BD3 and a fourth border BD4 facing each other in the first direction D1. The third and fourth boundaries BD3 and BD4 may extend in the second direction D2.

Gate cutting patterns CT may be disposed on boundaries parallel to the second direction D2 of each of the first and second single height cells SHC1 and SHC2. For example, gate cutting patterns CT may be disposed on the third and fourth boundaries BD3 and BD4 of the first single height cell SHC1. The gate cutting patterns CT may be arranged at the first pitch along the third boundary BD3. The gate cutting patterns CT may be arranged at the first pitch along the fourth boundary BD4. From a plan view, the gate cutting patterns CT on the third and fourth boundaries BD3 and BD4 may be arranged to overlap each other on the gate electrodes GE.

Referring to FIG. 5E , the gate cutting pattern CT may extend from the device isolation layer ST to the second interlayer insulating layer 120 in the third direction D3. The top surface of the gate cutting pattern (CT) may be higher than the top surface of the gate electrode (GE). The top surface of the gate cutting pattern (CT) may be substantially coplanar with the top surface of the gate capping pattern (GP). The gate cutting pattern (CT) may include an insulating material such as a silicon nitride film, a silicon oxide film, or a combination thereof.

The gate electrode GE on the first single height cell SHC1 may be separated from the gate electrode GE on the second single height cell SHC2 by a gate cutting pattern CT. A gate cutting pattern (CT) is interposed between the gate electrode (GE) on the first single height cell (SHC1) and the gate electrode (GE) on the second single height cell (SHC2) aligned in the first direction (D1). It can be. In other words, the gate electrode GE extending in the first direction D1 may be separated into a plurality of gate electrodes GE by the gate cutting patterns CT.

Referring again to FIGS. 4 and 5A to 5E , a pair of gate spacers GS may be disposed on both side walls of the fourth portion PO4 of the gate electrode GE. The gate spacers GS may extend in the first direction D1 along the gate electrode GE. The top surfaces of the gate spacers GS may be higher than the top surfaces of the gate electrode GE. The top surfaces of the gate spacers GS may be coplanar with the top surface of the first interlayer insulating film 110, which will be described later. Gate spacers GS may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacers GS may include a multi-layer made of at least two of SiCN, SiCON, and SiN.

A gate capping pattern (GP) may be provided on the gate electrode (GE). The gate capping pattern GP may extend in the first direction D1 along the gate electrode GE. The gate capping pattern GP may include a material that has etch selectivity with respect to the first and second interlayer insulating films 110 and 120, which will be described later. Specifically, the gate capping patterns GP may include at least one of SiON, SiCN, SiCON, and SiN.

A gate insulating layer GI may be interposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may cover the top surface TS, bottom surface BS, and both side surfaces SW1 and SW2 of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may cover the top surface of the device isolation layer ST below the gate electrode GE (see FIG. 5E).

In one embodiment of the present invention, the gate insulating film GI may include a silicon oxide film, a silicon oxynitride film, and/or a high-k dielectric film. The high dielectric film may include a high dielectric constant material that has a higher dielectric constant than the silicon oxide film. As an example, the high dielectric constant material includes hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, and strontium titanium. oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In another embodiment, the semiconductor device of the present invention may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric material layer with ferroelectric properties and a paraelectric material layer with paraelectric properties.

The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance will be less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

When a ferroelectric material film with a negative capacitance and a paraelectric material film with a positive capacitance are connected in series, the overall capacitance value of the ferroelectric material film and the paraelectric material film connected in series may increase. By taking advantage of the increase in overall capacitance value, a transistor including a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV/decade at room temperature.

A ferroelectric material film may have ferroelectric properties. Ferroelectric material films include, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium oxide. titanium oxide). Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

The ferroelectric material film may further include a doped dopant. For example, dopants include aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), and cerium (Ce). ), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on what kind of ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film is, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). It can be included.

When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% of silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% of zirconium.

A paradielectric material film may have paradielectric properties. For example, the paradielectric material film may include at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paradielectric material film may include, but is not limited to, at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide.

The ferroelectric material film and the paraelectric material film may include the same material. A ferroelectric material film may have ferroelectric properties, but a paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

The ferroelectric material film may have a thickness having ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness representing ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

As an example, the gate insulating layer GI may include one ferroelectric material layer. As another example, the gate insulating layer GI may include a plurality of ferroelectric material layers spaced apart from each other. The gate insulating film GI may have a stacked structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

The first gate electrode GE1 may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on the gate insulating layer GI and adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal that adjusts the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, the desired threshold voltage of the transistor can be achieved. For example, the first to third portions PO1, PO2, and PO3 of the first gate electrode GE1 may be composed of a first metal pattern that is a work function metal.

The first metal pattern may include a metal nitride film. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). You can. Furthermore, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal films.

The second metal pattern may include a metal with lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion PO4 of the first gate electrode GE1 may include a first metal pattern and a second metal pattern on the first metal pattern.

Referring again to FIG. 5B, inner spacers IP may be provided on the first and second NMOSFET regions NR1 and NR2. The inner spacers IP may be interposed between the first to third portions PO1, PO2, and PO3 of the first gate electrode GE1 and the second source/drain pattern SD2, respectively. The inner spacers IP may directly contact the second source/drain pattern SD2. Each of the first to third portions PO1, PO2, and PO3 of the first gate electrode GE1 may be spaced apart from the second source/drain pattern SD2 by the inner spacer IP.

A first interlayer insulating film 110 may be provided on the substrate 100. The first interlayer insulating film 110 may cover the gate spacers GS and the first and second source/drain patterns SD1 and SD2. The top surface of the first interlayer insulating film 110 may be substantially coplanar with the top surface of the gate capping pattern GP and the top surface of the gate spacer GS. A second interlayer insulating film 120 may be disposed on the first interlayer insulating film 110 to cover the gate capping pattern GP. A third interlayer insulating film 130 may be provided on the second interlayer insulating film 120. A fourth interlayer insulating film 140 may be provided on the third interlayer insulating film 130. As an example, the first to fourth interlayer insulating films 110 - 140 may include a silicon oxide film.

A pair of separation structures DB facing each other in the second direction D2 may be provided on both sides of each of the first and second single height cells SHC1 and SHC2. For example, a pair of separation structures DB may be provided on the first and second boundaries BD1 and BD2 of the first single height cell SHC1, respectively. The separation structure DB may extend parallel to the first gate electrodes GE1 in the first direction D1. The pitch between the separation structure DB and the first gate electrode GE1 adjacent thereto may be the same as the first pitch.

The separation structure DB may extend through the first and second interlayer insulating films 110 and 120 and into the first and second active patterns AP1 and AP2. The separation structure DB may penetrate the upper portion of each of the first and second active patterns AP1 and AP2. The separation structure DB may electrically separate the active area of each of the first and second single height cells SHC1 and SHC2 from the active area of another adjacent cell.

Active contacts AC may be provided through the first and second interlayer insulating films 110 and 120 and electrically connected to the first and second source/drain patterns SD1 and SD2, respectively. A pair of active contacts AC may be provided on both sides of the first gate electrode GE1, respectively. From a plan view, the active contact AC may have a bar shape extending in the first direction D1.

The active contact (AC) may be a self-aligned contact. In other words, the active contact AC can be formed in a self-aligned manner using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of the sidewall of the gate spacer GS. Although not shown, the active contact AC may cover a portion of the top surface of the gate capping pattern GP.

Silicide patterns SC may be interposed between the active contact AC and the first source/drain pattern SD1 and between the active contact AC and the second source/drain pattern SD2, respectively. The active contact (AC) may be electrically connected to the source/drain patterns (SD1 and SD2) through the silicide pattern (SC). The silicide pattern (SC) may include metal-silicide, for example, at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide. .

Referring to FIG. 5D, at least one active contact (AC) on the first single height cell (SHC1) is connected to the first source/drain pattern (SD1) of the first PMOSFET region (PR1) and the first NMOSFET region (NR1). The second source/drain patterns SD2 may be electrically connected to each other. The active contact AC extends in a first direction D1 from the second source/drain pattern SD2 of the first NMOSFET region NR1 to the first source/drain pattern SD1 of the first PMOSFET region PR1. It may be extended. The active contact AC may include a first body part BP1 on the first source/drain pattern SD1 and a second body part BP2 on the second source/drain pattern SD2. The first body BP1 may be connected to the top surface of the first source/drain pattern SD1 through the silicide pattern SC, and the second body BP2 may be connected to the second source/drain pattern SD1 through the silicide pattern SC. It may be connected to the top surface of the drain pattern (SD2). The first active contact AC1 may further include a protrusion PRP interposed between the first body BP1 and the second body BP2. The protrusion PRP may be provided on the device isolation layer ST between the first PMOSFET region PR1 and the first NMOSFET region NR1.

The protrusion PRP may extend from the first body BP1 along the inclined sidewall of the first source/drain pattern SD1 toward the device isolation layer ST. The protrusion PRP may extend from the second body BP2 along the inclined sidewall of the second source/drain pattern SD2 toward the device isolation layer ST. The bottom surface of the protrusion PRP may be lower than the bottom surfaces of each of the first body BP1 and the second body BP2. The bottom surface of the protrusion (PRP) may be located higher than the device isolation layer (ST). In other words, the protrusion PRP may be spaced apart from the device isolation layer ST with the first interlayer insulating layer 110 interposed therebetween.

According to an embodiment of the present invention, the active contact AC is not only connected to the top surface of the first source/drain pattern SD1 through the first body BP1, but also connected to the first source/drain pattern SD1 through the protrusion PRP. It can also be connected to the inclined sidewall of the drain pattern (SD1). In other words, the protrusion PRP may increase the contact area between the active contact AC and the first source/drain pattern SD1. Accordingly, the resistance between the active contact (AC) and the first source/drain pattern (SD1) may be reduced. Likewise, the protrusion PRP may reduce resistance between the active contact AC and the second source/drain pattern SD2. As a result, the operating speed of semiconductor devices according to embodiments of the present invention can be improved.

Gate contacts GC may be provided through the second interlayer insulating layer 120 and the gate capping pattern GP and electrically connected to the first gate electrodes GE1, respectively. From a plan view, the gate contacts GC on the first single height cell SHC1 may be arranged to overlap the first PMOSFET region PR1. In other words, the gate contacts GC on the first single height cell SHC1 may be provided on the first active pattern AP1 (see FIG. 5A).

The gate contact GC may be freely disposed on the first gate electrode GE1 without location restrictions. For example, the gate contacts GC on the second single height cell SHC2 are on the device isolation layer ST filling the second PMOSFET region PR2, the second NMOSFET region NR2, and the trench TR. Each can be arranged (see Figure 4).

In one embodiment of the present invention, referring to FIGS. 5A and 5C, the upper portion of the active contact (AC) adjacent to the gate contact (GC) may be filled with the upper insulating pattern (UIP). The bottom surface of the upper insulating pattern (UIP) may be lower than the bottom surface of the gate contact (GC). In other words, the top surface of the active contact (AC) adjacent to the gate contact (GC) may be lowered than the bottom surface of the gate contact (GC) by the upper insulating pattern (UIP). As a result, it is possible to prevent a short circuit occurring when the gate contact (GC) contacts the adjacent active contact (AC).

Each of the active contact (AC) and the gate contact (GC) may include a conductive pattern (FM) and a barrier pattern (BM) surrounding the conductive pattern (FM). For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal film/metal nitride film. The metal film may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

A first metal layer M1 may be provided in the third interlayer insulating film 130. For example, the first metal layer M1 may include a first power wire M1_R1, a second power wire M1_R2, a third power wire M1_R3, and first wires M1_I. Each of the wires M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1 may extend parallel to each other in the second direction D2.

Specifically, the first and second power wires M1_R1 and M1_R2 may be provided on the third and fourth boundaries BD3 and BD4 of the first single height cell SHC1, respectively. The first power wire M1_R1 may extend in the second direction D2 along the third boundary BD3. The second power wire M1_R2 may extend in the second direction D2 along the fourth boundary BD4.

The first wires M1_I of the first metal layer M1 may be arranged along the first direction D1 at a second pitch. The second pitch may be smaller than the first pitch. The line width of each of the first wires (M1_I) may be smaller than the line width of each of the first to third power wires (M1_R1, M1_R2, and M1_R3).

The first metal layer M1 may further include first vias VI1. The first vias VI1 may be provided under the wires M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1, respectively. The wiring of the active contact AC and the first metal layer M1 may be electrically connected to each other through the first via VI1. The gate contact GC and the wiring of the first metal layer M1 may be electrically connected to each other through the first via VI1.

The wiring of the first metal layer M1 and the first via VI1 below it may be formed through separate processes. In other words, each of the wiring of the first metal layer M1 and the first via VI1 may be formed through a single damascene process. The semiconductor device according to this embodiment may be formed using a process of less than 20 nm.

A second metal layer M2 may be provided in the fourth interlayer insulating film 140. The second metal layer M2 may include a plurality of second wires M2_I. Each of the second wires M2_I of the second metal layer M2 may have a line shape or a bar shape extending in the first direction D1. In other words, the second wires M2_I may extend parallel to each other in the first direction D1.

The second metal layer M2 may further include second vias VI2 respectively provided below the second wires M2_I. The wiring of the first metal layer M1 and the wiring of the second metal layer M2 may be electrically connected to each other through the second via VI2. The wiring of the second metal layer (M2) and the second via (VI2) below it may be formed together through a dual damascene process.

The wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include the same or different conductive materials. For example, the wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, and cobalt. Although not shown, metal layers (eg, M3, M4, M5...) stacked on the fourth interlayer insulating film 140 may be additionally disposed. Each of the stacked metal layers may include wires for routing between cells.

6 to 21C, the method for manufacturing a semiconductor device according to the present invention will be described in more detail.

6 to 21C are diagrams for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 6, 8, 10, 14, 16, and 20 are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 6 , a substrate 100 having a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2 may be provided. The first NMOSFET region (NR1) and the first PMOSFET region (PR1) may define a first single height cell (SHC1), and the second NMOSFET region (NR2) and the second PMOSFET region (PR2) may define a second single height cell (SHC1). A height cell (SHC2) can be defined.

Sacrificial layers (SAL) and active layers (ACL) may be formed on the substrate 100 to be alternately stacked. The sacrificial layers (SAL) may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the active layers (ACL) may include silicon (Si), germanium (Ge), and It may include another one of silicon-germanium (SiGe).

For example, the sacrificial layers SAL may include silicon-germanium (SiGe), and the active layers ACL may include silicon (Si). The concentration of germanium (Ge) in each of the sacrificial layers (SAL) may be 10 at% to 30 at%.

Mask patterns may be formed on the first and second active regions AR1 and AR2 of the substrate 100, respectively. The mask pattern may have a line shape or a bar shape extending in the first direction D1.

By performing a patterning process using the mask patterns as an etch mask, a trench TR defining the first active pattern AP1 and the second active pattern AP2 may be formed. First active patterns AP1 may be formed on each of the first and second PMOSFET regions PR1 and PR2. Second active patterns AP2 may be formed on each of the first and second NMOSFET regions NR1 and NR2.

A device isolation layer (ST) may be formed to fill the trench (TR). Specifically, an insulating film may be formed on the entire surface of the substrate 100 to cover the first to third active patterns AP1 - AP3 and the stacked patterns STP. A device isolation layer (ST) may be formed by recessing the insulating layer until the stacking patterns (STP) are exposed. The device isolation film (ST) may include an insulating material such as a silicon oxide film. The stacking patterns (STP) may be exposed on the device isolation layer (ST). In other words, the stacked patterns STP may protrude vertically above the device isolation layer ST.

FIGS. 6, 7A, and 7B are diagrams for explaining a method of forming sacrificial patterns PP. FIGS. 7A and 7B are cross-sectional views taken along lines A-A' and B-B' of FIG. 6, respectively.

Referring to FIG. 6, a first sacrificial layer (PPL) may be formed on the entire surface of the substrate 100. Referring to FIGS. 7A and 7B , the first sacrificial layer (PPL) may be formed on the device isolation layer (ST) and the stacking patterns (STP). Mask patterns MP may be formed on the first sacrificial layer.

9A and 9B are cross-sectional views taken along lines A-A' and B-B' of FIG. 8, respectively.

Referring to FIGS. 8, 9A, and 9B, the first sacrificial layer PPL may be patterned using the mask patterns MP as an etch mask to form a plurality of sacrificial patterns PP. The first sacrificial layer (PPL) may include polysilicon. The sacrificial patterns PP may be formed in a line shape or a bar shape extending in the first direction D1.

FIGS. 11A and 11B are cross-sectional views taken along line A-A' of FIG. 10. Figure 11b is a cross-sectional view according to other embodiments of the present invention. Figure 12 is an enlarged view of area M of Figure 11a.

Referring to FIGS. 11A and 12 , both side walls PSW1 and PSW2 of the sacrificial pattern PP may be nitrided to form a nitrided pattern NP. The side walls PSW1 and PSW2 may face each other in the second direction D2. The upper portion of the nitride pattern NP may have a first width W1 in the second direction D2. The lower portion of the nitride pattern NP may have a second width W2 in the second direction D2. The second width W2 may be larger than the first width W1 (see FIG. 12). The second width W2 may be 1.5 to 3 times the first width W1. In another embodiment, the nitride pattern (NP) may also be formed on the device isolation layer (ST) and the mask pattern (MP) (see FIG. 11b).

Referring to FIG. 12 , the width of the nitride pattern NP in the second direction D2 may increase from top to bottom. The cross section of each nitride pattern (NP) may have a triangular or trapezoidal profile. The sacrificial pattern PP may have a third width in the second direction D2. The third width may decrease as it gets closer to the substrate. Accordingly, the sum of the width of the nitride pattern (NP) and the widths of the sacrificial patterns (PP) formed on both sides of the nitride pattern (NP) may be constant at any height.

Specifically, forming the nitride pattern (NP) includes oxidizing the surfaces of both side walls of the sacrificial pattern (PP), and depositing nitrogen on the surface of the oxidized sacrificial pattern (PP) to form silicon nitride (Silicon nitride). It may include forming nitride, Si ₃ N ₄ ). At this time, the concentration of nitrogen deposited on the lower part of the sacrificial pattern (PP) may be higher than the concentration of nitrogen deposited on the upper part of the sacrificial pattern (PP). Accordingly, the concentration of nitrogen may increase from the top to the bottom of the nitride pattern (NP). This can prevent the lower part of the sacrificial pattern PP from being etched more than the upper part by the etching process to be described later.

Referring to FIGS. 13A and 13B , after forming the nitride pattern (NP), a gate spacer (GS) may be formed on the nitride pattern (NP). Forming the gate spacers GS may include conformally forming a gate spacer film on the front surface of the substrate 100 and anisotropically etching the gate spacer film. The gate spacer film may include at least one of SiCN, SiCON, and SiN.

Referring to FIG. 13A , the bottom surface of the sacrificial pattern PP may be located at the first level LV1. Referring to FIG. 13B , the bottom surface of the sacrificial pattern PP on the stacking pattern STP may be located at the second level LV2. The second level (LV2) may be higher than the first level (LV1). Referring again to FIG. 12, the width of the nitride pattern NP at the second level LV2 may be smaller than the width at the first level LV1. On the other hand, the width of the sacrificial pattern PP at the second level LV2 may be larger than the width at the first level LV1. Accordingly, the sum of the width of the nitride pattern (NP) and the width of the sacrificial pattern (PP) may be the same in the first and second levels (LV1 and LV2).

FIGS. 15A to 15D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of FIG. 14, respectively.

First recesses RS1 may be formed in the stacking pattern STP on the first active area AP1. Second recesses RS2 may be formed in the stacked pattern STP on the second active area AP2. While forming the first and second recesses RS1 and RS2, the device isolation layer ST on both sides of each of the first and second active regions AP1 and AP2 may be further recessed (FIG. 15a).

Specifically, the first recesses RS1 may be formed by etching the stacking pattern STP on the first active area AP1 using the hard mask patterns MP and the gate spacers GS as an etch mask. there is. The first recess RS1 may be formed between a pair of sacrificial patterns PP. The second recesses RS2 in the stacked pattern STP on the second active area AP2 may be formed in the same manner as the first recesses RS1.

From the active layers ACL, first to third semiconductor patterns SP1, SP2, and SP3 may be formed sequentially stacked between adjacent first recesses RS1. From the active layers ACL, first to third semiconductor patterns SP1, SP2, and SP3 may be formed sequentially between adjacent second recesses RS2. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1 may form a first channel pattern CH1. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent second recesses RS2 may form a second channel pattern CH2.

Referring to FIG. 15B , first source/drain patterns SD1 may be formed within the first recesses RS1, respectively. Specifically, a first selective epitaxial growth process (i.e., a first SEG process) is performed using the inner wall of the first recess (RS1) as a seed layer to form a first source/drain pattern (SD1). This can be formed. The first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

The first source/drain pattern SD1 may include a semiconductor element (eg, SiGe) having a lattice constant greater than the lattice constant of the semiconductor element of the substrate 100 . During the first SEG process, impurities may be injected in-situ. As another example, after the first source/drain pattern SD1 is formed, impurities may be injected into the first source/drain pattern SD1. The first source/drain pattern SD1 may be doped to have a first conductivity type (eg, p-type).

Second source/drain patterns SD2 may be formed in the second recesses RS2, respectively. Specifically, the second source/drain pattern SD2 may be formed by performing a second SEG process using the inner wall of the second recess RS2 as a seed layer. For example, the second source/drain pattern SD2 may include the same semiconductor element (eg, Si) as that of the substrate 100 . The second source/drain pattern SD2 may be doped to have a second conductivity type (eg, n-type). Inner spacers IP may be formed between the second source/drain pattern SD2 and the sacrificial layers SAL, respectively.

FIGS. 17A to 17C are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 16, respectively.

16 and 17A to 17C, the first interlayer insulating film 110 covers the first and second source/drain patterns SD1 and SD2, hard mask patterns MP, and gate spacers GS. ) can be formed. As an example, the first interlayer insulating film 110 may include a silicon oxide film. The first interlayer insulating layer 110 may be planarized until the top surfaces of the sacrificial patterns PP are exposed. Planarization of the first interlayer insulating film 110 may be performed using an etch back or chemical mechanical polishing (CMP) process. During the planarization process, all hard mask patterns MP may be removed.

FIGS. 18A and 18B are diagrams showing an etching process performed after the process shown in FIGS. 17A and 17B, respectively. FIGS. 19A and 19B are enlarged views of area N of FIG. 18A.

Referring to FIGS. 18A and 18B , the exposed sacrificial pattern PP may be selectively removed. The outer region (ORG) can be formed by removing the sacrificial pattern (PP). Referring to FIG. 19B, the outer region ORG may have a fourth width W4 in the second direction D2. The fourth width may be constant in the third direction D3.

Specifically, the process of removing the sacrificial pattern PP may be performed through a first etching process and a second etching process. The first etching process may be wet etching. By the first etching process, part of the sacrificial pattern (PP) and the nitride pattern (NP) may be removed. In the first etching process, the etch rate for the nitride pattern (NP) may be less than the etch rate for the sacrificial pattern (PP). That is, the nitride pattern (NP) may have higher etching resistance than the sacrificial pattern (PP) in the first etching process. Accordingly, a portion of the lower portion of the nitride pattern NP may not be removed after the first etching process (see FIG. 19A).

By removing the sacrificial pattern PP, sacrificial layers SAL may be exposed. Exposed sacrificial layers (SAL) may be selectively removed by a second etching process. The second etching process may be wet etching. The etching material used in the etching process can quickly remove the sacrificial layer (SAL) having a relatively high germanium concentration.

Referring to FIG. 19B, the nitride pattern NP that is not removed by the first etching process may be removed by the second etching process. Accordingly, after the first etching process and the second etching process, the fourth width W4 of the outer region ORG may be constant at any height.

FIGS. 21A to 21C are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 20, respectively.

Referring to FIGS. 20 and 21A to 21C , a gate insulating film (GI) and a gate electrode (GE) may be sequentially formed in the outer region (ORG). The gate insulating layer GI may surround the first to third semiconductor patterns SP1, SP2, and SP3.

When the nitride pattern (NP) is not formed or the width of the nitride pattern (NP) is constant, while performing the first and second etching processes, the lower part of the outer region (ORG) may be formed to be wider than the upper part. there is. That is, the width of the outer region ORG may not be constant in the third direction D3 due to multiple etching processes. When the width of the outer region ORG is not constant, the width of the gate electrode GE filling the outer region ORG may be larger at the bottom than at the top. Additionally, the gate electrode GE may not be completely filled and an empty space may be formed. When forming a gate cutting pattern (CT), which will be described later, the gate electrode (GE) is etched and then filled with an insulating material. At this time, the entire lower portion of the gate electrode (GE) may not be etched. As a result, a portion of the lower part of the gate electrode GE is not removed, which may cause process defects.

On the other hand, by forming the lower part of the nitride pattern (NP) to be wider than the upper part, the width of the outer region (ORG) can be formed to be constant even after the first and second etching processes. As a result, the outer region ORG can be filled with the gate electrode GE without any empty space. Additionally, before forming the gate cutting pattern CT, the entire gate electrode GE may be etched. As a result, process defects in semiconductor devices can be prevented and reliability improved.

Referring to FIGS. 20 and 21A , gate cutting patterns CT may be disposed on boundaries parallel to the second direction D2 of each of the first and second single height cells SHC1 and SHC2. Specifically, forming the gate cutting patterns CT may include etching the cutting area of the gate electrode GE and filling the cutting area with an insulating material. The cutting area may be located at a boundary between a first single height cell and a second single height cell. Since the width of the gate electrode GE is the same at the bottom and top, all of the gate electrode GE can be removed from the cutting area.

A second interlayer insulating film 120 may be formed on the gate cutting patterns CT and the first interlayer insulating film 110. The second interlayer insulating film 120 may include a silicon oxide film. Active contacts AC may be formed through the second interlayer insulating film 120 and the first interlayer insulating film 110 and electrically connected to the first and second source/drain patterns SD1 and SD2. A gate contact GC may be formed that penetrates the second interlayer insulating layer 120 and the gate capping pattern GP and is electrically connected to the gate electrode GE.

Forming each active contact (AC) and gate contact (GC) may include forming a barrier pattern (BM) and forming a conductive pattern (FM) on the barrier pattern (BM). The barrier pattern BM may be formed conformally and may include a metal film/metal nitride film. The conductive pattern (FM) may include a low-resistance metal.

A pair of separation structures DB may be formed on both sides of the logic cell LC. The separation structure DB may extend from the second interlayer insulating film 120 through the gate electrode GE into the active pattern AP1 or AP2. The separation structure DB may include an insulating material such as a silicon oxide film or a silicon nitride film.

A third interlayer insulating layer 130 may be formed on the active contacts AC and the gate contacts GC. A first metal layer M1 may be formed in the third interlayer insulating film 130. A fourth interlayer insulating film 140 may be formed on the third interlayer insulating film 130. A second metal layer M2 may be formed in the fourth interlayer insulating film 140.

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention may be implemented in other specific forms without changing the technical idea or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims (10)

Forming a stacking pattern on a substrate, the stacking pattern including active layers and sacrificial layers alternately stacked with each other;
forming a sacrificial pattern extending in a first direction on the stacked pattern;
forming a nitrided pattern by nitriding both side walls of the sacrificial pattern;
etching the stacked pattern using the sacrificial pattern as a mask to form a recess in the stacked pattern, wherein the active layers include a plurality of semiconductor patterns exposed by the recess;
forming a source/drain pattern filling the recess;
removing the sacrificial pattern, the nitride pattern, and the sacrificial layers to expose the plurality of semiconductor patterns;
forming a gate insulating film on the exposed plurality of semiconductor patterns; and
Including forming a gate electrode on the gate insulating film,
The upper portion of the nitrided pattern has a first width in a second direction,
A lower portion of the nitrided pattern has a second width in the second direction,
A method of manufacturing a semiconductor device wherein the second width is greater than the first width. According to claim 1,
The method of manufacturing a semiconductor device wherein the second width is 1.5 to 3 times the first width. According to claim 1,
A method of manufacturing a semiconductor device in which the width of the nitride pattern increases from top to bottom. According to claim 1,
A method of manufacturing a semiconductor device in which the nitrogen concentration of the nitride pattern increases from top to bottom. According to claim 1,
Forming the nitrided pattern is:
oxidizing the surfaces of both side walls of the sacrificial pattern; and
A method of manufacturing a semiconductor device comprising forming silicon nitride by depositing nitrogen on the oxidized surface. According to claim 1,
the sacrificial pattern has a third width in the second direction,
A method of manufacturing a semiconductor device wherein the third width decreases as it gets closer to the substrate. According to claim 1,
After forming the nitride pattern, the method of manufacturing a semiconductor device further includes forming a gate spacer on the nitride pattern. According to claim 1,
The sacrificial pattern is removed to form an outer region,
the outer region has a fourth width in the second direction,
The fourth method of manufacturing a semiconductor device having a constant width. According to claim 1,
The substrate includes a first logic cell and a second logic cell,
The second logic cell is adjacent to the first logic cell in the first direction,
A method of manufacturing a semiconductor device further comprising forming a gate cutting pattern at a boundary between the second logic cell and the first logic cell. According to claim 1,
A method of manufacturing a semiconductor device in which the nitride pattern is also formed on the device isolation layer and the mast pattern.

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