KR20240055612A - Electronic device and the method to calibration offset voltage - Google Patents

Abstract

An electronic device that performs offset calibration in an AFE circuit according to the technical idea of the present disclosure includes a plurality of modules included in the AFE circuit and at least one processor, wherein the at least one processor includes firmware. Provides a user interface for updating, determines a target module to perform offset calibration among the plurality of modules based on user input to the user interface, and determines a common mode voltage when performing calibration on the target module. It is possible to determine the location where voltage is applied, and determine a calibration sequence including the target module and the location where the common mode voltage is applied.

Description

Electronic device and offset calibration method {ELECTRONIC DEVICE AND THE METHOD TO CALIBRATION OFFSET VOLTAGE}

The technical idea of the present disclosure relates to an electronic device, and more specifically, to a method for an electronic device to perform offset calibration.

An analog front end (AFE) is a block for digitizing analog signals in a digital system for processing analog signals into digital signals. It refers to a circuit that integrates an analog pre-processing circuit and an analog-to-digital converter on one chip. The AFE circuit may include a plurality of modules (or amplifiers) for digitizing analog signals. Each module may have an offset due to interactions between elements included in the module. Because offsets cause problems in the operation of semiconductors, technologies for calibrating offsets are being researched.

The technical idea of the present disclosure provides a method for calibrating an offset using an electronic device.

According to the technical idea of the present disclosure, an electronic device that performs offset calibration in an AFE circuit includes a plurality of modules included in the AFE circuit and at least one processor, wherein the at least one processor includes: Provides a user interface for firmware update, determines a target module to perform offset calibration among the plurality of modules based on user input to the user interface, and determines a common mode voltage (common) when performing calibration on the target module. mode voltage) can be applied, and a calibration sequence including the target module and the common mode voltage can be determined.

According to the technical idea of the present disclosure, a method of performing offset calibration in an AFE circuit includes providing a user interface for firmware update, and based on a user input to the user interface, a plurality of devices included in the AFE circuit. An operation of determining a target module to perform offset calibration among modules, an operation of determining a location where a common mode voltage is applied when performing calibration on the target module, and a location where the target module and the common mode voltage are applied. An operation may be included to determine a calibration sequence including the position.

According to the technical idea of the present disclosure, the AFE circuit for offset calibration includes a CTLE (continuous time linear equalizer) module including an HF module and a VGA (video graphics array) module electrically connected to the HF module, and an electrical circuit connected to the CTLE module. A decision feedback equalizer (DFE) module connected to a DFE module, at least one 1-bit sampler electrically connected to the DFE module, connected to the at least one 1-bit sampler, and converting the input digital code into an analog voltage signal and outputting it. Provides at least one DAC, a user interface for firmware update, and based on a user input to the user interface, a target module to perform offset calibration, a location where a common mode voltage is applied on the AFE circuit, and a digital code search method. It may include a control module that makes decisions.

According to the technical idea of the present disclosure, the electronic device can update the calibration sequence of each module included in the AFE circuit through firmware update. By allowing custom calibration for various modules, it has the effect of minimizing module offset and improving device performance.

1 is a block diagram of an electronic device according to an embodiment of the present disclosure.
2A to 2G are examples of an operation in which an electronic device performs offset calibration on a DFE even module and a module connected to the DFE even module, according to an embodiment of the present disclosure.
FIG. 3 is a diagram illustrating an operation in which an electronic device calibrates a DFE odd module and modules connected to the DFE odd module according to an embodiment of the present disclosure.
FIG. 4 is a diagram for explaining a method of calibrating using another method when the calibration process shown in FIGS. 2 and 3 fails.
FIG. 5 is a diagram illustrating a method by which an electronic device determines a digital code to be input to the DAC of each module according to an embodiment of the present disclosure.
FIG. 6 is a diagram illustrating a system-on-chip including an equalizer according to an embodiment of the present disclosure.
Figure 7 is a flowchart of a method by which an electronic device determines an offset calibration sequence according to an embodiment of the present disclosure.
FIG. 8 is a diagram illustrating how an amplifier included in an electronic device operates according to an embodiment of the present disclosure.

1 is a block diagram of an electronic device according to an embodiment of the present disclosure.

Referring to FIG. 1, the electronic device 100 includes a continuous time linear equalizer (CTLE) 120 including a processor 110, a HF 122, and a video graphic array (VGA) 124. A DFE module 130 (decision feedback equalizer) including a connected DFE odd, a DFE even, at least one 1-bit sampler 140 connected to the DFE module 130, and a DAC 142 connected to the 1-bit sampler 140. ) may include an analog front end (AFE) circuit including.

The DFE module 130 may compensate the signal by applying a weighting value to the detected 1 or 0 signal and feeding it back. The bandwidth of an electrical channel (e.g., a transmission line) may be reduced due to physical effects (e.g., skin effect, dielectric loss, reflections due to impedance discontinuities), and the DFE module 130 may amplify noise or crosstalk. The channel response can be flattened and signal distortion can be reduced. The DFE module 130 can improve driving speed by including a DFE odd that receives signals on odd-numbered clocks and a DFE even that receives signals on even-numbered clocks.

The 1-bit sampler 140 can receive one input signal and output an output signal. The 1-bit sampler 140 may receive one input signal, compare the voltage level of the input signal and the magnitude of the reference voltage, and output the result as an output signal. According to one embodiment, the 1-bit sampler 140 outputs 1V when the voltage level of the input signal is higher than or equal to the reference voltage level, and outputs 0V when the voltage level of the input signal is lower than the reference voltage level. . For example, in the case of a 1-bit sampler with a reference voltage of 0.5V, if the voltage level of the input signal is 1V higher than the reference voltage, 1V can be output, and if the voltage level of the input signal is 0V lower than the reference voltage, 0V can be output. there is. Hereinafter, if the voltage level of the input signal is higher than the reference voltage, 1V will be output, and if the voltage level of the input signal is lower than the reference voltage, 0V will be output. However, the operation of the 1-bit sampler described above is an example, and the operation of the 1-bit sampler 140 in the present invention is not limited thereto. For example, the reference voltage of the 1-bit sampler 140 may have various values, and the value of the output voltage output when the voltage level of the input signal is higher or lower than the reference voltage may also vary.

The electronic device 100 may include a plurality of 1-bit samplers 140. When there are a plurality of 1-bit samplers 140 included in the electronic device 100, each 1-bit sampler 140 may have a different reference voltage. For example, the first reference voltage of the first 1-bit sampler is 0V, the second reference voltage of the second 1-bit sampler is 0.5V, and the third reference voltage of the third 1-bit sampler 140 is 1V. You can. The electronic device 100 applies the same input voltage to the first 1-bit sampler, the second 1-bit sampler, and the third 1-bit sampler, and the first 1-bit sampler, the second 1-bit sampler, and the third The approximate voltage level of the input voltage can be confirmed based on the output voltage of the 1-bit sampler. For example, in response to the same input voltage, the first 1-bit sampler outputs an output voltage of 0V, the second 1-bit sampler outputs an output voltage of 0V, and the third 1-bit sampler outputs an output voltage of 1V, the electronic device 100 The input voltage may be determined to be greater than the second reference voltage and lower than the third reference voltage.

According to one embodiment, the processor 110 may determine an input offset voltage to compensate for the offset included in the 1-bit sampler 140. The 1-bit sampler 140 may include a digital to analog converter (DAC) 142. The DAC 142 can receive a digital code and convert the input digital code into an analog voltage. The processor 110 may determine a digital code based on the output voltage and input the digital code to the DAC 142 to compensate for the offset. The analog voltage (input offset voltage) converted from the digital code by the DAC 142 may be a voltage that compensates for the offset of the corresponding module. Offset refers to the voltage output due to electrical action between resistances inside the module even though the input voltage is 0V. Since the offset reduces the size comparison accuracy of the 1-bit sampler 140, it can be reduced using the input offset voltage.

According to one embodiment, the electronic device 100 may include a plurality of modules implemented as a 1-bit sampler 140. For example, in the electronic device 100, the error even path (EREP), data even path (DAEP), and edge even path (EDEP) electrically connected to the DFE even module may be a 1-bit sampler 140. For example, in the electronic device 100, the edge odd path (EDOP), data odd path (DAOP), and error odd path (EROP) electrically connected to the DFE odd module may be a 1-bit sampler 140.

The processor 110 may perform offset calibration for a plurality of modules included in the AFE circuits 120, 130, and 140. Offset refers to the voltage value output when the input voltage is 0V, and offset calibration refers to compensating for the offset through this input offset voltage. The processor 110 may apply a common mode voltage to one node of the AFE circuit and measure the output voltage at the end of the AFE circuit. The common mode voltage is a voltage close to 0V. In the ideal case where there is no offset of each module included in the AFE circuit when the common mode voltage is input, the output voltage is 0V. If the output voltage is not 0V, the processor 110 may determine that an offset exists in at least one module of the AFE circuit. The processor 110 may determine the offset value of at least one module based on the output voltage and input a digital code for compensating the offset to the DAC 142 electrically connected to the module. The DAC 142 may convert the received digital code into an input offset voltage having a corresponding voltage level. The module can receive the input voltage and input offset voltage received from the front end and output a voltage with the offset compensated. The specific process by which the processor 110 performs offset calibration will be described later with reference to FIGS. 2A to 2G.

The processor 110 may determine a sequence for performing offset calibration on a plurality of modules. Each sequence may vary the target module that is the target of offset calibration, the location to apply the common mode voltage when calibrating each module, and the code search method. For example, the first sequence may use the first module as a target module, apply a common mode voltage to the front of the first module, and determine a digital code according to a predetermined method. The second sequence may perform calibration using a different module from the first sequence as a target module, and may vary the location of the applied common mode voltage and the code search method. The processor 110 can set N sequences and perform offset calibration by sequentially executing the determined sequences. For example, upon receiving a calibration execution command, the processor 110 may sequentially execute from the first sequence to the Nth sequence. According to one embodiment, the processor 110 may set a sequence interruption flag at the start and/or end point of the sequence. The processor 110 may stop sequence execution in response to checking the sequence stop flag. For example, the processor 110 may sequentially execute an offset calibration sequence starting from the first sequence, and then stop execution of the sequence in response to checking the sequence stop flag in the fourth sequence.

The processor 110 may provide a user interface for setting an offset calibration sequence in firmware. According to one embodiment, the processor 110 may provide a user interface that can determine the calibration sequence in firmware initial settings. Users can freely set each sequence of offset calibration using the user interface.

The processor 110 may perform a code search to determine a digital code for compensating for the offset. The processor 110 may divide a unit voltage (eg, 1V) into N levels and generate a digital code corresponding to each voltage level. The processor 110 sequentially inputs digital codes to the DAC 142 and can find an input offset voltage that can compensate for the offset of the module. The processor 110 may compensate for the offset of the module by inputting a digital code when the output voltage is closest to 0V.

For example, if the processor 110 divides the unit voltage into 10 levels (e.g., 0.1V, 0.2V, 0.3V, ??, 1V), 10 digital codes (h'0, h'1, h' 2,??,h'9) can be generated. The processor 110 can sequentially input digital codes to the DAC 142 of the target module and find the digital code when the output voltage is closest to 0V. Since the digital code corresponds to a voltage level that quantizes the unit voltage, it cannot perfectly compensate for the offset, which is an analog value, but the impact of the offset on the output voltage can be minimized by selecting the optimal input offset voltage. The code search method by which the processor 110 searches for a digital code will be described later with reference to FIGS. 5 and 6.

2A to 2G are examples of an operation in which an electronic device performs offset calibration on a DFE even module and a module connected to the DFE even module, according to an embodiment of the present disclosure.

FIG. 3 is a diagram illustrating an operation in which an electronic device calibrates a DFE odd module and modules connected to the DFE odd module according to an embodiment of the present disclosure.

Modules through which the processor 110 can compensate for offset through offset calibration are not limited to the modules shown in FIGS. 2 and 3. For example, the processor 110 may perform offset calibration using the same process even when a plurality of modules are added to the AFE circuit or the modules shown in FIGS. 2 and 3 are replaced with other modules. However, for explanation purposes, the AFE circuit will be described below as including the modules shown in FIGS. 2 and 3.

The AFE circuit is electrically connected to the CTLE (200) including the HF (202) and the VGA (204), the DFE even (210) and the DFE odd (310), which are electrically connected to the VGA (204), and the DFE even (210). An error even path (EREP) 212, a data even path (DAEP) 214 and an edge even path (EDEP) 216, an edge odd path (EDOP) 312 electrically connected to the DFE odd path 310, It may include a data odd path (DAOP) 314 and an error odd path (EROP) 316. The processor 110 may sequentially perform offset calibration for each module according to a predetermined sequence. Since the only voltage that the processor 110 can measure is the output voltage of a 1-bit sampler such as data even path, the processor 110 first measures and compensates the offset of the 1-bit sampler and moves to the front end of the DFE. The offset of the entire AFE circuit can be compensated in the order of measuring and compensating the offset and then measuring and compensating the offset of the CTLE (200) module.

In the first sequence, the processor 110 applies a common mode voltage to the front of the DFE even 210 and determines the digital code of the data even path (DAEP) 214 to determine the DFE even 210 and the data even path (DAEP) ( 214) can be calibrated. In the second sequence, the processor 110 may apply a common mode voltage in front of the VGA 204 to calibrate the VGA 204, the DFE even 210, and the data even path (DAEP) 214. In the third sequence, the processor 110 applies a common mode voltage to the front of the HF (202) and determines the digital code of the HF (202) to determine the HF (202), VGA (204), DFE even (210), and data even path. (DAEP) 214 can be calibrated. In the fourth sequence, the processor 110 applies a common mode voltage to the front of the HF 202 and determines the digital code of the VGA 204 to determine the HF 202, VGA 204, DFE even 210, and data even path. (DAEP) 214 can be calibrated. In the fifth sequence, the processor 110 applies a common mode voltage to the front of the HF (202) and determines the digital code of the data even path (DAEP) 214 to determine the digital code of the HF (202), VGA (204), and DFE even (210). ) and data even path (DAEP) 214 can be calibrated. In the sixth sequence, the processor 110 applies a common mode voltage to the front of the HF 202 and determines the digital code of the edge even path (EDEP) 216 to determine the digital code of the HF (202), VGA (204), and DFE even (210). ) and edge even path (EDEP) 216 can be calibrated. In the seventh sequence, the processor 110 applies a common mode voltage to the front of the HF 202 and determines the digital code of the error even path (EREP) 212 to determine the digital code of the HF (202), VGA (204), and DFE even (210). ) and error even path (EREP) 212 can be calibrated. In the 8th to 10th sequences, the processor 110 applies a common mode voltage to the front of the HF 202 to operate the HF 202, VGA 204, DFE odd 310, and data odd path (DAOP) 314. , error odd path (EDOP) and edge odd path (EDOP) 312 can be calibrated. The sequence and calibration method described in FIGS. 2 and 3 are only examples, and the calibration method performed by the processor 110 should not be interpreted as being limited thereto. Hereinafter, the process in which the processor 110 sequentially performs offset calibration for each module will be described in detail.

Referring to FIG. 2A, in the first sequence, the processor 110 applies a common mode voltage in front of the DFE even 210 and determines the digital code of the data even path (DAEP) 214 to determine the digital code of the DFE even 210 and the data even 210. Even path (DAEP) 214 can be calibrated. The processor 110 measures the output voltage of the data even path (DAEP) 214, determines the offset of the DFE even 210 and the data even path (DAEP) 214, and generates a digital code to compensate for the offset. You can decide.

Referring to Figure 2b, in the second sequence, the processor 110 measures the output voltage of the data even path (DAEP) 214 by applying a common mode voltage in front of the VGA 204, and the VGA 204 and the DFE even (210) and data even path (DAEP) 214 can be calibrated. Under the assumption that the offsets of the calibrated DFE even 210 and data even path (DAEP) 214 in the first sequence are sufficiently small, the processor 110 determines the digital code of the VGA 204 in the second sequence to The offset of (204) can be compensated.

Referring to FIG. 2C, in the third sequence, the processor 110 applies a common mode voltage in front of the HF 202 to measure the output voltage of the data even path (DAEP) 214 and the digital code of the HF 202. By determining , the HF (202), VGA (204), DFE even (210), and data even path (DAEP) (214) can be calibrated. Under the assumption that the offsets of the VGA 204, DFE even 210, and data even path (DAEP) 214 calibrated through the first and second sequences are sufficiently small, the processor 110 performs HF in the third sequence. The offset of HF 202 can be compensated by determining the digital code of 202.

Through the process described in FIGS. 2A to 2C, the processor 110 can compensate for the offset of all modules up to the data even path (DAEP) 214 of the AFE circuit. However, as explained earlier, the analog offset of each module cannot be perfectly compensated with the quantized input offset voltage. At this time, the residual offset amplified according to the gain of each module may increase as the stage progresses. The gains of all modules are g, and the residual offsets of HF (202), VGA (204), DFE even (210), and data even path (DAEP) (214) are V _HF , V _VGA , V _{DFE EVEN} , and V _DAEP , respectively. When , the final residual offset V _RO can be expressed as Equation 1 below.

Therefore, the digital code determined when the offset is compensated in the order of 1-bit sampler & DFE -> VGA (204) -> HF (202) may be a digital code that minimizes the offset at each stage, but the amplified code from the previous stage may be It may be a digital code that does not minimize the final offset due to residual offset. The processor 110 may perform calibration once more to compensate for the residual offset that has a significant impact on the output voltage. Calibration to compensate for the residual offset may be performed in the reverse order of the process described in FIGS. 2A to 2C. In the process of compensating for the residual offset, the offset of each module is compensated to some extent, and the residual offset of the front end (HF (202)), which has a large impact on the final output voltage, must be compensated first to reduce the final residual offset. am. Hereinafter, the process of performing calibration in reverse order will be described in FIGS. 2D to 2E.

Referring to FIG. 2D, in the fourth sequence, the processor 110 applies a common mode voltage in front of the HF 202, measures the output voltage of the data even path (DAEP) 214, and calculates the digital code of the VGA 204. You can decide. The processor 110 may calibrate the HF 202, VGA 204, DFE even 210, and data even path (DAEP) 214 in the fourth sequence. Although the digital code of VGA 204 has already been determined in the second sequence, processor 110 can fine-tune the digital code to compensate for residual offsets in HF 202. The digital code of the VGA 204 determined in the second sequence may be a digital code that minimizes its own offset of the VGA 204, and the digital code of the VGA 204 adjusted in the fourth sequence may be a digital code that minimizes the offset of the VGA 204. It may be a digital code that minimizes the offset of the VGA 204 by considering the offset.

Referring to FIG. 2E, in the fifth sequence, the processor 110 applies a common mode voltage to the front end of the HF 202 and measures the output voltage of the data even path (DAEP) 214. ) can be determined. The processor 110 may calibrate the HF 202, VGA 204, DFE even 210, and data even path (DAEP) 214 in the fifth sequence. The digital code of the data even path (DAEP) 214 has already been determined in the first sequence, but the processor 110 can fine-tune the digital code to compensate for residual offsets in the HF 202 and VGA 204. there is. The digital code of the data even path (DAEP) 214 determined in the first sequence may be a digital code that minimizes the offset of the DFE even 210 and the data even path (DAEP) 214, and in the fifth sequence The digital code of the adjusted data even path (DAEP) 214 minimizes the offset of the DFE even 210 and data even path (DAEP) 214 by considering the residual offset of the HF 202 and VGA 204. It could be a digital code.

Through the above processes (first to fifth sequences), the processor 110 can minimize the offsets of the HF 202, VGA 204, DFE even 210, and data even path. Thereafter, the processor 110 may calibrate the remaining 1-bit samplers connected to the DFE even 210, that is, the error even path (EREP) 212 and the edge even path (EDEP) 216. When calibrating the error even path (EREP) 212 and the edge even path (EDEP) 216, the processor 110 determines the digital values of the HF 202 and the VGA 204 through the first to fifth sequences. You can use the code as is.

Referring to FIG. 2F, in the sixth sequence, the processor 110 applies a common mode voltage in front of the HF 202 and determines the digital code of the edge even path (EDEP) 216 to determine the digital code of the HF 202 and the VGA 204. ), DFE even (210) and edge even path (EDEP) (216) can be calibrated. The digital code of the edge even path (EDEP) 216 determined in the sixth sequence is not only the offset of the DFE even 210 and the edge even path (EDEP) 216, but also the HF 202 and the VGA 204. It may be a digital code that minimizes the amplified residual offset that has been passed.

Referring to FIG. 2G, in the seventh sequence, the processor 110 applies a common mode voltage in front of the HF 202 and determines the digital code of the error even path (EREP) 212 to determine the HF 202 and the VGA 204. ), DFE even (210) and error even path (EREP) (212) can be calibrated. The digital code of the error even path (EREP) 212 determined in the seventh sequence is not only the offset of the DFE even 210 and the error even path (EREP) 212, but also the HF 202 and the VGA 204. It may be a digital code that minimizes the amplified residual offset that has been passed.

Referring to FIG. 3, in the eighth to tenth sequences, the processor 110 may calibrate the DFE odd 310 and the error odd path, data odd path, and edge odd path connected to the DFE odd path 310. The eighth to tenth sequences can be calibrated by applying a common mode voltage to the front end of the HF 202 and determining the digital code of each path. The method for calibrating the DFE odd 310 part is similar to the seventh sequence described in FIG. 2G, so description is omitted.

An exemplary method by which the processor 110 performs calibration is as described in FIGS. 2 and 3 . The processor 110 may provide a user interface so that a user can freely set the first to Nth sequences on firmware. The processor 110 may set an offset calibration sequence based on user input. For example, the processor 110 calibrates the edge even path (EDEP) 216 in the first to fifth sequences and the data even path (DAEP) 214 in the sixth sequence based on the user input. You can decide to do it. For example, the processor 110 calibrates the DFE odd 310 part rather than the DFE even 210 part in the first to seventh sequences based on the user input, and the DFE odd 310 part in the eighth to tenth sequences. You can decide to calibrate the even (210) part. Calibration sequence changes that the processor 110 can provide through firmware updates are not limited to the examples mentioned above, and the target module, the location where the common mode voltage is applied, and the code search method can be freely changed.

FIG. 4 is a diagram for explaining a method of calibrating using another method when the calibration process shown in FIGS. 2 and 3 fails.

The calibration process described in FIGS. 2 and 3 may be performed by first compensating for the offset of the DFE even part and then compensating for the offset of the DFE odd part (400). As can be seen in FIGS. 2 and 3, the calibration results of HF and VGA determined through the first to fifth sequences may also affect the calibration of the edge even path, error even path, and DFE odd part. However, if there is a problem with the DFE even part and a digital code that can minimize the offset and residual offset cannot be determined in HF or VGA, problems may also arise in the calibration of the DFE odd part.

For example, if the offset of the data even path (DAEP) is too large to compensate for the offset with its own input offset voltage, the offset of the data even path (DAEP) can be compensated by adjusting the digital code value in HF or VGA. there is. If the digital code value of the HF or VGA is affected by the offset compensation of the data even path (DAEP), a digital code that is different from the HF or VGA's own offset minimization may be selected. Therefore, calibration of the DFE odd part using the digital code of HF or VGA affected by the offset of the data even path (DAEP) may be inaccurate. The processor 110 may determine that calibration has failed if the digital code of HF or VGA is affected by the offset of the 1-bit sampler, or if the digital code of HF is affected by the offset of the VGA or 1-bit sampler.

If the processor 110 determines that calibration of the DFE even part has failed, the processor 110 may first perform calibration of the DFE odd part (410). If calibration of the DFE odd part is successful, the processor 110 can calibrate the DFE even part using the determined digital codes of HF and VGA. According to one embodiment, when calibration of the DFE even part fails, the sequence for calibrating the DFE odd part first may be set by user input through firmware update.

FIG. 5 is a diagram illustrating a method by which an electronic device determines a digital code to be input to the DAC of each module according to an embodiment of the present disclosure.

The processor 110 may determine a digital code to minimize the offset of the target module. The processor 110 can input the determined digital code to the DAC of the target module, and the analog voltage signal converted to a level corresponding to the digital code in the DAC can minimize offset. The faster you can determine the digital code, the shorter the time required for calibration. Hereinafter, 2-step linear search, a code search method that quickly determines a digital code, will be described.

, 각 전압 레벨에 디지털 코드(h'0~h'FF)를 부여할 수 있다.The processor 110 may divide the unit voltage into a predetermined number of levels and assign a digital code corresponding to the voltage of each level. For example, referring to Figure 5, the processor 110 divides the unit voltage into 256 voltages and

, a digital code (h'0~h'FF) can be assigned to each voltage level.

)에 해당하는 디지털 코드 h'9A를 DAC에 입력하면 오프셋이 최대로 보상되는 것으로 결정할 수 있다. 따라서, 프로세서(110)는 155(154개의 디지털 코드까지는 출력 전압이 감소하다가, 155번째 디지털 코드를 입력했을 때 출력 전압이 다시 증가함을 확인할 수 있음)개의 디지털 코드를 입력해야 타겟 모듈의 오프셋을 보상할 수 있다. 일반적인 선형 탐색의 경우 시간이 너무 오래 걸린다는 단점이 있다. 이를 보완하기 위하여 2-step 선형 탐색을 이용할 수 있다.In the case of a general linear search, the processor 110 sequentially sends a digital code to the DAC of the target module (e.g., h'0->h'1->h'2->...->h' FF) can be input and a digital code that can compensate for the offset as much as possible can be determined. For example, if the offset is 0.6V, the processor 110 sequentially inputs the digital code and then changes the voltage level (

), the offset can be determined to be maximally compensated by inputting the digital code h'9A corresponding to ) into the DAC. Therefore, the processor 110 must input 155 digital codes (the output voltage decreases up to 154 digital codes, and it can be seen that the output voltage increases again when the 155th digital code is input) to set the offset of the target module. Compensation is possible. The disadvantage of general linear search is that it takes too long. To compensate for this, 2-step linear search can be used.

In a 2-step linear search, the processor 110 may generate a subset of digital codes with a set search length (e.g., 16). The processor 110 may sequentially assign the first digital code of each subset to the DAC to determine the subset containing the digital code with the maximum offset compensation. The processor 110 can find the optimal digital code by sequentially inputting the digital codes included in the determined subset to the DAC.

For example, if the processor 110 sets the search length to 16, in the example above, the processor 110 inputs 10 times to find the optimal digital code for the 9th subset (h'91 - h'A0). It can be determined that is included. The processor 110 may sequentially input digital codes within the 9th subset, and if h'91, h'92, h'93, ?? are sequentially input, h'9A may be determined to be the optimal digital code. You can. In other words, the optimal digital code can be determined through a total of 20 inputs. Therefore, the digital code can be determined much faster than a typical linear search.

)만큼 이전 코드부터 순차적으로 DAC에 입력할 수 있다. 코드 서치에서 계산 오류가 발생하였더라도 마진만큼 여유를 두어 디지털 코드 서칭 정확도를 향상할 수 있다. 예를 들어, 위의 예시에서 9번째 부분 집합에 최적의 디지털 코드가 포함된 것으로 결정한 경우, 9번째 부분 집합의 첫 번째 디지털 코드에서 정해진 마진만큼 이전 디지털 코드(8번째 부분 집합에 속함)부터 순차적으로 DAC에 입력할 수 있다.According to one embodiment, the processor 110 determines a subset containing the optimal digital code and then determines a margin (e.g., a predetermined margin) in the first digital code of the determined subset.

) can be entered into the DAC sequentially starting from the previous code. Even if a calculation error occurs in code search, digital code search accuracy can be improved by providing a margin. For example, in the example above, if it is determined that the 9th subset contains the optimal digital code, the number of digits in the 9th subset is increased sequentially from the previous digital code (in the 8th subset) by a set margin. It can be input to the DAC.

Figure 6 is a diagram showing a system-on-chip according to an embodiment of the present disclosure.

Referring to FIG. 6, a system on chip (SoC) 2000 may refer to an integrated circuit that integrates components of a computing system or other electronic system. For example, an application processor (AP) as one of the system-on-chip 2000 may include a processor and components for other functions. As shown in FIG. 11, the system-on-chip 2000 includes a core 2100, a digital signal processor (DSP) 2200, a graphics processing unit (GPU) 2300, a built-in memory 2400, and a communication interface. It may include 2500 and a memory interface 2600. Components of system-on-chip 2000 may communicate with each other through bus 2700.

The core 2100 can process instructions and control the operation of components included in the system-on-chip 2000. For example, the core 2100 can drive an operating system and run applications on the operating system by processing a series of instructions. The DSP 2200 may generate useful data by processing digital signals, for example, digital signals provided from the communication interface 2500. The GPU 2300 may generate data for an image output through a display device from image data provided from the built-in memory 2400 or the memory interface 2600, and may encode the image data. The built-in memory 2400 can store data necessary for the core 2100, DSP 2200, and GPU 2300 to operate. The memory interface 2600 may provide an interface to external memory of the system-on-chip 2000, such as dynamic random access memory (DRAM) and flash memory.

An electronic device that performs offset calibration in an AFE circuit according to the technical idea of the present disclosure includes a plurality of modules included in the AFE circuit and at least one processor, wherein the at least one processor includes firmware. Provides a user interface for updating, determines a target module to perform offset calibration among the plurality of modules based on user input to the user interface, and determines a common mode voltage when performing calibration on the target module. It is possible to determine the location where voltage is applied, and determine a calibration sequence including the target module and the location where the common mode voltage is applied.

In addition, according to the technical idea of the present disclosure, the at least one processor divides the unit voltage into N levels (N is an integer) and assigns one digital code to each level, and the search length for determining the N digital codes Create a plurality of subsets grouped in the same number, apply a common mode voltage, input the first digital code of each subset to the DAC of the target module in ascending order, measure the output voltage sequentially, and measure the output voltage sequentially. Among the output voltages, a subset including a digital code with the minimum output voltage is detected, a common mode voltage is applied, and a plurality of digital codes belonging to the detected subset are input to the DAC in ascending order to sequentially increase the output voltage. , and among sequentially measured output voltages, the digital code with the lowest output voltage can be determined.

Additionally, according to the technical idea of the present disclosure, the at least one processor may input the first digital code of the detected subset to the DAC of the target module in ascending order from a smaller digital code by a predetermined margin.

In addition, according to the technical idea of the present disclosure, the at least one processor determines a code search method for searching the digital code based on a user input to the user interface, and performs a calibration method further comprising the code search method. The sequence can be determined.

In addition, according to the technical idea of the present disclosure, the AFE circuit includes a CTLE (continuous time linear equalizer) module including an HF module and a VGA (video graphics array) module electrically connected to the HF module, and electrically connected to the CTLE module. A connected DFE (decision feedback equalizer) module, at least one 1-bit sampler electrically connected to the DFE module, and at least one device connected to the at least one 1-bit sampler and converting the input digital code into an analog voltage signal and outputting it. Can include one DAC;

In addition, according to the technical idea of the present disclosure, the DFE module includes a DFE even and a DFE odd, and the at least one 1-bit sampler includes an error even path (EREP) and a data even path (DAEP) connected to the DFE even. ), edge even path (EDEP), and error odd path (EROP), data odd path (DAOP), and edge odd path (EDOP) connected to the DFE odd.

Additionally, according to the technical idea of the present disclosure, the at least one processor determines a plurality of offset calibration sequences based on a user input to the user interface, and, in response to receiving a calibration performance command, performs the plurality of offset calibration sequences. The calibration sequence can be executed sequentially.

In addition, according to the technical idea of the present disclosure, at least one offset calibration sequence includes a sequence interruption flag, and the at least one processor, in response to checking the sequence interruption flag while sequentially executing the offset calibration sequence, stops the offset calibration sequence. The calibration sequence can be aborted.

Additionally, according to the technical idea of the present disclosure, the at least one processor may perform the firmware update during system idle time and set an offset calibration sequence.

In addition, according to the technical idea of the present disclosure, a common mode voltage is applied to the front end of the target module to measure the output voltage, an offset of the target module is determined based on the output voltage, and a digital code corresponding to the determined offset is generated. A voltage that compensates for the offset can be applied by determining the digital code and inputting the digital code to a digital to analog converter (DAC) connected to the target module.

In addition, according to the technical idea of the present disclosure, the electronic device includes a first target module and a second target module connected to a front end of the first target module, and the at least one processor Measure the first offset of the first target module based on the voltage output by applying the mode voltage, input a first digital code corresponding to the first offset into the first DAC connected to the first target module, and A second offset of the second target module is measured based on the voltage output by applying a common mode voltage to the second target module, and a second digital signal corresponding to the second offset is connected to the second DAC connected to the second target module. You can enter the code.

In addition, according to the technical idea of the present disclosure, after inputting the second digital code to the second DAC, the at least one processor applies a common mode voltage to the second target module and operates based on the output voltage. The first offset of the first target module may be remeasured, and a 1-2 digital code corresponding to the remeasured first offset may be input to the first DAC.

According to the technical idea of the present disclosure, the AFE circuit for offset calibration includes a CTLE (continuous time linear equalizer) module including an HF module and a VGA (video graphics array) module electrically connected to the HF module, and an electrical circuit connected to the CTLE module. A decision feedback equalizer (DFE) module connected to a DFE module, at least one 1-bit sampler electrically connected to the DFE module, connected to the at least one 1-bit sampler, and converting the input digital code into an analog voltage signal and outputting it. Provides at least one DAC, a user interface for firmware update, and based on a user input to the user interface, a target module to perform offset calibration, a location where a common mode voltage is applied on the AFE circuit, and a digital code search method. It may include a control module that makes decisions.

Figure 7 is a flowchart of a method by which an electronic device determines an offset calibration sequence according to an embodiment of the present disclosure.

In operation 700, the electronic device may provide a user interface for firmware update. For example, an electronic device may provide a user interface for setting an offset calibration sequence in firmware initial settings. The electronic device may determine the offset calibration sequence according to the user's selection through the user interface.

In operation 702, the electronic device may determine a target module on which to perform offset calibration. According to one embodiment, the electronic device may determine a target module to perform offset calibration based on a user input on a user interface. Among the plurality of modules included in the AFE circuit, the electronic device can map one target module to one sequence. The electronic device may determine a plurality of target modules corresponding to each of the plurality of sequences based on the user input. Target modules mapped to each sequence may overlap. For example, the electronic device may determine the same module as the target module in the first sequence and the second sequence.

In operation 704, the electronic device may determine a location where the common mode voltage is applied on the AFE circuit when performing offset calibration. The electronic device can determine where to apply the common mode voltage in each sequence. Even if offset calibration is performed on the same target module, the location of the common mode voltage may be different.

In operation 706, the electronic device may determine a calibration sequence including the target module and the location where the common mode voltage is applied. The electronic device may determine the target module and the location where the common mode voltage is applied based on user input to the user interface. The electronic device can determine where one target module and one common mode voltage are applied for each sequence.

According to one embodiment, the electronic device may determine a method to search for a digital code to be input to the DAC connected to the target module. An electronic device can determine a digital code using various code search methods. For example, the electronic device may determine the digital code using one of linear search, binary search, and 2-step linear search methods. The electronic device may determine a digital code to be input to the DAC of the target module in each sequence based on user input to the user interface.

In operation 708, the electronic device may perform offset calibration by sequentially executing the stored sequence.

A method of performing offset calibration in an AFE circuit according to the technical idea of the present disclosure includes providing a user interface for firmware update, and based on a user input to the user interface, a plurality of modules included in the AFE circuit. Among them, determining a target module to perform offset calibration, determining a location where a common mode voltage is applied when performing calibration on the target module, and a location where the target module and the common mode voltage are applied. It may include an operation of determining a calibration sequence including.

In addition, according to the technical idea of the present disclosure, the method divides the unit voltage into N levels (N is an integer) and assigns one digital code to each level, the number of N digital codes equal to the determined search length. An operation to generate a plurality of subsets grouped together, an operation to apply a common mode voltage and input the first digital code of each subset to the DAC of the target module in ascending order to sequentially measure the output voltage, sequentially measured output An operation of detecting a subset of voltages that includes a digital code with a minimum output voltage, applying a common mode voltage, and inputting a plurality of digital codes belonging to the detected subset to the DAC in ascending order to sequentially increase the output voltage. It may further include an operation of measuring and an operation of determining a digital code with the minimum output voltage among sequentially measured output voltages.

In addition, according to the technical idea of the present disclosure, the operation of determining the digital code with the minimum output voltage is performed by selecting the DAC of the target module in ascending order from the digital code that is smaller by a predetermined margin from the first digital code of the detected subset. It may further include an input operation.

In addition, according to the technical idea of the present disclosure, the operation of determining a digital code with the minimum output voltage includes determining a code search method for searching the digital code based on a user input to the user interface; The method may further include determining a calibration sequence that further includes the code search method.

In addition, according to the technical idea of the present disclosure, the operation of measuring the output voltage by applying a common mode voltage to the front end of the target module, determining the offset of the target module based on the output voltage, and generating a digital code corresponding to the determined offset It may include an operation of determining, and an operation of applying a voltage that compensates for the offset by inputting the digital code to a digital to analog converter (DAC) connected to the target module.

In addition, according to the technical idea of the present disclosure, the operation of performing the offset calibration includes measuring the first offset of the first target module based on the voltage output by applying a common mode voltage to the first target module, An operation of inputting a first digital code corresponding to the first offset to a first DAC connected to a first target module, applying a common mode voltage to a second target module connected in front of the first target module, It may include measuring a second offset of a second target module based on the second target module and inputting a second digital code corresponding to the second offset into a second DAC connected to the second target module.

In addition, according to the technical idea of the present disclosure, the operation of performing the offset calibration is to apply a common mode voltage to the second target module after inputting the second digital code to the second DAC to change the output voltage to the output voltage. The method may further include re-measuring the first offset of the first target module based on the method and inputting a 1-2 digital code corresponding to the re-measured first offset into the first DAC.

FIG. 8 is a diagram illustrating how an amplifier included in an electronic device operates according to an embodiment of the present disclosure.

Electronics include HF, VGA, DFE even, error even path (EREP), data even path (DAEP), edge even path (EDEP), DFE odd, edge odd path (EDOP), data odd path (DAOP), and The error odd path (EROP) can all be implemented in the form of an amplifier 800. Each amplifier 800 can receive two input voltages and generate an output voltage. Referring to FIG. 8, the amplifier 800 may receive a first input voltage (V _in+ ) and a second input voltage (V _in- ). In the case of an ideal amplifier without offset (V _off ), when a common mode voltage (first voltage = second voltage = 0) is applied, the output voltage level is 0V. However, if the amplifier 800 includes an offset (V _off ), the offset can be offset by inputting a digital code into the DAC 810 to generate an analog voltage (V _dac ). The output voltage of the amplifier 800 can be expressed as Equation 2 below.

V _out : output voltage

V _in+ : first input voltage

V _in- : second input voltage

A: Amplifier gain

V _off : offset voltage

V _dac : analog voltage

Each amplifier 800 can select a digital code that causes the output voltage calculated through Equation 2 above to be 0V and input it to the DAC 810.

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terms, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached patent claims.

Claims (20)

In an electronic device that performs offset calibration in an AFE circuit,
A plurality of modules included in the AFE circuit; and
Contains at least one processor,
The at least one processor,
Providing a user interface for firmware update, and based on user input to the user interface,
Determine a target module to perform offset calibration among the plurality of modules,
When performing calibration for the target module, determine the location where the common mode voltage is applied,
An electronic device that determines a calibration sequence including the target module and a location where the common mode voltage is applied. According to claim 1,
The at least one processor,
Divide the unit voltage into N levels (N is an integer) and assign one digital code to each level,
Generate a plurality of subsets of N digital codes grouped into numbers equal to the determined search length,
Apply the common mode voltage, input the first digital code of each subset to the DAC of the target module in ascending order, and measure the output voltage sequentially;
Among sequentially measured output voltages, detect a subset containing a digital code with the minimum output voltage,
Apply a common mode voltage, input a plurality of digital codes belonging to the detected subset to the DAC in ascending order, and sequentially measure the output voltage,
An electronic device that determines the digital code with the lowest output voltage among sequentially measured output voltages. According to clause 2,
The at least one processor,
An electronic device that inputs the first digital code of the detected subset to the DAC of the target module in ascending order from a smaller digital code by a predetermined margin. According to clause 3,
The at least one processor,
Based on user input to the user interface, determine a code search method to search the digital code,
An electronic device for determining a calibration sequence further comprising the code search method. According to claim 1,
The AFE circuit is,
A CTLE (continuous time linear equalizer) module including an HF module and a VGA (video graphics array) module electrically connected to the HF module;
a decision feedback equalizer (DFE) module electrically connected to the CTLE module;
At least one 1-bit sampler electrically connected to the DFE module;
An electronic device comprising: at least one DAC connected to the at least one 1-bit sampler and converting the input digital code into an analog voltage signal and outputting the converted signal. According to clause 5,
The DFE module includes DFE even and DFE odd,
The at least one 1-bit sampler:
Error even path (EREP), data even path (DAEP), edge even path (EDEP) connected to the DFE even, and error odd path (EROP), data odd path (DAOP), and edge odd path ( Electronic devices containing EDOP). According to claim 1,
The at least one processor,
Based on user input to the user interface, determine a plurality of offset calibration sequences,
An electronic device that sequentially executes the plurality of offset calibration sequences in response to receiving a calibration performance command. According to clause 7,
at least one offset calibration sequence includes a sequence abort flag,
The at least one processor,
An electronic device that stops an offset calibration sequence in response to checking the sequence stop flag while sequentially executing the offset calibration sequence. According to claim 1,
The at least one processor,
An electronic device that performs the firmware update during system idle time and sets an offset calibration sequence. According to claim 1,
Measure the output voltage by applying a common mode voltage to the front end of the target module,
Determine an offset of the target module based on the output voltage, determine a digital code corresponding to the determined offset, and
An electronic device that inputs the digital code into a digital to analog converter (DAC) connected to the target module to apply a voltage that compensates for the offset. According to claim 10,
The electronic device includes a first target module and a second target module connected to a front end of the first target module,
The at least one processor,
Applying a common mode voltage to the first target module and measuring the first offset of the first target module based on the voltage output,
Inputting a first digital code corresponding to the first offset into the first DAC connected to the first target module,
Applying a common mode voltage to the second target module and measuring a second offset of the second target module based on the voltage output,
An electronic device that inputs a second digital code corresponding to the second offset into a second DAC connected to the second target module. According to claim 11,
The at least one processor,
After inputting the second digital code to the second DAC, apply a common mode voltage to the second target module and remeasure the first offset of the first target module based on the output voltage,
An electronic device that inputs a 1-2 digital code corresponding to the re-measured first offset into the first DAC. In a method of performing offset calibration in an AFE circuit,
providing a user interface for updating firmware, and
Based on user input to the user interface,
An operation of determining a target module to perform offset calibration among a plurality of modules included in the AFE circuit;
An operation of determining a location where a common mode voltage is applied when performing calibration for the target module,
A method comprising determining a calibration sequence including the target module and a location where the common mode voltage is applied. According to claim 13,
An operation of dividing a unit voltage into N levels (N is an integer) and assigning one digital code to each level,
An operation of generating a plurality of subsets of N digital codes grouped into numbers equal to the determined search length,
An operation of applying a common mode voltage and sequentially measuring the output voltage by inputting the first digital code of each subset to the DAC of the target module in ascending order;
An operation of detecting a subset containing a digital code with a minimum output voltage among sequentially measured output voltages,
An operation of applying a common mode voltage and inputting a plurality of digital codes belonging to the detected subset to the DAC in ascending order to sequentially measure the output voltage, and
A method further comprising determining a digital code with the minimum output voltage among sequentially measured output voltages. According to claim 14,
The operation of determining the digital code with the minimum output voltage is,
The method further includes inputting the first digital code of the detected subset to the DAC of the target module in ascending order from a smaller digital code by a predetermined margin. According to claim 15,
The operation of determining the digital code with the minimum output voltage is,
An operation of determining a code search method for searching the digital code based on a user input to the user interface;
The method further includes determining a calibration sequence that further includes the code search method. According to claim 13,
An operation of measuring the output voltage by applying a common mode voltage to the front of the target module,
An operation of determining an offset of the target module based on the output voltage and determining a digital code corresponding to the determined offset, and
A method comprising applying a voltage to compensate for the offset by inputting the digital code into a digital to analog converter (DAC) connected to the target module. According to claim 17,
The operation of performing the offset calibration is:
An operation of measuring the first offset of the first target module based on the voltage output by applying a common mode voltage to the first target module;
An operation of inputting a first digital code corresponding to the first offset into a first DAC connected to the first target module,
An operation of applying a common mode voltage to a second target module connected to the front of the first target module and measuring a second offset of the second target module based on the voltage output;
A method comprising inputting a second digital code corresponding to the second offset into a second DAC connected to the second target module. According to clause 18,
The operation of performing the offset calibration is:
After inputting the second digital code to the second DAC, applying a common mode voltage to the second target module and re-measuring the first offset of the first target module based on the output voltage;
The method further includes inputting a 1-2 digital code corresponding to the re-measured first offset into the first DAC. In the AFE circuit for offset calibration,
A CTLE (continuous time linear equalizer) module including an HF module and a VGA (video graphics array) module electrically connected to the HF module;
a decision feedback equalizer (DFE) module electrically connected to the CTLE module;
At least one 1-bit sampler electrically connected to the DFE module;
At least one DAC connected to the at least one 1-bit sampler and converting the input digital code into an analog voltage signal and outputting it;
A control module that provides a user interface for firmware update and determines, based on user input to the user interface, a target module to perform offset calibration, a location where a common mode voltage is applied on the AFE circuit, and a digital code search method; AFE circuit including.

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