KR20240052918A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device according to an embodiment includes a substrate having a cell region and an outer region surrounding the cell region, a device isolation film including a first device isolation film located in the outer region on the substrate, and an active region of the cell region. a gate structure including a second device isolation layer defining a second device isolation layer, and a word line that crosses the active region in the cell region and extends over the first device isolation layer in the outer region, the gate structure comprising: It may include a first pattern including a first part having a flat top surface and a second part of the cell area, and a second pattern located on the second part of the first pattern.

Description

Semiconductor device and method of manufacturing the same {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

This disclosure relates to semiconductor devices and methods of manufacturing semiconductor devices.

In order to reduce the impact and leakage current caused by shorter channel lengths due to the high integration of semiconductor devices, a buried channel array transistor (buried channel) is used in which the word line is buried inside the semiconductor substrate and the overlap between the gate and drain regions is minimized. array transistor (BCAT) is being proposed.

The embodiments are intended to improve the characteristics of semiconductor devices and reduce gate structure defects.

A semiconductor device according to an embodiment includes a substrate having a cell region and an outer region surrounding the cell region, a device isolation film including a first device isolation film located in the outer region on the substrate, and an active region of the cell region. A device isolation layer including a second device isolation layer defining, and a gate structure including a word line that crosses the active region in the cell region and extends over the first device isolation layer in the outer region, the gate structure may include a first pattern including a first part having a flat upper surface in the outer area and a second part of the cell area, and a second pattern located on the second part of the first pattern. .

A method of manufacturing a semiconductor device according to an embodiment includes providing a substrate including a cell region and an outer region surrounding the cell region, etching the substrate to form a first device isolation layer defining an active region of the cell region. and forming a device isolation film including a first device isolation film defining the outer region, extending across the active region on the substrate and over the first device isolation film in the outer region, forming a first pattern. It may include forming a second pattern on the first pattern made of a different material from the first pattern, and performing a planarization process to polish the second pattern in the outer area. .

According to embodiments, the characteristics of semiconductor devices can be improved and gate structure defects can be reduced.

1 is a plan view of a semiconductor device according to an embodiment.
FIG. 2 is an enlarged view of area S of FIG. 1.
Figure 3 is a cross-sectional view taken along line A-A' of Figure 2.
Figure 4 is a cross-sectional view taken along line B-B' in Figure 2.
5 to 14 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment.

Hereinafter, with reference to the attached drawings, various embodiments of the present invention will be described in detail so that those skilled in the art can easily practice the present invention. The invention may be implemented in many different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts that are not relevant to the description are omitted, and identical or similar components are given the same reference numerals throughout the specification.

In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, so the present invention is not necessarily limited to what is shown. In the drawing, the thickness is enlarged to clearly express various layers and areas. And in the drawing, for convenience of explanation, the thickness of some layers and regions are exaggerated.

Additionally, when a part of a layer, membrane, region, plate, etc. is said to be “on” or “on” another part, this includes not only cases where it is “directly above” another part, but also cases where there is another part in between. . Conversely, when a part is said to be “right on top” of another part, it means that there is no other part in between. In addition, being “on” or “on” a reference part means being located above or below the reference part, and does not necessarily mean being located “above” or “on” the direction opposite to gravity. .

In addition, throughout the specification, when a part is said to "include" a certain component, this means that it may further include other components rather than excluding other components, unless specifically stated to the contrary.

In addition, throughout the specification, when referring to “on a plane,” this means when the target portion is viewed from above, and when referring to “in cross-section,” this means when a cross section of the target portion is cut vertically and viewed from the side.

Hereinafter, a semiconductor device according to an embodiment will be described with reference to FIGS. 1 and 2 as follows.

FIG. 1 is a plan view of a semiconductor device according to an embodiment, and FIG. 2 is an enlarged view of region S of FIG. 1 .

Referring to FIGS. 1 and 2 , a semiconductor device may include a substrate 100 and a plurality of active regions (AC). The substrate 100 includes a cell region (CR), an outer region (OR) surrounding the cell region (CR), and a peripheral region where elements for driving the cell region (CR) are located. region) (PR) may be included. In this specification, the regions CR, OR, and PR may be defined and explained in the substrate 100.

The substrate 100 may include a semiconductor material. For example, the substrate 100 may include a group IV semiconductor, a group III-V compound semiconductor, a group II-VI compound semiconductor, etc. For example, the substrate 100 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. It may be a Silicon on Insulator (SOI) substrate or a Germanium on Insulator (GOI) substrate. However, the material of the substrate 100 is not limited to this and may be changed in various ways.

A plurality of active regions (AC) may be formed in the cell region (CR). In the cell region CR, semiconductor cells including the active region AC may be arranged in an array. For example, when the semiconductor device to be formed is a semiconductor memory device, semiconductor memory cells may be formed in an array in the cell region CR. A device isolation film (e.g., the second device isolation film 110B of FIG. 3) may be formed in the cell region CR.

The peripheral area PR may be placed around the cell area CR, or may be placed in a separate area different from the cell area CR. For example, the peripheral area (PR) may surround the cell area (CR). Circuits necessary to control semiconductor cells formed in the cell region CR may be disposed in the peripheral area PR. For example, a word line driver, a sense amplifier, row and column decoders, and control circuits may be placed in the peripheral area PR.

The outer area (OR) may correspond to an area surrounding the cell area (CR). The outer area (OR) may be interposed between the cell area (CR) and the peripheral area (PR). For example, the outer region (OR) may surround the cell region (CR), and the peripheral region (PR) may surround the outer region (OR). A device isolation film (eg, the first device isolation film 110A of FIG. 3) may be formed in the outer region OR.

Referring to FIG. 2 , the active area AC may have a bar shape and may be arranged in an island shape extending in one direction, for example, the W direction, within the substrate 100 . The W direction may be inclined with respect to the extension direction of the word lines WL. Each active area AC may be formed in a bar shape extending in the W direction rather than the X and Y directions on a plane extending in the X and Y directions. Here, the W direction is parallel to the top surface of the substrate 100 and may be any direction other than the X and Y directions. In some embodiments, the W direction may form an acute angle with the X direction. The acute angle may be, for example, 60 degrees, but is not limited thereto.

The active areas AC may be arranged to be parallel to each other, and an end portion of one active area AC may be arranged adjacent to the center of another active area AC adjacent thereto. Specifically, the active areas AC may be spaced apart in the W direction. Adjacent active areas AC in the Y direction may be arranged side by side. Adjacent active areas AC in the X direction may be arranged to be staggered.

The active area AC may include impurities to form source and drain areas. For example, the active area AC may include p-type impurities or n-type impurities. Implanting impurities into the active area AC may be performed, for example, by an ion implantation process, but is not limited thereto.

The word line WL may be arranged to extend in the X direction across the active area AC. For example, a pair of word lines (WL) adjacent to each other may be arranged to cross one active area (AC). A plurality of word lines WL may extend parallel to each other. Additionally, the plurality of word lines WL may be spaced apart from each other at equal intervals. The word line (WL) may form the gate of a buried channel array transistor (BCAT), but is not limited to this. In example embodiments, the word lines WL may be arranged on top of the substrate 100 .

According to one embodiment, the word line (WL) may extend beyond the cell area (CR) to the outer area (OR). For example, as shown in FIG. 3, a portion of the word line (WL) may be placed on the outer area (OR). Accordingly, as shown in FIG. 3, a portion of the word line WL may extend above the first device isolation layer 110A. More specifically, the first pattern 130 included in the word line WL may extend over the first device isolation layer 110A. Hereinafter, a semiconductor device according to an embodiment will be further described with further reference to FIGS. 3 and 4 .

Figure 3 is a cross-sectional view taken along line A-A' of Figure 2. Figure 4 is a cross-sectional view taken along line B-B' in Figure 2. 3 and 4 may show an example structure of an intermediate state in the process of forming the semiconductor device 10. The semiconductor device 10 shown in FIGS. 3 and 4 is shown centered on the device isolation structure, and the semiconductor device 10 may further include other configurations in addition to those shown in FIGS. 3 and 4 through subsequent processes. You can. For example, bit lines, capacitors, etc. may be further included in the semiconductor device 10.

3 and 4, the semiconductor device 10 is embedded and extends within the substrate 100, the device isolation layer 110, and the substrate 100 including active regions (AC) and a word line (WL). It may include a gate structure 300 including. The active regions AC and the gate structure 300 may be disposed in the cell region CR.

According to one embodiment, the active regions AC may be defined within the substrate 100 by the second device isolation layer 110B in the cell region. In example embodiments, the active area AC may or may not include a well area containing impurities. For example, in the case of a p-type transistor (pFET), the well region may include n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb). In this case, the well region may include p-type impurities such as boron (B), gallium (Ga), or indium (In). For example, the well area may be located at a predetermined depth from the top surface of the active area AC.

The active area AC may include impurities to form a source region and a drain region. For example, the active area AC may include p-type impurities or n-type impurities. Implanting impurities into the active area AC may be performed, for example, by an ion implantation process, but is not limited thereto.

The device isolation film 110 may be formed by a shallow trench isolation (STI) process. The device isolation film 110 may be made of an insulating material, and the insulating material may be, for example, silicon oxide, silicon nitride, or a combination thereof. The device isolation layer 110 may include a plurality of regions with different bottom depths depending on the width of the trench in which the substrate 100 is etched.

The device isolation film 110 includes a first device isolation film 110A located in the outer region OR on the substrate 100 and a second device isolation film 110B defining the active region AC of the cell region CR. can do. According to one embodiment, the depth of the first device isolation layer 110A may be deeper than the depth of the second device isolation layer 110B. The width of the first device isolation film 110A may be larger than the width of the second device isolation film 110B.

According to one embodiment, the first device isolation layer 110A may be formed in the outer region OR. The first device isolation layer 110A may define a boundary between the cell region (CR) and the outer region (OR).

According to one embodiment, the first device isolation layer 110A may be formed as a multilayer. For example, the first device isolation layer 110A may include one or more insulating layers. According to one embodiment, the first device isolation layer 110A may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. The second insulating layer 112 may be disposed on the first insulating layer 111, and the third insulating layer 113 may be disposed on the second insulating layer 112. Within the first device isolation layer 110A, the first insulating layer 111 and the second insulating layer 112 may be sequentially formed conformally along the surface of the first device isolation layer 110A.

The third insulating layer 113 may fill the space where the first insulating layer 111 and the second insulating layer 112 do not fill the first device isolation layer 110A. The second insulating layer 112 may include an insulating material different from the first insulating layer 111, and the third insulating layer 113 may include an insulating material different from the second insulating layer 112. For example, the first insulating layer 111 and the third insulating layer 113 may include silicon oxide, and the second insulating layer 112 may include silicon nitride.

In FIG. 3 , the sidewall of the first device isolation layer 110A is shown as having an inclination, but this is only a characteristic of the etching process for forming the first device isolation layer 110A, and the technical idea of the present invention is not limited thereto.

According to one embodiment, the second device isolation layer 110B may be formed in the cell region CR. The second device isolation layer 110B may define an active region AC that protrudes on the cell region CR. The second device isolation layer 110B may surround the active regions AC and electrically separate them from each other. According to one embodiment, the second device isolation film 110B may include a plurality of regions (or isolation films) having different widths and/or depths.

In FIG. 3 , the sidewall of the second device isolation layer 110B is shown as having an inclination, but this is only a characteristic of the etching process for forming the second device isolation layer 110B, and the technical idea of the present invention is not limited thereto.

According to one embodiment, the second device isolation layer 110B may be formed as a multilayer. For example, the second device isolation layer 110B may include one or more insulating layers. Specifically, the second device isolation layer 110B may include a fourth insulating layer 114 and a fifth insulating layer 115. The fourth insulating layer 114 may have a conformal shape to cover the sidewalls and bottom of the first trench 211 . The fourth insulating layer 114 may include, for example, silicon oxide. According to one embodiment, the fifth insulating layer 115 may include silicon nitride.

According to one embodiment, the mask layer 120 may be positioned on the third insulating layer 113. Additionally, at least a portion of the third insulating layer 113 may be in contact with the second insulating layer 112. For example, the mask layer 120 may include a material having an etch selectivity with respect to the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The mask layer 120 may be formed, for example, by a chemical vapor deposition (CVD) process or an ALD process.

In FIG. 3, the mask layer 120 is shown as a single layer, but this is only for convenience of explanation and is not limited thereto. The mask layer 120 may be formed as one layer or may be formed as multiple layers.

The gate structure 300 may be disposed in gate trenches GT extending within the substrate 100 . The gate structure 300 may include a gate insulating layer 121, a word line (WL), and a gate capping layer 150.

Referring to FIGS. 3 and 4 , a portion of the side surface and a portion of the bottom surface of the gate structure 300 may be in contact with the active area AC. A portion of the side surface and a portion of the bottom surface of the gate structure 300 may also be in contact with the second device isolation layer 110B. Specifically, the gate insulating layer 121 included in the gate structure 300 may contact the active area AC and the second device isolation layer 110B.

The gate insulating layer 121 may be disposed on the bottom and inner surfaces of the gate trench GT. The gate insulating layer 121 may conformally cover the inner wall of the gate trench (GT).

According to one embodiment, the gate insulating layer 121 may be interposed between the active region AC and the word line WL in the cell region CR. According to one embodiment, at least a portion of the gate insulating layer 121 in the outer region OR may be interposed between the first device isolation layer 110A and the first pattern 130 of the word line WL. Additionally, at least a portion of the gate insulating layer 121 may cover the top surface and sidewalls of the mask layer 120 in the outer area OR. The gate insulating layer 121 may be connected to the mask layer 120 along the top and sidewalls of the first device isolation layer 110A.

The gate insulating layer 121 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. According to one embodiment, the gate insulating layer 121 may be a layer formed by oxidizing the active area AC, or may be a layer formed by deposition.

The mask layer 120 and the gate insulating layer 121 located on the mask layer 120 may be removed in a subsequent process.

The word line (WL) is a conductive material, such as polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN). ), and may include at least one of aluminum (Al).

According to one embodiment, the word line WL may include a first pattern 130 and a second pattern 140 formed of different materials.

According to one embodiment, the first pattern 130 may be a metal pattern including at least one of metal and metal nitride. More specifically, for example, the first pattern 130 is at least one of tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). may include.

Referring to FIGS. 3 and 4 , the gate trench GT according to one embodiment may extend in the X direction, and the first pattern 130 may be formed within the gate trench GT. That is, the first pattern 130 may also extend long in the X direction.

According to one embodiment, the first pattern 130 may be located in the cell area (CR) and the outer area (OR). More specifically, the first pattern 130 may extend beyond the cell area (CR) to the outer area (OR). For example, the first pattern 130 may have a first part 131 in the outer area OR and a second part 132 in the cell area CR. The first part 131 and the second part 132 of the first pattern 130 may be connected to each other. For example, the first part 131 and the second part 132 may be formed as one piece.

According to one embodiment, the first thickness t1 of the first part 131 and the second thickness t2 of the second part 132 may be different from each other. For example, the first thickness t1 may be thicker than the second thickness t2. That is, the first part 131 of the first pattern 130 has a first thickness t1 in the vertical direction of the substrate 100, and the second part 132 of the first pattern 130 has a first thickness t1 in the vertical direction of the substrate 100. ) may have a second thickness (t2) that is smaller than the first thickness (t1) in the vertical direction. The first thickness t1 may correspond to the longest distance between the gate insulating layer 121 and the top surface of the first portion 131. The second thickness t2 may correspond to the longest distance between the gate insulating layer 121 and the top surface of the second portion 132.

As described above, in the semiconductor device 10 according to the present specification, the thickness of the first pattern 130 in the outer region (OR) is increased compared to the cell region (CR), so that the outer region (OR) and the cell region ( The disconnection phenomenon of the first pattern 130 between CR) can be improved. Accordingly, product reliability can be improved by improving semiconductor device defects due to disconnection phenomenon.

According to one embodiment, there may be a height difference (or step) of the upper surface of the first pattern 130 at the boundary between the cell region CR and the outer region OR. Specifically, the height of the top surface of the first pattern 130 in the outer area OR may be higher than the height of the top surface of the first pattern 130 in the cell area CR. That is, the height of the top surface of the first part 131 may be higher than the height of the top surface of the second part 132.

According to one embodiment, the first portion 131 of the first pattern 130 may have a flat top surface. For example, the upper surface of the first portion 131 may have a surface roughness of about 50 Å or less. As will be described later with reference to FIGS. 11 and 12 , the fact that the first part 131 has a flat top surface means that all of the second patterns 140 are removed from the outer area OR and placed on the first part 131. This may mean that the second pattern 140 does not exist. According to one embodiment, the second portion 132 of the first pattern 130 may have an uneven top surface in the cell region CR. However, the present invention is not limited to this, and the second part 132 may have a flat top surface in the cell region CR.

According to one embodiment, the second pattern 140 may be a semiconductor pattern including polysilicon doped with P-type or N-type impurities.

According to one embodiment, the second pattern 140 may extend in the X direction. According to one embodiment, the second pattern 140 may be located in the cell region CR.

According to one embodiment, the second pattern 140 may be disposed on the second portion 132 of the first pattern 130. According to one embodiment, the second pattern 140 extends in the You can access it. According to one embodiment, the second pattern 140 may not be disposed on the first portion 131 of the first pattern 130. More specifically, as the second pattern 140 is removed from the outer area OR, it may not be disposed on the first portion 131.

As described above, in the semiconductor device 10 according to the present specification, distribution deterioration in a subsequent etching process can be prevented by removing the second pattern 140.

The second pattern 140 may have a third thickness t3 in the vertical direction on the second portion 132 . The third thickness t3 may correspond to the longest distance between the second portion 132 and the top surface of the second pattern 140. According to one embodiment, the first thickness t1 may be greater than or equal to the sum of the second thickness t2 and the third thickness t3.

As described above, in the semiconductor device 10 according to the present specification, the first thickness t1 of the first pattern 130 is formed to be sufficiently thicker than the sum of the second thickness t2 and the third thickness t3. , the disconnection phenomenon of the first pattern 130 between the outer area (OR) and the cell area (CR) can be improved.

The gate capping layer 150 may be formed on the word line (WL). For example, the gate capping layer 150 may fill the area of the gate trench GT remaining after the gate insulating layer 121 and the word line WL are filled. That is, the gate capping layer 150 may be disposed to fill the gate trench GT at the top of the word line WL. More specifically, in the cell region CR, the gate capping layer 150 may cover the second pattern 140 and bury the upper part of the gate trench GT. That is, the gate capping layer 150 may fill the space where the gate insulating layer 121, the first pattern 130, and the second pattern 140 do not fill the gate trench GT.

According to one embodiment, the gate capping layer 150 may be disposed to contact the second pattern 140 in the cell region CR and to contact the first pattern 130 in the outer region OR. More specifically, the gate capping layer 150 may contact the second pattern 140 in the cell region CR, and may contact the first pattern 130 having a flat top surface in the outer region OR. According to one embodiment, the second pattern 140 may be positioned between the second portion 132 of the first pattern 130 and the gate capping layer 150. That is, the gate capping layer 150 may be in contact with the first part 131 and not in contact with the second part 132.

The gate capping layer 150 may include, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof.

5 to 14 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment. The semiconductor device 10 shown in FIGS. 3 and 4 can be manufactured by the manufacturing method according to FIGS. 7 to 12. Detailed description of parts that have already been described will be omitted, and parts that have not been explained will be explained in detail.

Figures 5, 7, 9, 11, and 13 are cross-sectional views taken along line A-A' in Figure 2. Line A-A' may be parallel to the X direction. FIGS. 6, 8, 10, 12, and 14 are cross-sectional views taken along line B-B' of FIG. 2. Line B-B' may be parallel to the Y direction.

Referring to FIGS. 5 and 6 , the device isolation layer 110 may be formed on the substrate 100 including the cell region (CR) and the outer region (OR). For example, the device isolation film 110 may be formed by a shallow trench isolation (STI) process.

According to one embodiment, the device isolation film 110 may include a first device isolation film 110A located in the outer region OR and a second device isolation film 110B located in the cell region CR.

According to one embodiment, the first device isolation layer 110A may be formed to define the boundary between the outer region OR and the cell region CR. According to one embodiment, the first device isolation layer 110A may be located in the outer region OR. Alternatively, the first device isolation layer 110A may be located at the boundary between the cell region CR and the outer region OR. According to one embodiment, the first device isolation film 110A may have a greater depth than the second device isolation film 110B. Additionally, the width of the first device isolation layer 110A may be larger than the width of the second device isolation layer 110B.

According to one embodiment, the second device isolation layer 110B may be formed to define (or limit) the active region AC in the cell region CR. According to one embodiment, the second device isolation film 110B may include a plurality of regions (or isolation films) having different widths and/or depths. A plurality of regions having different widths and/or depths may be alternately positioned along the X direction on the substrate 100 .

Next, insulating layers 111, 112, 113, 114, and 115 may be formed within the device isolation film 110. The insulating layers 111, 112, 113, 114, and 115 may be formed by, for example, an atomic layer deposition (ALD) process.

According to one embodiment, the first insulating layer 111 and the second insulating layer 112 may be sequentially formed conformally along the surface of the first device isolation layer 110A. According to one embodiment, the third insulating layer 113 may fill the space where the first insulating layer 111 and the second insulating layer 112 do not fill the first device isolation layer 110A.

According to one embodiment, the fourth insulating layer 114 may be formed conformally along the surface of the second device isolation layer 110B. According to one embodiment, the fifth insulating layer 115 may fill the space where the fourth insulating layer 114 does not fill the second device isolation layer 110B.

According to one embodiment, the first device isolation layer 110A may include a first insulating layer 111 and a third insulating layer 113 including a first material. According to one embodiment, the first device isolation layer 110A may include a second insulating layer 112 including a second material.

According to one embodiment, the second device isolation layer 110B may include a fourth insulating layer 114 including a first material and a fifth insulating layer 115 including a second material.

The first material and the second material may each be an insulating material. The second material may include a different insulating material than the first material. In this specification, a case where the first material is silicon oxide and the second material is silicon nitride will be described. However, the first and second materials are not limited to this and may be changed in various ways.

A mask layer 120 may be formed on the insulating layers 111, 112, 113, 114, and 115. For example, the mask layer 120 may include a material having an etch selectivity with respect to the insulating layers 111, 112, 113, 114, and 115. The mask layer 120 may be formed, for example, by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

Referring to FIG. 6 , gate trenches GT may be formed that intersect the active area AC and extend in a direction parallel to the top surface of the substrate 100 (eg, the X direction in FIG. 5 ). For example, gate trenches GT may be formed through an etching process. Gate trenches GT may be arranged to be spaced apart in the Y direction.

According to one embodiment, the gate trench GT may be formed through an etching process. For example, the etching process can be performed using a material having a selectivity ratio of silicon nitride to silicon oxide. For example, the material may have an etch rate for silicon oxide that is higher than that for silicon nitride.

Referring to FIGS. 5 and 6 , the gate insulating layer 121 may be formed on the active area AC and the insulating layers 111, 112, 113, 114, and 115 exposed by the gate trench GT. The gate insulating layer 121 may be located on the mask layer 120. The gate insulating layer 121 may be formed, for example, through an ALD process. The gate insulating layer 121 may include, for example, silicon oxide.

The gate insulating layer 121 may cover the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 located within the first device isolation layer 110A. For example, the gate insulating layer 121 may cover the top surfaces of the first insulating layer 111 and the second insulating layer 112. Also, for example, the gate insulating layer 121 may cover the sidewall and top surface of the third insulating layer 113.

The gate insulating layer 121 may cover the fourth insulating layer 114 and the fifth insulating layer 115 located in the second device isolation layer 110B. For example, the gate insulating layer 121 may cover the upper surfaces of the fourth insulating layer 114 and the fifth insulating layer 115.

According to one embodiment, the mask layer 120 and the gate insulating layer 121 located on the mask layer 120 may be removed in a subsequent process.

Referring to FIGS. 7 and 8 , the first pattern 130 may be formed on the gate insulating layer 121 . The first pattern 130 may be located on the first device isolation layer 110A in the outer region OR and the second device isolation layer 110B in the cell region CR. Specifically, the first pattern 130 may extend from the cell region CR across the active region AC and onto the first device isolation layer 110A in the outer region OR in the X direction.

Referring to FIG. 7 , the first pattern 130 may be formed to have a first part 131 in the outer area OR and a second part 132 in the cell area CR. For example, the first part 131 and the second part 132 may be formed as one piece. According to one embodiment, the first pattern 130 may be formed to be thicker in the outer area OR than in the cell area CR.

Accordingly, there may be a height difference (or step) between the upper surface of the first pattern at the boundary between the cell region CR and the outer region OR. Specifically, the height of the top surface of the first part 131 in the outer area OR may be higher than the height of the second part 132 in the cell area CR.

As described above, in the semiconductor device according to the present invention, the first pattern 130 is formed thicker in the outer region (OR) than in the cell region (CR), so that the first pattern 130 is formed thicker at the boundary between the outer region (OR) and the cell region (CR). The disconnection phenomenon of the pattern 130 can be improved.

Referring to FIG. 8, the first pattern 130 can be deposited by controlling the deposition process conditions so that the gate trench GT is sufficiently filled. Accordingly, the first pattern 130 may cover the gate insulating layer 121 and bury the lower portion of the gate trench (GT).

According to one embodiment, the first pattern 130 is formed by a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). It can be formed by depositing a conductive material on the gate insulating layer 121.

According to one embodiment, the first pattern 130 may be a metal pattern including at least one of metal and metal nitride. For example, the first pattern 130 may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). You can.

Referring to FIG. 9 , the second pattern 140 may be formed on the first pattern 130. According to one embodiment, the second pattern 140 includes the first portion 131 of the first pattern 130 located in the outer region OR and the first pattern 130 located in the cell region CR. It may be located on the second portion 132. Specifically, the second pattern 140 will cross the second portion 132 of the first pattern 130 in the cell region (CR) and extend over the first pattern 130 in the outer region (OR) in the X direction. You can.

According to one embodiment, the second pattern 140 may be formed to be thicker in the cell region (CR) than the outer region (OR). Here, the thickness may mean the thickness in the Z direction perpendicular to the upper surface of the substrate 100.

According to one embodiment, there may be a height difference (or step) between the top surface of the second pattern 140 in the cell region CR and the top surface of the second pattern 140 in the outer region OR. According to one embodiment, as the height of the top surface of the first pattern 130 in the outer region OR is formed to be higher than the height of the top surface of the first pattern 130 in the cell region CR, the outer region OR ), the height of the upper surface of the second pattern 140 may be higher than the height of the second pattern 140 in the cell region CR.

According to one embodiment, the second pattern 140 is formed by a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). It can be formed by depositing a conductive material on the first pattern 130.

According to one embodiment, the second pattern 140 may be formed of a different material from the first pattern 130. For example, the second pattern 140 may be a semiconductor pattern including polysilicon doped with P-type or N-type impurities.

Referring to FIG. 10, the second pattern 140 can be deposited so that the gate trench GT is sufficiently filled by controlling the deposition process conditions. Accordingly, the second pattern 140 can cover the first pattern 130 and sufficiently fill the gate trench GT.

As will be described later with reference to FIGS. 11 and 12 , the second pattern 140 may be removed from the outer area OR. Additionally, the second pattern 140 may not be removed from the cell region CR.

Referring to FIGS. 11 and 12 , the second pattern 140 may be polished by performing a planarization process. For example, at least a portion of the second pattern 140 may be removed by performing a chemical mechanical polishing (CMP) process.

According to one embodiment, CMP process conditions for removing the second pattern 140 can be adjusted. For example, polishing pressure, rotation speed, slurry flow rate, and slurry type can be adjusted.

According to one embodiment, the polishing pressure may refer to the pressure applied when the polishing head is brought into contact with the semiconductor substrate. The polishing pressure can be selected depending on the polishing purpose. For example, the polishing pressure may be from about 0.5 psi to about 2.5 psi, but is not limited thereto. In the method of manufacturing a semiconductor device according to the present invention, distribution deterioration can be prevented by performing a planarization process under low pressure conditions.

According to one embodiment, the rotation speed may refer to the speed when the semiconductor substrate and the polishing head rotate while in contact. At this time, the rotation directions of the semiconductor substrate and the polishing head may be in the same direction or in opposite directions. The rotational speed of the polishing head can be selected depending on the purpose. For example, the rotation speed may be from about 10 rpm to about 140 rpm, but is not limited thereto. As described above, in the method of manufacturing a semiconductor device according to the present invention, the rotation speed satisfies the above range, so that the fluidity of the slurry due to centrifugal force can be properly secured.

According to one embodiment, the slurry supply flow rate may refer to the amount of slurry supplied for the planarization process. For example, the slurry may be sprayed through a supply nozzle. The flow rate of slurry sprayed through the supply nozzle can be selected depending on the purpose. For example, the slurry supply flow rate may be from about 50 ml/min to about 500 ml/min, but is not limited thereto.

According to one embodiment, in the planarization process, the second pattern 140 is polished using a slurry containing an abrasive having a high polishing selectivity to either the first pattern 130 or the second pattern 140. You can. Specifically, the planarization process involves chemical mechanical polishing (CMP) of the second pattern 140 using a slurry containing an abrasive having a high polishing selectivity for either the first pattern 130 or the second pattern 140. ) may include the step of.

The slurry used in the planarization process may include abrasive particles, additives, oxidizing agents, dispersants, and pH adjusters. The abrasive particles may include metal oxides, metal oxides coated with organic or inorganic materials, or metal oxides in a colloidal state. For example, abrasive particles include silica, alumina, ceria, titania, zirconia, magnesia, germania, mangania and others. It may include at least one of the combinations, but is not limited thereto. For example, the abrasive particles may include colloidal silica. The shape of the abrasive particles may vary, such as spherical shape, square shape, needle shape, or plate shape.

Below, a case where the abrasive particles include colloidal silica will be described. By using a colloidal silica-based slurry in the method of manufacturing a semiconductor device according to the present invention, deterioration of the semiconductor device can be prevented by preventing scratches from occurring in the first pattern 130 containing a metal material. Additionally, the second pattern 140 containing polysilicon can be polished by using a slurry based on colloidal silica, which has a greater hardness than polysilicon.

The slurry used in the planarization process may have a selectivity. The selectivity ratio may be the ratio of the amount of removal of a specific film material when performing a planarization process using a slurry. According to one embodiment, the slurry may be composed of a composition that relatively further polishes the second pattern 140 made of polysilicon and hardly polishes the first pattern 130 made of a conductive metal material. For example, the selectivity ratio of the polysilicon film to the metal film by the slurry composition may be about 5:1 or more.

According to one embodiment, the second pattern 140 on the outer region OR may be completely removed by performing (or carrying out) a planarization process using a slurry containing abrasive particles. As the second pattern 140 on the outer area OR is removed, the upper surface of the first portion 131 of the first pattern 130 may be exposed in the outer area OR.

According to one embodiment, the planarization process may be performed until the first portion 131 of the first pattern 130 is exposed in the outer area OR. As the first part 131 is exposed in the outer area OR, the surface of the first part 131 may be flattened through a planarization process. Specifically, the upper surface of the first portion 131 may have a surface roughness of about 50 Å or less.

According to one embodiment, the planarization process may include the step of chemical mechanical polishing (CMP) using a slurry to stop the first pattern 130 formed in the outer region OR. Specifically, by using a slurry formed with a composition that polishes polysilicon and does not polish the conductive metal material, the planarization process can be stopped at the first pattern 130 including the metal material. According to one embodiment, the planarization process may be stopped when some portions of the first pattern 130 are exposed. That is, the first pattern 130 can be used as a polishing stopper or a polishing resistive layer in a planarization process.

As described above, in the semiconductor device 10 according to the present specification, the second pattern 140 containing polysilicon is completely removed from the outer region (OR), thereby creating a structure required in the subsequent etch back process. can be formed.

Specifically, by completely removing the second pattern 140 containing polysilicon in the outer region OR, defects caused by polysilicon can be prevented in a subsequent process.

According to one embodiment, as the planarization process is performed, the first portion 131 of the first pattern 130 in the outer area OR may have a uniform height. According to one embodiment, as the planarization process is performed, the second pattern 140 may have a uniform height in the cell region CR.

According to one embodiment, as the planarization process is performed, the step between the outer region (OR) and the cell region (CR) may be minimized. Specifically, the difference between the height of the top surface of the first pattern 130 in the outer area OR and the height of the second pattern 140 in the cell area CR can be minimized. As the planarization process is performed, the height of the top surface of the first pattern 130 in the outer region OR and the height of the second pattern 140 in the cell region CR may become substantially the same.

Referring to FIGS. 13 and 14 , the first pattern 130 and the second pattern 140 may be recessed to a certain depth. That is, a portion of the first pattern 130 and the second pattern 140 can be removed to a predetermined height. The recess process can be performed as an etch-back process. As the etch-back process is performed, a portion of the first portion 131 may be removed to a predetermined height from the outer area OR. Additionally, as the etch-back process is performed, a portion of the second pattern 140 may be removed to a predetermined height from the cell region CR.

According to one embodiment, as the etch-back process is performed, the height (or level) of the top surface of the first portion 131 in the outer area OR may be lowered. Additionally, as the etch-back process is performed, the height of the top surface of the second pattern 140 in the cell region CR may be lowered. According to one embodiment, the height of the top surface of the second pattern 140 may be lower than the height of the top surface of the first portion 131. Accordingly, a step may occur between the cell area (CR) and the outer area (OR).

Referring to FIG. 14 , as an etch-back process is performed to remove a portion of the second pattern 140, the height of the top surface of the second pattern 140 within the gate trench GT may be lowered. Specifically, the height of the top surface of the second pattern 140 may be lower than the height of the top surface of the second pattern 140 of FIG. 12 .

As described above with reference to FIGS. 3 and 4 , the gate capping layer 150 may be formed on the word line WL. For example, the gate capping layer 150 may fill the area of the gate trench GT remaining after the gate insulating layer 121 and the word line WL are recessed.

In the cell region CR, the gate capping layer 150 may fill the gate trench GT at the top of the word line WL. That is, the gate capping layer 150 may cover the second pattern 140 and bury the upper part of the gate trench GT. The gate capping layer 150 may fill the space where the gate insulating layer 121, the first pattern 130, and the second pattern 140 do not fill the gate trench GT.

According to one embodiment, the gate capping layer 150 may be disposed to contact the second pattern 140 in the cell region CR and to contact the first pattern 130 in the outer region OR. The second pattern 140 may be positioned between the second portion 132 of the first pattern 130 and the gate capping layer 150. More specifically, the gate capping layer 150 may contact the second pattern 140 in the cell region (CR) and may contact the first portion 131 having a flat top surface in the outer region (OR).

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims are also possible. It falls within the scope of rights.

10: Semiconductor device
100: substrate
110: device isolation membrane
110A: first device isolation film
110B: second device separator
120: Mask layer
121: Gate insulating layer
130: first pattern
131: Part 1
132: Part 2
140: second pattern
150: gate capping layer
AC: active area
CR: cell region
OR: Outer Area
PR: Peripheral area

Claims (10)

A substrate having a cell region and an outer region surrounding the cell region,
On the substrate, a device isolation film including a first device isolation film located in the outer region and a second device isolation film defining an active region of the cell region, and
a gate structure including a word line extending across the active region in the cell region and over the first device isolation layer in the outer region;
The gate structure is,
a first pattern including a first portion having a flat upper surface in the outer region and a second portion of the cell region;
A semiconductor device comprising a second pattern located on the second portion of the first pattern. In paragraph 1:
The semiconductor device wherein the upper surface of the first portion has a surface roughness of 50 Å or less. In paragraph 1:
A semiconductor device in which the second pattern is disposed on the second portion and the second pattern is not disposed on the first portion. In paragraph 1:
The first portion of the first pattern has a first thickness in a vertical direction,
The second portion of the first pattern has a second thickness that is smaller than the first thickness in a vertical direction. In paragraph 4,
the second pattern has a third thickness in a vertical direction on the second portion,
A semiconductor device wherein the first thickness is greater than or equal to the sum of the second thickness and the third thickness. In paragraph 1:
The gate structure further includes a gate capping layer in contact with the second pattern in the cell region and in contact with the first pattern in the outer region. In paragraph 1:
A semiconductor device wherein the first pattern and the second pattern are made of different materials. Providing a substrate including a cell region and an outer region surrounding the cell region,
etching the substrate to form a device isolation film including a first device isolation film defining the outer region and a second device isolation film defining an active region of the cell region;
forming a first pattern on the substrate, extending across the active region and over the first device isolation layer in the outer region;
forming a second pattern on the first pattern and made of a material different from the first pattern, and
A method of manufacturing a semiconductor device comprising polishing the second pattern in the outer area by performing a planarization process. In paragraph 8:
The step of polishing the second pattern is,
A method of manufacturing a semiconductor device comprising chemically and mechanically polishing the second pattern using a slurry containing an abrasive having a polishing selectivity with respect to the first pattern and the second pattern. In paragraph 9:
The step of polishing the second pattern is,
A method of manufacturing a semiconductor device comprising chemical and mechanical polishing using the slurry to stop polishing at an upper portion of the first pattern formed in the outer region.